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Searched refs:ss_clk (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/crypto/
H A Dallwinner,sun4i-a10-crypto.yaml91 clocks = <&ahb_gates 5>, <&ss_clk>;
/openbmc/linux/drivers/clk/sunxi-ng/
H A Dccu-sun5i.c362 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
571 &ss_clk.common,
698 [CLK_SS] = &ss_clk.common.hw,
831 [CLK_SS] = &ss_clk.common.hw,
942 [CLK_SS] = &ss_clk.common.hw,
H A Dccu-sun8i-a33.c350 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
550 &ss_clk.common,
679 [CLK_SS] = &ss_clk.common.hw,
H A Dccu-sun8i-a83t.c435 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents,
659 &ss_clk.common,
764 [CLK_SS] = &ss_clk.common.hw,
H A Dccu-sun9i-a80.c487 static struct ccu_mp ss_clk = { variable
872 &ss_clk.common,
1018 [CLK_SS] = &ss_clk.common.hw,
H A Dccu-sun4i-a10.c525 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
968 &ss_clk.common,
1155 [CLK_SS] = &ss_clk.common.hw,
1321 [CLK_SS] = &ss_clk.common.hw,
H A Dccu-sun6i-a31.c436 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
892 &ss_clk.common,
1080 [CLK_SS] = &ss_clk.common.hw,
/openbmc/linux/drivers/usb/host/
H A Dxhci-tegra.c279 struct clk *ss_clk; member
838 err = clk_prepare_enable(tegra->ss_clk); in tegra_xusb_clk_enable()
869 clk_disable_unprepare(tegra->ss_clk); in tegra_xusb_clk_enable()
881 clk_disable_unprepare(tegra->ss_clk); in tegra_xusb_clk_disable()
1186 tegra->ss_clk, in tegra_xusb_unpowergate_partitions()
1621 tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss"); in tegra_xusb_probe()
1622 if (IS_ERR(tegra->ss_clk)) { in tegra_xusb_probe()
1623 err = PTR_ERR(tegra->ss_clk); in tegra_xusb_probe()