| /openbmc/u-boot/arch/arm/mach-imx/mx7ulp/ |
| H A D | soc.c | 177 u32 cause1, cause = 0, srs = 0; in get_reset_cause() local
184 srs = readl(reg_srs); in get_reset_cause()
222 debug("[%X] SRS[%X] %X - ", cause1, srs, srs^cause1); in get_reset_cause()
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| /openbmc/linux/drivers/irqchip/ |
| H A D | irq-ls-scfg-msi.c | 41 unsigned int srs; /* Shared interrupt register select */ member
208 msir->srs; in ls_scfg_msi_irq_handler()
272 msir->srs = 0; /* This value is determined by the CPU */ in ls_scfg_msi_setup_hwirq()
274 msir->srs = index; in ls_scfg_msi_setup_hwirq()
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| /openbmc/qemu/target/arm/tcg/ |
| H A D | a32-uncond.decode | 38 &srs mode w pu
42 SRS 1111 100 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs
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| H A D | t32.decode | 693 &srs !extern mode w pu
694 @srs .... .... .. w:1 . .... ........... mode:5 &srs
696 SRS 1110 1000 00.0 1101 1100 0000 000. .... @srs pu=2
697 SRS 1110 1001 10.0 1101 1100 0000 000. .... @srs pu=1
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| /openbmc/qemu/hw/intc/ |
| H A D | openpic.c | 886 int srs, ibs; in openpic_msi_write() local
896 srs = val >> MSIIR_SRS_SHIFT; in openpic_msi_write()
897 idx += srs; in openpic_msi_write()
899 opp->msi[srs].msir |= 1 << ibs; in openpic_msi_write()
912 int i, srs; in openpic_msi_read() local
919 srs = addr >> 4; in openpic_msi_read()
930 r = opp->msi[srs].msir; in openpic_msi_read()
932 opp->msi[srs].msir = 0; in openpic_msi_read()
933 openpic_set_irq(opp, opp->irq_msi + srs, 0); in openpic_msi_read()
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| /openbmc/linux/arch/powerpc/kvm/ |
| H A D | mpic.c | 944 int srs, ibs; in openpic_msi_write() local
952 srs = val >> MSIIR_SRS_SHIFT; in openpic_msi_write()
953 idx += srs; in openpic_msi_write()
955 opp->msi[srs].msir |= 1 << ibs; in openpic_msi_write()
970 int i, srs; in openpic_msi_read() local
976 srs = addr >> 4; in openpic_msi_read()
987 r = opp->msi[srs].msir; in openpic_msi_read()
989 opp->msi[srs].msir = 0; in openpic_msi_read()
990 openpic_set_irq(opp, opp->irq_msi + srs, 0); in openpic_msi_read()
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| /openbmc/linux/arch/powerpc/sysdev/ |
| H A D | fsl_msi.c | 71 int cascade_virq, srs; in fsl_msi_print_chip() local
73 srs = (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK; in fsl_msi_print_chip()
74 cascade_virq = msi_data->cascade_array[srs]->virq; in fsl_msi_print_chip()
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| /openbmc/linux/drivers/iommu/intel/ |
| H A D | cap_audit.c | 62 CHECK_FEATURE_MISMATCH(a, b, ecap, srs, ECAP_SRS_MASK); in check_dmar_capabilities()
108 CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, srs, ECAP_SRS_MASK); in cap_audit_hotplug()
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| /openbmc/linux/arch/mips/kernel/ |
| H A D | traps.c | 2064 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) in set_vi_srs_handler() argument
2076 srs = 0; in set_vi_srs_handler()
2083 if (srs >= srssets) in set_vi_srs_handler()
2084 panic("Shadow register set %d not supported", srs); in set_vi_srs_handler()
2088 board_bind_eic_interrupt(n, srs); in set_vi_srs_handler()
2092 change_c0_srsmap(0xf << n*4, srs << n*4); in set_vi_srs_handler()
2095 if (srs == 0) { in set_vi_srs_handler()
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| /openbmc/linux/sound/soc/codecs/ |
| H A D | wm8995.c | 1529 static const int srs[] = { variable
1614 for (i = 0; i < ARRAY_SIZE(srs); ++i) in wm8995_hw_params()
1615 if (srs[i] == params_rate(params)) in wm8995_hw_params()
1617 if (i == ARRAY_SIZE(srs)) { in wm8995_hw_params()
1624 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i]); in wm8995_hw_params()
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| H A D | wm8994.c | 2886 } srs[] = { variable
3002 for (i = 0; i < ARRAY_SIZE(srs); i++) in wm8994_hw_params()
3003 if (srs[i].rate == params_rate(params)) in wm8994_hw_params()
3005 if (i == ARRAY_SIZE(srs)) in wm8994_hw_params()
3007 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT; in wm8994_hw_params()
3009 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate); in wm8994_hw_params()
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| /openbmc/qemu/target/s390x/ |
| H A D | cpu_features_def.h.inc | 31 DEF_FEAT(SENSE_RUNNING_STATUS, "srs", STFL, 9, "Sense-running-status facility")
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