Searched refs:src_mask (Results 1 – 5 of 5) sorted by relevance
58 VMSTATE_UINT8(src_mask, CombinerGroupState),111 val |= s->group[grp_quad_base_n].src_mask & in exynos4210_combiner_read()113 val |= (s->group[grp_quad_base_n + 1].src_mask & in exynos4210_combiner_read()115 val |= (s->group[grp_quad_base_n + 2].src_mask & in exynos4210_combiner_read()117 val |= (s->group[grp_quad_base_n + 3].src_mask & in exynos4210_combiner_read()136 if (s->group[group_n].src_mask & s->group[group_n].src_pending) { in exynos4210_combiner_update()217 s->group[grp_quad_base_n].src_mask |= val & 0xFF; in exynos4210_combiner_write()218 s->group[grp_quad_base_n + 1].src_mask |= (val & 0xFF00) >> 8; in exynos4210_combiner_write()219 s->group[grp_quad_base_n + 2].src_mask |= (val & 0xFF0000) >> 16; in exynos4210_combiner_write()220 s->group[grp_quad_base_n + 3].src_mask |= (val & 0xFF000000) >> 24; in exynos4210_combiner_write()[all …]
32 uint8_t src_mask; /* 1 - source enabled, 0 - disabled */ member
493 data &= ahc->src_mask; in aspeed_hace_write()662 ahc->src_mask = 0x0FFFFFFF; in aspeed_ast2400_hace_class_init()682 ahc->src_mask = 0x3fffffff; in aspeed_ast2500_hace_class_init()702 ahc->src_mask = 0x7FFFFFFF; in aspeed_ast2600_hace_class_init()722 ahc->src_mask = 0x7FFFFFFF; in aspeed_ast1030_hace_class_init()742 ahc->src_mask = 0x7FFFFFFF; in aspeed_ast2700_hace_class_init()
47 uint32_t src_mask; member
22 int32_t src_mask; member433 src = (src >> bit_info->src_bit) & bit_info->src_mask; in exynos5_get_periph_rate()524 src = (src >> bit_info->src_bit) & bit_info->src_mask; in exynos542x_get_periph_rate()