Searched refs:spllcsr (Results 1 – 2 of 2) sorted by relevance
480 reg = readl(&scg1_regs->spllcsr); in decode_pll()852 val = readl(&scg1_regs->spllcsr); in scg_a7_spll_init()854 writel(val, &scg1_regs->spllcsr); in scg_a7_spll_init()879 val = readl(&scg1_regs->spllcsr); in scg_a7_spll_init()881 writel(val, &scg1_regs->spllcsr); in scg_a7_spll_init()884 while (!(readl(&scg1_regs->spllcsr) & SCG_SPLL_CSR_SPLLVLD_MASK)) in scg_a7_spll_init()
310 u32 spllcsr; /* System PLL Control Status Register, offset 0x600 */ member