1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SH QSPI (Quad SPI) driver
4 *
5 * Copyright (C) 2013 Renesas Electronics Corporation
6 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
7 */
8
9 #include <common.h>
10 #include <console.h>
11 #include <malloc.h>
12 #include <spi.h>
13 #include <wait_bit.h>
14 #include <asm/arch/rmobile.h>
15 #include <asm/io.h>
16
17 /* SH QSPI register bit masks <REG>_<BIT> */
18 #define SPCR_MSTR 0x08
19 #define SPCR_SPE 0x40
20 #define SPSR_SPRFF 0x80
21 #define SPSR_SPTEF 0x20
22 #define SPPCR_IO3FV 0x04
23 #define SPPCR_IO2FV 0x02
24 #define SPPCR_IO1FV 0x01
25 #define SPBDCR_RXBC0 BIT(0)
26 #define SPCMD_SCKDEN BIT(15)
27 #define SPCMD_SLNDEN BIT(14)
28 #define SPCMD_SPNDEN BIT(13)
29 #define SPCMD_SSLKP BIT(7)
30 #define SPCMD_BRDV0 BIT(2)
31 #define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \
32 SPCMD_SPNDEN | SPCMD_SSLKP | \
33 SPCMD_BRDV0
34 #define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \
35 SPCMD_BRDV0
36 #define SPBFCR_TXRST BIT(7)
37 #define SPBFCR_RXRST BIT(6)
38 #define SPBFCR_TXTRG 0x30
39 #define SPBFCR_RXTRG 0x07
40
41 /* SH QSPI register set */
42 struct sh_qspi_regs {
43 u8 spcr;
44 u8 sslp;
45 u8 sppcr;
46 u8 spsr;
47 u32 spdr;
48 u8 spscr;
49 u8 spssr;
50 u8 spbr;
51 u8 spdcr;
52 u8 spckd;
53 u8 sslnd;
54 u8 spnd;
55 u8 dummy0;
56 u16 spcmd0;
57 u16 spcmd1;
58 u16 spcmd2;
59 u16 spcmd3;
60 u8 spbfcr;
61 u8 dummy1;
62 u16 spbdcr;
63 u32 spbmul0;
64 u32 spbmul1;
65 u32 spbmul2;
66 u32 spbmul3;
67 };
68
69 struct sh_qspi_slave {
70 #ifndef CONFIG_DM_SPI
71 struct spi_slave slave;
72 #endif
73 struct sh_qspi_regs *regs;
74 };
75
sh_qspi_init(struct sh_qspi_slave * ss)76 static void sh_qspi_init(struct sh_qspi_slave *ss)
77 {
78 /* QSPI initialize */
79 /* Set master mode only */
80 writeb(SPCR_MSTR, &ss->regs->spcr);
81
82 /* Set SSL signal level */
83 writeb(0x00, &ss->regs->sslp);
84
85 /* Set MOSI signal value when transfer is in idle state */
86 writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr);
87
88 /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
89 writeb(0x01, &ss->regs->spbr);
90
91 /* Disable Dummy Data Transmission */
92 writeb(0x00, &ss->regs->spdcr);
93
94 /* Set clock delay value */
95 writeb(0x00, &ss->regs->spckd);
96
97 /* Set SSL negation delay value */
98 writeb(0x00, &ss->regs->sslnd);
99
100 /* Set next-access delay value */
101 writeb(0x00, &ss->regs->spnd);
102
103 /* Set equence command */
104 writew(SPCMD_INIT2, &ss->regs->spcmd0);
105
106 /* Reset transfer and receive Buffer */
107 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
108
109 /* Clear transfer and receive Buffer control bit */
110 clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
111
112 /* Set equence control method. Use equence0 only */
113 writeb(0x00, &ss->regs->spscr);
114
115 /* Enable SPI function */
116 setbits_8(&ss->regs->spcr, SPCR_SPE);
117 }
118
sh_qspi_cs_activate(struct sh_qspi_slave * ss)119 static void sh_qspi_cs_activate(struct sh_qspi_slave *ss)
120 {
121 /* Set master mode only */
122 writeb(SPCR_MSTR, &ss->regs->spcr);
123
124 /* Set command */
125 writew(SPCMD_INIT1, &ss->regs->spcmd0);
126
127 /* Reset transfer and receive Buffer */
128 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
129
130 /* Clear transfer and receive Buffer control bit */
131 clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
132
133 /* Set equence control method. Use equence0 only */
134 writeb(0x00, &ss->regs->spscr);
135
136 /* Enable SPI function */
137 setbits_8(&ss->regs->spcr, SPCR_SPE);
138 }
139
sh_qspi_cs_deactivate(struct sh_qspi_slave * ss)140 static void sh_qspi_cs_deactivate(struct sh_qspi_slave *ss)
141 {
142 /* Disable SPI Function */
143 clrbits_8(&ss->regs->spcr, SPCR_SPE);
144 }
145
sh_qspi_xfer_common(struct sh_qspi_slave * ss,unsigned int bitlen,const void * dout,void * din,unsigned long flags)146 static int sh_qspi_xfer_common(struct sh_qspi_slave *ss, unsigned int bitlen,
147 const void *dout, void *din, unsigned long flags)
148 {
149 u32 nbyte, chunk;
150 int i, ret = 0;
151 u8 dtdata = 0, drdata;
152 u8 *tdata = &dtdata, *rdata = &drdata;
153 u32 *spbmul0 = &ss->regs->spbmul0;
154
155 if (dout == NULL && din == NULL) {
156 if (flags & SPI_XFER_END)
157 sh_qspi_cs_deactivate(ss);
158 return 0;
159 }
160
161 if (bitlen % 8) {
162 printf("%s: bitlen is not 8bit alined %d", __func__, bitlen);
163 return 1;
164 }
165
166 nbyte = bitlen / 8;
167
168 if (flags & SPI_XFER_BEGIN) {
169 sh_qspi_cs_activate(ss);
170
171 /* Set 1048576 byte */
172 writel(0x100000, spbmul0);
173 }
174
175 if (flags & SPI_XFER_END)
176 writel(nbyte, spbmul0);
177
178 if (dout != NULL)
179 tdata = (u8 *)dout;
180
181 if (din != NULL)
182 rdata = din;
183
184 while (nbyte > 0) {
185 /*
186 * Check if there is 32 Byte chunk and if there is, transfer
187 * it in one burst, otherwise transfer on byte-by-byte basis.
188 */
189 chunk = (nbyte >= 32) ? 32 : 1;
190
191 clrsetbits_8(&ss->regs->spbfcr, SPBFCR_TXTRG | SPBFCR_RXTRG,
192 chunk == 32 ? SPBFCR_TXTRG | SPBFCR_RXTRG : 0);
193
194 ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPTEF,
195 true, 1000, true);
196 if (ret)
197 return ret;
198
199 for (i = 0; i < chunk; i++) {
200 writeb(*tdata, &ss->regs->spdr);
201 if (dout != NULL)
202 tdata++;
203 }
204
205 ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPRFF,
206 true, 1000, true);
207 if (ret)
208 return ret;
209
210 for (i = 0; i < chunk; i++) {
211 *rdata = readb(&ss->regs->spdr);
212 if (din != NULL)
213 rdata++;
214 }
215
216 nbyte -= chunk;
217 }
218
219 if (flags & SPI_XFER_END)
220 sh_qspi_cs_deactivate(ss);
221
222 return ret;
223 }
224
225 #ifndef CONFIG_DM_SPI
to_sh_qspi(struct spi_slave * slave)226 static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave)
227 {
228 return container_of(slave, struct sh_qspi_slave, slave);
229 }
230
spi_cs_is_valid(unsigned int bus,unsigned int cs)231 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
232 {
233 return 1;
234 }
235
spi_cs_activate(struct spi_slave * slave)236 void spi_cs_activate(struct spi_slave *slave)
237 {
238 struct sh_qspi_slave *ss = to_sh_qspi(slave);
239
240 sh_qspi_cs_activate(ss);
241 }
242
spi_cs_deactivate(struct spi_slave * slave)243 void spi_cs_deactivate(struct spi_slave *slave)
244 {
245 struct sh_qspi_slave *ss = to_sh_qspi(slave);
246
247 sh_qspi_cs_deactivate(ss);
248 }
249
spi_setup_slave(unsigned int bus,unsigned int cs,unsigned int max_hz,unsigned int mode)250 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
251 unsigned int max_hz, unsigned int mode)
252 {
253 struct sh_qspi_slave *ss;
254
255 if (!spi_cs_is_valid(bus, cs))
256 return NULL;
257
258 ss = spi_alloc_slave(struct sh_qspi_slave, bus, cs);
259 if (!ss) {
260 printf("SPI_error: Fail to allocate sh_qspi_slave\n");
261 return NULL;
262 }
263
264 ss->regs = (struct sh_qspi_regs *)SH_QSPI_BASE;
265
266 /* Init SH QSPI */
267 sh_qspi_init(ss);
268
269 return &ss->slave;
270 }
271
spi_free_slave(struct spi_slave * slave)272 void spi_free_slave(struct spi_slave *slave)
273 {
274 struct sh_qspi_slave *spi = to_sh_qspi(slave);
275
276 free(spi);
277 }
278
spi_claim_bus(struct spi_slave * slave)279 int spi_claim_bus(struct spi_slave *slave)
280 {
281 return 0;
282 }
283
spi_release_bus(struct spi_slave * slave)284 void spi_release_bus(struct spi_slave *slave)
285 {
286 }
287
spi_xfer(struct spi_slave * slave,unsigned int bitlen,const void * dout,void * din,unsigned long flags)288 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
289 const void *dout, void *din, unsigned long flags)
290 {
291 struct sh_qspi_slave *ss = to_sh_qspi(slave);
292
293 return sh_qspi_xfer_common(ss, bitlen, dout, din, flags);
294 }
295
296 #else
297
298 #include <dm.h>
299
sh_qspi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)300 static int sh_qspi_xfer(struct udevice *dev, unsigned int bitlen,
301 const void *dout, void *din, unsigned long flags)
302 {
303 struct udevice *bus = dev->parent;
304 struct sh_qspi_slave *ss = dev_get_platdata(bus);
305
306 return sh_qspi_xfer_common(ss, bitlen, dout, din, flags);
307 }
308
sh_qspi_set_speed(struct udevice * dev,uint speed)309 static int sh_qspi_set_speed(struct udevice *dev, uint speed)
310 {
311 /* This is a SPI NOR controller, do nothing. */
312 return 0;
313 }
314
sh_qspi_set_mode(struct udevice * dev,uint mode)315 static int sh_qspi_set_mode(struct udevice *dev, uint mode)
316 {
317 /* This is a SPI NOR controller, do nothing. */
318 return 0;
319 }
320
sh_qspi_probe(struct udevice * dev)321 static int sh_qspi_probe(struct udevice *dev)
322 {
323 struct sh_qspi_slave *ss = dev_get_platdata(dev);
324
325 sh_qspi_init(ss);
326
327 return 0;
328 }
329
sh_qspi_ofdata_to_platdata(struct udevice * dev)330 static int sh_qspi_ofdata_to_platdata(struct udevice *dev)
331 {
332 struct sh_qspi_slave *plat = dev_get_platdata(dev);
333
334 plat->regs = (struct sh_qspi_regs *)dev_read_addr(dev);
335
336 return 0;
337 }
338
339 static const struct dm_spi_ops sh_qspi_ops = {
340 .xfer = sh_qspi_xfer,
341 .set_speed = sh_qspi_set_speed,
342 .set_mode = sh_qspi_set_mode,
343 };
344
345 static const struct udevice_id sh_qspi_ids[] = {
346 { .compatible = "renesas,qspi" },
347 { }
348 };
349
350 U_BOOT_DRIVER(sh_qspi) = {
351 .name = "sh_qspi",
352 .id = UCLASS_SPI,
353 .of_match = sh_qspi_ids,
354 .ops = &sh_qspi_ops,
355 .ofdata_to_platdata = sh_qspi_ofdata_to_platdata,
356 .platdata_auto_alloc_size = sizeof(struct sh_qspi_slave),
357 .probe = sh_qspi_probe,
358 };
359 #endif
360