1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * ASPEED AST2500 FMC/SPI Controller driver
4 *
5 * Copyright (c) 2015-2018, IBM Corporation.
6 */
7
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10 #include <common.h>
11 #include <clk.h>
12 #include <dm.h>
13 #include <spi.h>
14 #include <spi_flash.h>
15 #include <asm/io.h>
16 #include <linux/ioport.h>
17 #include <malloc.h>
18
19 #define ASPEED_SPI_MAX_CS 3
20 #define FLASH_CALIBRATION_LEN 0x400
21
22 struct aspeed_spi_regs {
23 u32 conf; /* 0x00 CE Type Setting */
24 u32 ctrl; /* 0x04 Control */
25 u32 intr_ctrl; /* 0x08 Interrupt Control and Status */
26 u32 cmd_ctrl; /* 0x0c Command Control */
27 u32 ce_ctrl[ASPEED_SPI_MAX_CS]; /* 0x10 .. 0x18 CEx Control */
28 u32 _reserved0[5]; /* .. */
29 u32 segment_addr[ASPEED_SPI_MAX_CS];
30 /* 0x30 .. 0x38 Segment Address */
31 u32 _reserved1[5]; /* .. */
32 u32 soft_rst_cmd_ctrl; /* 0x50 Auto Soft-Reset Command Control */
33 u32 _reserved2[4]; /* .. */
34 u32 fmc_wdt2_ctrl; /* 0x64 FMC_WDT2 control */
35 u32 _reserved3[6]; /* .. */
36 u32 dma_ctrl; /* 0x80 DMA Control/Status */
37 u32 dma_flash_addr; /* 0x84 DMA Flash Side Address */
38 u32 dma_dram_addr; /* 0x88 DMA DRAM Side Address */
39 u32 dma_len; /* 0x8c DMA Length Register */
40 u32 dma_checksum; /* 0x90 Checksum Calculation Result */
41 u32 timings; /* 0x94 Read Timing Compensation */
42 u32 _reserved4[1];
43 /* not used */
44 u32 soft_strap_status; /* 0x9c Software Strap Status */
45 u32 write_cmd_filter_ctrl; /* 0xa0 Write Command Filter Control */
46 u32 write_addr_filter_ctrl; /* 0xa4 Write Address Filter Control */
47 u32 lock_ctrl_reset; /* 0xa8 Lock Control (SRST#) */
48 u32 lock_ctrl_wdt; /* 0xac Lock Control (Watchdog) */
49 u32 write_addr_filter[8]; /* 0xb0 Write Address Filter */
50 u32 _reserved5[12];
51 u32 fully_qualified_cmd[20]; /* 0x100 Fully Qualified Command */
52 u32 addr_qualified_cmd[12]; /* 0x150 Address Qualified Command */
53 };
54
55 /* CE Type Setting Register */
56 #define CONF_ENABLE_W2 BIT(18)
57 #define CONF_ENABLE_W1 BIT(17)
58 #define CONF_ENABLE_W0 BIT(16)
59 #define CONF_FLASH_TYPE2 4
60 #define CONF_FLASH_TYPE1 2 /* Hardwired to SPI */
61 #define CONF_FLASH_TYPE0 0 /* Hardwired to SPI */
62 #define CONF_FLASH_TYPE_NOR 0x0
63 #define CONF_FLASH_TYPE_SPI 0x2
64
65 /* CE Control Register */
66 #define CTRL_EXTENDED2 BIT(2) /* 32 bit addressing for SPI */
67 #define CTRL_EXTENDED1 BIT(1) /* 32 bit addressing for SPI */
68 #define CTRL_EXTENDED0 BIT(0) /* 32 bit addressing for SPI */
69
70 /* Interrupt Control and Status Register */
71 #define INTR_CTRL_DMA_STATUS BIT(11)
72 #define INTR_CTRL_CMD_ABORT_STATUS BIT(10)
73 #define INTR_CTRL_WRITE_PROTECT_STATUS BIT(9)
74 #define INTR_CTRL_DMA_EN BIT(3)
75 #define INTR_CTRL_CMD_ABORT_EN BIT(2)
76 #define INTR_CTRL_WRITE_PROTECT_EN BIT(1)
77
78 /* CEx Control Register */
79 #define CE_CTRL_IO_MODE_MASK GENMASK(31, 28)
80 #define CE_CTRL_IO_QPI_DATA BIT(31)
81 #define CE_CTRL_IO_DUAL_DATA BIT(29)
82 #define CE_CTRL_IO_SINGLE 0
83 #define CE_CTRL_IO_DUAL_ADDR_DATA (BIT(29) | BIT(28))
84 #define CE_CTRL_IO_QUAD_DATA BIT(30)
85 #define CE_CTRL_IO_QUAD_ADDR_DATA (BIT(30) | BIT(28))
86 #define CE_CTRL_CMD_SHIFT 16
87 #define CE_CTRL_CMD_MASK 0xff
88 #define CE_CTRL_CMD(cmd) \
89 (((cmd) & CE_CTRL_CMD_MASK) << CE_CTRL_CMD_SHIFT)
90 #define CE_CTRL_DUMMY_HIGH_SHIFT 14
91 #define CE_CTRL_DUMMY_HIGH_MASK 0x1
92 #define CE_CTRL_CLOCK_FREQ_SHIFT 8
93 #define CE_CTRL_CLOCK_FREQ_MASK 0xf
94 #define CE_CTRL_CLOCK_FREQ(div) \
95 (((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT)
96 #define CE_G6_CTRL_CLOCK_FREQ(div) \
97 ((((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT) | (((div) & 0xf0) << 20))
98 #define CE_CTRL_DUMMY_LOW_SHIFT 6 /* 2 bits [7:6] */
99 #define CE_CTRL_DUMMY_LOW_MASK 0x3
100 #define CE_CTRL_DUMMY(dummy) \
101 (((((dummy) >> 2) & CE_CTRL_DUMMY_HIGH_MASK) \
102 << CE_CTRL_DUMMY_HIGH_SHIFT) | \
103 (((dummy) & CE_CTRL_DUMMY_LOW_MASK) << CE_CTRL_DUMMY_LOW_SHIFT))
104 #define CE_CTRL_STOP_ACTIVE BIT(2)
105 #define CE_CTRL_MODE_MASK 0x3
106 #define CE_CTRL_READMODE 0x0
107 #define CE_CTRL_FREADMODE 0x1
108 #define CE_CTRL_WRITEMODE 0x2
109 #define CE_CTRL_USERMODE 0x3
110 #define CE_CTRL_FREQ_MASK 0xf0fff0ff
111
112 #define SPI_READ_FROM_FLASH 0x00000001
113 #define SPI_WRITE_TO_FLASH 0x00000002
114
115 /* Auto Soft-Reset Command Control */
116 #define SOFT_RST_CMD_EN GENMASK(1, 0)
117
118 /*
119 * The Segment Register uses a 8MB unit to encode the start address
120 * and the end address of the AHB window of a SPI flash device.
121 * Default segment addresses are :
122 *
123 * CE0 0x20000000 - 0x2fffffff 128MB
124 * CE1 0x28000000 - 0x29ffffff 32MB
125 * CE2 0x2a000000 - 0x2bffffff 32MB
126 *
127 * The full address space of the AHB window of the controller is
128 * covered and CE0 start address and CE2 end addresses are read-only.
129 */
130 #define SEGMENT_ADDR_START(reg) ((((reg) >> 16) & 0xff) << 23)
131 #define SEGMENT_ADDR_END(reg) ((((reg) >> 24) & 0xff) << 23)
132 #define SEGMENT_ADDR_VALUE(start, end) \
133 (((((start) >> 23) & 0xff) << 16) | ((((end) >> 23) & 0xff) << 24))
134
135 #define G6_SEGMENT_ADDR_START(reg) (((reg) << 16) & 0x0ff00000)
136 #define G6_SEGMENT_ADDR_END(reg) (((reg) & 0x0ff00000) + 0x100000)
137 #define G6_SEGMENT_ADDR_VALUE(start, end) \
138 ((((start) & 0x0ff00000) >> 16) | (((end) - 0x100000) & 0xffff0000))
139
140 /* DMA Control/Status Register */
141 #define DMA_CTRL_DELAY_SHIFT 8
142 #define DMA_CTRL_DELAY_MASK 0xf
143 #define G6_DMA_CTRL_DELAY_MASK 0xff
144 #define DMA_CTRL_FREQ_SHIFT 4
145 #define G6_DMA_CTRL_FREQ_SHIFT 16
146
147 #define DMA_CTRL_FREQ_MASK 0xf
148 #define TIMING_MASK(div, delay) \
149 (((delay & DMA_CTRL_DELAY_MASK) << DMA_CTRL_DELAY_SHIFT) | \
150 ((div & DMA_CTRL_FREQ_MASK) << DMA_CTRL_FREQ_SHIFT))
151 #define G6_TIMING_MASK(div, delay) \
152 (((delay & G6_DMA_CTRL_DELAY_MASK) << DMA_CTRL_DELAY_SHIFT) | \
153 ((div & DMA_CTRL_FREQ_MASK) << G6_DMA_CTRL_FREQ_SHIFT))
154 #define DAM_CTRL_REQUEST BIT(31)
155 #define DAM_CTRL_GRANT BIT(30)
156 #define DMA_CTRL_CALIB BIT(3)
157 #define DMA_CTRL_CKSUM BIT(2)
158 #define DMA_CTRL_WRITE BIT(1)
159 #define DMA_CTRL_ENABLE BIT(0)
160
161 #define DMA_GET_REQ_MAGIC 0xaeed0000
162 #define DMA_DISCARD_REQ_MAGIC 0xdeea0000
163
164 /* for ast2600 setting */
165 #define SPI_3B_AUTO_CLR_REG 0x1e6e2510
166 #define SPI_3B_AUTO_CLR BIT(9)
167
168 /* FMC_WDT2 control register */
169 #define FMC_WDT2_ENABLE BIT(0)
170 /*
171 * flash related info
172 */
173 struct aspeed_spi_flash {
174 u8 cs;
175 /* Initialized when the SPI bus is
176 * first claimed
177 */
178 bool init;
179 void __iomem *ahb_base; /* AHB Window for this device */
180 u32 ahb_size; /* AHB Window segment size */
181 u32 ce_ctrl_user; /* CE Control Register for USER mode */
182 u32 ce_ctrl_fread; /* CE Control Register for FREAD mode */
183 u32 read_iomode;
184 u32 write_iomode;
185 u32 max_freq;
186 struct spi_flash *spi; /* Associated SPI Flash device */
187 };
188
189 enum aspeed_spi_dir {
190 ASPEED_SPI_DIR_IN,
191 ASPEED_SPI_DIR_OUT,
192 };
193
194 #define ASPEED_SPI_OP_CMD(__opcode) \
195 { \
196 .opcode = __opcode, \
197 }
198
199 #define ASPEED_SPI_OP_ADDR(__nbytes, __val) \
200 { \
201 .nbytes = __nbytes, \
202 .val = __val, \
203 }
204
205 #define ASPEED_SPI_OP_NO_ADDR { }
206
207 #define ASPEED_SPI_OP_DUMMY(__nbytes) \
208 { \
209 .nbytes = __nbytes, \
210 }
211
212 #define ASPEED_SPI_OP_NO_DUMMY { }
213
214 #define ASPEED_SPI_OP_DATA_IN(__nbytes, __buf) \
215 { \
216 .dir = ASPEED_SPI_DIR_IN, \
217 .nbytes = __nbytes, \
218 .buf.in = __buf, \
219 }
220
221 #define ASPEED_SPI_OP_DATA_OUT(__nbytes, __buf) \
222 { \
223 .dir = ASPEED_SPI_DIR_OUT, \
224 .nbytes = __nbytes, \
225 .buf.out = __buf, \
226 }
227
228 #define ASPEED_SPI_OP_NO_DATA { }
229
230 #define ASPEED_SPI_OP(__io_mode, __cmd, __addr, __dummy, __data) \
231 { \
232 .io_mode = __io_mode, \
233 .cmd = __cmd, \
234 .addr = __addr, \
235 .dummy = __dummy, \
236 .data = __data, \
237 }
238
239 struct aspeed_spi_op {
240 u32 io_mode;
241
242 struct {
243 u16 opcode;
244 } cmd;
245
246 struct {
247 u8 nbytes;
248 u32 val;
249 } addr;
250
251 struct {
252 u8 nbytes;
253 } dummy;
254
255 struct {
256 enum aspeed_spi_dir dir;
257 unsigned int nbytes;
258 union {
259 void *in;
260 const void *out;
261 } buf;
262 } data;
263 };
264
265 struct aspeed_spi_priv {
266 struct aspeed_spi_regs *regs;
267 void __iomem *ahb_base; /* AHB Window for all flash devices */
268 int new_ver;
269 u32 ahb_size; /* AHB Window segments size */
270 ulong hclk_rate; /* AHB clock rate */
271 u8 num_cs;
272 bool is_fmc;
273 bool disable_fmc_wdt2;
274
275 struct aspeed_spi_flash flashes[ASPEED_SPI_MAX_CS];
276 u32 flash_count;
277
278 u8 cmd_buf[16]; /* SPI command in progress */
279 size_t cmd_len;
280 u8 *tmp_buf;
281 int (*spi_exec_op_cmd)(struct aspeed_spi_priv *priv,
282 struct aspeed_spi_flash *flash,
283 struct aspeed_spi_op *op);
284 };
285
286 static u32 aspeed_spi_flash_to_addr(struct aspeed_spi_flash *flash,
287 const u8 *cmdbuf, unsigned int cmdlen);
288
aspeed_spi_get_flash(struct udevice * dev)289 static struct aspeed_spi_flash *aspeed_spi_get_flash(struct udevice *dev)
290 {
291 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
292 struct aspeed_spi_priv *priv = dev_get_priv(dev->parent);
293 u8 cs = slave_plat->cs;
294
295 if (cs >= priv->flash_count) {
296 pr_err("invalid CS %u\n", cs);
297 return NULL;
298 }
299
300 return &priv->flashes[cs];
301 }
302
aspeed_g6_spi_hclk_divisor(struct aspeed_spi_priv * priv,u32 max_hz)303 static u32 aspeed_g6_spi_hclk_divisor(struct aspeed_spi_priv *priv, u32 max_hz)
304 {
305 u32 hclk_rate = priv->hclk_rate;
306 /* HCLK/1 .. HCLK/16 */
307 const u8 hclk_masks[] = {
308 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0
309 };
310 u8 hclk_div = 0x4; /* default value */
311 bool found = false;
312 u32 i, j = 0;
313
314 /* FMC/SPIR10[27:24] */
315 for (j = 0; j < 0xf; j++) {
316 for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) {
317 if (i == 0 && j == 0)
318 continue;
319
320 if ((hclk_rate / ((i + 1) + j * 16)) <= max_hz) {
321 found = 1;
322 break;
323 }
324 }
325
326 if (found)
327 break;
328 }
329
330 debug("hclk=%d required=%d h_div %d, divisor is %d (mask %x) speed=%d\n",
331 hclk_rate, max_hz, j, i + 1, hclk_masks[i], hclk_rate / (i + 1 + j * 16));
332
333 hclk_div = ((j << 4) | hclk_masks[i]);
334
335 return hclk_div;
336 }
337
aspeed_spi_hclk_divisor(struct aspeed_spi_priv * priv,u32 max_hz)338 static u32 aspeed_spi_hclk_divisor(struct aspeed_spi_priv *priv, u32 max_hz)
339 {
340 u32 hclk_rate = priv->hclk_rate;
341 /* HCLK/1 .. HCLK/16 */
342 const u8 hclk_masks[] = {
343 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0
344 };
345 u32 i;
346 u32 hclk_div_setting = 0;
347
348 for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) {
349 if (max_hz >= (hclk_rate / (i + 1)))
350 break;
351 }
352 debug("hclk=%d required=%d divisor is %d (mask %x) speed=%d\n",
353 hclk_rate, max_hz, i + 1, hclk_masks[i], hclk_rate / (i + 1));
354
355 hclk_div_setting = hclk_masks[i];
356
357 return hclk_div_setting;
358 }
359
360 /*
361 * Use some address/size under the first flash device CE0
362 */
aspeed_spi_fmc_checksum(struct aspeed_spi_priv * priv,struct aspeed_spi_flash * flash,u8 div,u8 delay)363 static u32 aspeed_spi_fmc_checksum(struct aspeed_spi_priv *priv,
364 struct aspeed_spi_flash *flash,
365 u8 div, u8 delay)
366 {
367 u32 flash_addr = (u32)flash->ahb_base + 0x10000;
368 u32 dma_ctrl;
369 u32 checksum;
370
371 writel(flash_addr, &priv->regs->dma_flash_addr);
372 writel(FLASH_CALIBRATION_LEN, &priv->regs->dma_len);
373
374 /*
375 * When doing calibration, the SPI clock rate in the CE0
376 * Control Register and the data input delay cycles in the
377 * Read Timing Compensation Register are replaced by bit[11:4].
378 */
379 dma_ctrl = DMA_CTRL_ENABLE | DMA_CTRL_CKSUM | DMA_CTRL_CALIB |
380 TIMING_MASK(div, delay);
381
382 writel(dma_ctrl, &priv->regs->dma_ctrl);
383 while (!(readl(&priv->regs->intr_ctrl) & INTR_CTRL_DMA_STATUS))
384 ;
385
386 writel(0x0, &priv->regs->intr_ctrl);
387
388 checksum = readl(&priv->regs->dma_checksum);
389
390 writel(0x0, &priv->regs->dma_ctrl);
391 return checksum;
392 }
393
394 /*
395 * Use some address/size under the first flash device CE0
396 */
aspeed_g6_spi_fmc_checksum(struct aspeed_spi_priv * priv,struct aspeed_spi_flash * flash,u8 div,u8 delay)397 static u32 aspeed_g6_spi_fmc_checksum(struct aspeed_spi_priv *priv,
398 struct aspeed_spi_flash *flash,
399 u8 div, u8 delay)
400 {
401 u32 flash_addr = (u32)flash->ahb_base;
402 u32 dma_ctrl;
403 u32 checksum;
404
405 writel(DMA_GET_REQ_MAGIC, &priv->regs->dma_ctrl);
406 if (readl(&priv->regs->dma_ctrl) & DAM_CTRL_REQUEST) {
407 while (!(readl(&priv->regs->dma_ctrl) & DAM_CTRL_GRANT))
408 ;
409 }
410
411 writel(flash_addr, &priv->regs->dma_flash_addr);
412 writel(FLASH_CALIBRATION_LEN, &priv->regs->dma_len);
413
414 /*
415 * When doing calibration, the SPI clock rate in the control
416 * register and the data input delay cycles in the
417 * read timing compensation register are replaced by bit[11:4].
418 */
419 dma_ctrl = DMA_CTRL_ENABLE | DMA_CTRL_CKSUM | DMA_CTRL_CALIB |
420 G6_TIMING_MASK(div, delay);
421
422 writel(dma_ctrl, &priv->regs->dma_ctrl);
423 while (!(readl(&priv->regs->intr_ctrl) & INTR_CTRL_DMA_STATUS))
424 ;
425
426 checksum = readl(&priv->regs->dma_checksum);
427
428 writel(0x0, &priv->regs->intr_ctrl);
429 writel(0x0, &priv->regs->dma_ctrl);
430 writel(DMA_DISCARD_REQ_MAGIC, &priv->regs->dma_ctrl);
431
432 return checksum;
433 }
434
aspeed_spi_read_checksum(struct aspeed_spi_priv * priv,struct aspeed_spi_flash * flash,u8 div,u8 delay)435 static u32 aspeed_spi_read_checksum(struct aspeed_spi_priv *priv,
436 struct aspeed_spi_flash *flash,
437 u8 div, u8 delay)
438 {
439 if (priv->new_ver)
440 return aspeed_g6_spi_fmc_checksum(priv, flash, div, delay);
441
442 /* for AST2500, */
443 if (!priv->is_fmc) {
444 pr_warn("No timing calibration support for SPI controllers");
445 return 0xbadc0de;
446 }
447
448 return aspeed_spi_fmc_checksum(priv, flash, div, delay);
449 }
450
451 #define TIMING_DELAY_DI_4NS BIT(3)
452 #define TIMING_DELAY_HCYCLE_MAX 5
453
454 /*
455 * Check whether the data is not all 0 or 1 in order to
456 * avoid calibriate umount spi-flash.
457 */
aspeed_spi_calibriation_enable(const u8 * buf,u32 sz)458 static bool aspeed_spi_calibriation_enable(const u8 *buf, u32 sz)
459 {
460 const u32 *buf_32 = (const u32 *)buf;
461 u32 i;
462 u32 valid_count = 0;
463
464 for (i = 0; i < (sz / 4); i++) {
465 if (buf_32[i] != 0 && buf_32[i] != 0xffffffff)
466 valid_count++;
467 if (valid_count > 100)
468 return true;
469 }
470
471 return false;
472 }
473
get_mid_point_of_longest_one(u8 * buf,u32 len)474 static int get_mid_point_of_longest_one(u8 *buf, u32 len)
475 {
476 int i;
477 int start = 0, mid_point = 0;
478 int max_cnt = 0, cnt = 0;
479
480 for (i = 0; i < len; i++) {
481 if (buf[i] == 1) {
482 cnt++;
483 } else {
484 cnt = 0;
485 start = i;
486 }
487
488 if (max_cnt < cnt) {
489 max_cnt = cnt;
490 mid_point = start + (cnt / 2);
491 }
492 }
493
494 /*
495 * In order to get a stable SPI read timing,
496 * abandon the result if the length of longest
497 * consecutive good points is too short.
498 */
499 if (max_cnt < 4)
500 return -1;
501
502 return mid_point;
503 }
504
aspeed_spi_timing_calibration(struct aspeed_spi_priv * priv,struct aspeed_spi_flash * flash)505 static int aspeed_spi_timing_calibration(struct aspeed_spi_priv *priv,
506 struct aspeed_spi_flash *flash)
507 {
508 u32 cs = flash->cs;
509 /* HCLK/5 .. HCLK/1 */
510 const u8 hclk_masks[] = {13, 6, 14, 7, 15};
511 u32 timing_reg;
512 u32 checksum, gold_checksum;
513 int i;
514 u32 hcycle, delay_ns;
515 u32 final_delay = 0;
516 u32 hclk_div = 0;
517 u32 max_freq = flash->max_freq;
518 u32 reg_val;
519 u8 *tmp_buf = NULL;
520 u8 *calib_res = NULL;
521 int calib_point;
522 bool pass;
523
524 if (priv->new_ver) {
525 timing_reg = readl(&priv->regs->timings + cs);
526 if (timing_reg != 0)
527 return 0;
528
529 /*
530 * use the related low frequency to get check calibration data
531 * and get golden data.
532 */
533 reg_val = flash->ce_ctrl_fread & CE_CTRL_FREQ_MASK;
534 writel(reg_val, &priv->regs->ce_ctrl[cs]);
535 tmp_buf = (u8 *)malloc(FLASH_CALIBRATION_LEN);
536 if (!tmp_buf)
537 return -ENOMEM;
538
539 memcpy_fromio(tmp_buf, flash->ahb_base, FLASH_CALIBRATION_LEN);
540 if (!aspeed_spi_calibriation_enable(tmp_buf, FLASH_CALIBRATION_LEN)) {
541 debug("flash data is monotonous, skip calibration.\n");
542 goto no_calib;
543 }
544
545 /* Compute reference checksum at lowest freq HCLK/16 */
546 gold_checksum = aspeed_spi_read_checksum(priv, flash, 0, 0);
547
548 /*
549 * allocate a space to record calibration result for
550 * different timing compensation with fixed
551 * HCLK division.
552 */
553 calib_res = (u8 *)malloc(6 * 17);
554 if (!calib_res) {
555 free(tmp_buf);
556 return -ENOMEM;
557 }
558
559 /* from HCLK/2 to HCLK/5 */
560 for (i = 0; i < ARRAY_SIZE(hclk_masks) - 1; i++) {
561 if (priv->hclk_rate / (i + 2) > max_freq) {
562 debug("skipping freq %ld\n", priv->hclk_rate / (i + 2));
563 continue;
564 }
565
566 max_freq = (u32)priv->hclk_rate / (i + 2);
567
568 memset(calib_res, 0x0, 6 * 17);
569 for (hcycle = 0; hcycle <= 5; hcycle++) {
570 /* increase DI delay by the step of 0.5ns */
571 debug("Delay Enable : hcycle %x\n", hcycle);
572 for (delay_ns = 0; delay_ns <= 0xf; delay_ns++) {
573 checksum = aspeed_g6_spi_fmc_checksum(priv, flash,
574 hclk_masks[3 - i],
575 TIMING_DELAY_DI_4NS | hcycle | (delay_ns << 4));
576 pass = (checksum == gold_checksum);
577 calib_res[hcycle * 17 + delay_ns] = pass;
578 debug("HCLK/%d, %d HCLK cycle, %d delay_ns : %s\n",
579 i + 2, hcycle, delay_ns, pass ? "PASS" : "FAIL");
580 }
581 }
582
583 calib_point = get_mid_point_of_longest_one(calib_res, 6 * 17);
584 if (calib_point < 0) {
585 debug("cannot get good calibration point.\n");
586 continue;
587 }
588
589 hcycle = calib_point / 17;
590 delay_ns = calib_point % 17;
591 debug("final hcycle: %d, delay_ns: %d\n", hcycle, delay_ns);
592
593 final_delay = (TIMING_DELAY_DI_4NS | hcycle | (delay_ns << 4)) << (i * 8);
594 writel(final_delay, &priv->regs->timings + cs);
595 break;
596 }
597
598 no_calib:
599 hclk_div = aspeed_g6_spi_hclk_divisor(priv, max_freq);
600 /* configure SPI clock frequency */
601 reg_val = readl(&priv->regs->ce_ctrl[cs]);
602 reg_val = (reg_val & CE_CTRL_FREQ_MASK) | CE_G6_CTRL_CLOCK_FREQ(hclk_div);
603 writel(reg_val, &priv->regs->ce_ctrl[cs]);
604
605 /* add clock setting info for CE ctrl setting */
606 flash->ce_ctrl_user =
607 (flash->ce_ctrl_user & CE_CTRL_FREQ_MASK) | CE_G6_CTRL_CLOCK_FREQ(hclk_div);
608 flash->ce_ctrl_fread =
609 (flash->ce_ctrl_fread & CE_CTRL_FREQ_MASK) | CE_G6_CTRL_CLOCK_FREQ(hclk_div);
610
611 debug("cs: %d, freq: %dMHz\n", cs, max_freq / 1000000);
612
613 if (tmp_buf)
614 free(tmp_buf);
615 if (calib_res)
616 free(calib_res);
617 } else {
618 /* Use the ctrl setting in aspeed_spi_flash_init() to
619 * implement calibration process.
620 */
621 timing_reg = readl(&priv->regs->timings);
622 if (timing_reg != 0)
623 return 0;
624
625 /* Compute reference checksum at lowest freq HCLK/16 */
626 gold_checksum = aspeed_spi_read_checksum(priv, flash, 0, 0);
627
628 for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) {
629 u32 hdiv = 5 - i;
630 u32 hshift = (hdiv - 1) << 2;
631 bool pass = false;
632 u8 delay;
633
634 if (priv->hclk_rate / hdiv > flash->max_freq) {
635 debug("skipping freq %ld\n", priv->hclk_rate / hdiv);
636 continue;
637 }
638
639 /* Increase HCLK cycles until read succeeds */
640 for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) {
641 /* Try first with a 4ns DI delay */
642 delay = TIMING_DELAY_DI_4NS | hcycle;
643 checksum = aspeed_spi_read_checksum(priv, flash, hclk_masks[i],
644 delay);
645 pass = (checksum == gold_checksum);
646 debug(" HCLK/%d, 4ns DI delay, %d HCLK cycle : %s\n",
647 hdiv, hcycle, pass ? "PASS" : "FAIL");
648
649 /* Try again with more HCLK cycles */
650 if (!pass)
651 continue;
652
653 /* Try without the 4ns DI delay */
654 delay = hcycle;
655 checksum = aspeed_spi_read_checksum(priv, flash, hclk_masks[i],
656 delay);
657 pass = (checksum == gold_checksum);
658 debug(" HCLK/%d, no DI delay, %d HCLK cycle : %s\n",
659 hdiv, hcycle, pass ? "PASS" : "FAIL");
660
661 /* All good for this freq */
662 if (pass)
663 break;
664 }
665
666 if (pass) {
667 timing_reg &= ~(0xfu << hshift);
668 timing_reg |= delay << hshift;
669 }
670 }
671
672 debug("Read Timing Compensation set to 0x%08x\n", timing_reg);
673 writel(timing_reg, &priv->regs->timings);
674 }
675
676 return 0;
677 }
678
aspeed_spi_controller_init(struct aspeed_spi_priv * priv)679 static int aspeed_spi_controller_init(struct aspeed_spi_priv *priv)
680 {
681 int cs;
682
683 /*
684 * Enable write on all flash devices as USER command mode
685 * requires it.
686 */
687 setbits_le32(&priv->regs->conf,
688 CONF_ENABLE_W2 | CONF_ENABLE_W1 | CONF_ENABLE_W0);
689
690 if (priv->is_fmc && priv->disable_fmc_wdt2)
691 clrbits_le32(&priv->regs->fmc_wdt2_ctrl, FMC_WDT2_ENABLE);
692
693 /*
694 * Set safe default settings for each device. These will be
695 * tuned after the SPI flash devices are probed.
696 */
697 if (priv->new_ver) {
698 for (cs = 0; cs < priv->flash_count; cs++) {
699 struct aspeed_spi_flash *flash = &priv->flashes[cs];
700 u32 addr_config = 0;
701 switch(cs) {
702 case 0:
703 flash->ahb_base = priv->ahb_base;
704 debug("cs0 mem-map : %x\n", (u32)flash->ahb_base);
705 break;
706 case 1:
707 flash->ahb_base = priv->flashes[0].ahb_base + 0x4000000; /* cs0 + 64MB */
708 debug("cs1 mem-map : %x end %x\n",
709 (u32)flash->ahb_base, (u32)flash->ahb_base + 0x4000000);
710 break;
711 case 2:
712 flash->ahb_base = priv->flashes[0].ahb_base + 0x4000000 * 2; /* cs0 + 128MB : use 64MB */
713 debug("cs2 mem-map : %x end %x\n",
714 (u32)flash->ahb_base, (u32)flash->ahb_base + 0x4000000);
715 break;
716 }
717 addr_config =
718 G6_SEGMENT_ADDR_VALUE((u32)flash->ahb_base, (u32)flash->ahb_base + 0x4000000);
719 writel(addr_config, &priv->regs->segment_addr[cs]);
720 flash->cs = cs;
721 flash->ce_ctrl_user = CE_CTRL_USERMODE;
722 flash->ce_ctrl_fread = CE_CTRL_READMODE;
723 }
724 } else {
725 for (cs = 0; cs < priv->flash_count; cs++) {
726 struct aspeed_spi_flash *flash = &priv->flashes[cs];
727 u32 seg_addr = readl(&priv->regs->segment_addr[cs]);
728 /*
729 * The start address of the AHB window of CE0 is
730 * read-only and is the same as the address of the
731 * overall AHB window of the controller for all flash
732 * devices.
733 */
734 flash->ahb_base = cs ? (void *)SEGMENT_ADDR_START(seg_addr) :
735 priv->ahb_base;
736
737 flash->cs = cs;
738 flash->ce_ctrl_user = CE_CTRL_USERMODE;
739 flash->ce_ctrl_fread = CE_CTRL_READMODE;
740 }
741 }
742 return 0;
743 }
744
aspeed_spi_read_from_ahb(void __iomem * ahb_base,void * buf,size_t len)745 static int aspeed_spi_read_from_ahb(void __iomem *ahb_base, void *buf,
746 size_t len)
747 {
748 size_t offset = 0;
749
750 if (!((uintptr_t)buf % 4)) {
751 readsl(ahb_base, buf, len >> 2);
752 offset = len & ~0x3;
753 len -= offset;
754 }
755 readsb(ahb_base, (u8 *)buf + offset, len);
756
757 return 0;
758 }
759
aspeed_spi_write_to_ahb(void __iomem * ahb_base,const void * buf,size_t len)760 static int aspeed_spi_write_to_ahb(void __iomem *ahb_base, const void *buf,
761 size_t len)
762 {
763 size_t offset = 0;
764
765 if (!((uintptr_t)buf % 4)) {
766 writesl(ahb_base, buf, len >> 2);
767 offset = len & ~0x3;
768 len -= offset;
769 }
770 writesb(ahb_base, (u8 *)buf + offset, len);
771
772 return 0;
773 }
774
aspeed_spi_start_user(struct aspeed_spi_priv * priv,struct aspeed_spi_flash * flash)775 static void aspeed_spi_start_user(struct aspeed_spi_priv *priv,
776 struct aspeed_spi_flash *flash)
777 {
778 u32 ctrl_reg = flash->ce_ctrl_user | CE_CTRL_STOP_ACTIVE;
779
780 /* Deselect CS and set USER command mode */
781 writel(ctrl_reg, &priv->regs->ce_ctrl[flash->cs]);
782
783 /* Select CS */
784 clrbits_le32(&priv->regs->ce_ctrl[flash->cs], CE_CTRL_STOP_ACTIVE);
785 }
786
aspeed_spi_stop_user(struct aspeed_spi_priv * priv,struct aspeed_spi_flash * flash)787 static void aspeed_spi_stop_user(struct aspeed_spi_priv *priv,
788 struct aspeed_spi_flash *flash)
789 {
790 /* Deselect CS first */
791 setbits_le32(&priv->regs->ce_ctrl[flash->cs], CE_CTRL_STOP_ACTIVE);
792
793 /* Restore default command mode */
794 writel(flash->ce_ctrl_fread, &priv->regs->ce_ctrl[flash->cs]);
795 }
796
aspeed_spi_read_reg(struct aspeed_spi_priv * priv,struct aspeed_spi_flash * flash,u8 opcode,u8 * read_buf,int len)797 static int aspeed_spi_read_reg(struct aspeed_spi_priv *priv,
798 struct aspeed_spi_flash *flash,
799 u8 opcode, u8 *read_buf, int len)
800 {
801 struct aspeed_spi_op op =
802 ASPEED_SPI_OP(0,
803 ASPEED_SPI_OP_CMD(opcode),
804 ASPEED_SPI_OP_ADDR(0, 0),
805 ASPEED_SPI_OP_DUMMY(0),
806 ASPEED_SPI_OP_DATA_IN(len, read_buf));
807
808 if (priv->spi_exec_op_cmd) {
809 priv->spi_exec_op_cmd(priv, flash, &op);
810 return 0;
811 }
812
813 aspeed_spi_start_user(priv, flash);
814 aspeed_spi_write_to_ahb(flash->ahb_base, &opcode, 1);
815 aspeed_spi_read_from_ahb(flash->ahb_base, read_buf, len);
816 aspeed_spi_stop_user(priv, flash);
817
818 return 0;
819 }
820
aspeed_spi_write_reg(struct aspeed_spi_priv * priv,struct aspeed_spi_flash * flash,u8 opcode,const u8 * write_buf,int len)821 static int aspeed_spi_write_reg(struct aspeed_spi_priv *priv,
822 struct aspeed_spi_flash *flash,
823 u8 opcode, const u8 *write_buf, int len)
824 {
825 int i;
826 struct aspeed_spi_op op =
827 ASPEED_SPI_OP(0,
828 ASPEED_SPI_OP_CMD(opcode),
829 ASPEED_SPI_OP_ADDR(0, 0),
830 ASPEED_SPI_OP_DUMMY(0),
831 ASPEED_SPI_OP_DATA_OUT(len, write_buf));
832
833 if (priv->spi_exec_op_cmd) {
834 if (opcode == SPINOR_OP_BE_4K || opcode == SPINOR_OP_BE_4K_4B ||
835 opcode == SPINOR_OP_BE_32K || opcode == SPINOR_OP_BE_32K_4B ||
836 opcode == SPINOR_OP_SE || opcode == SPINOR_OP_SE_4B) {
837 op.addr.nbytes = len;
838 for (i = 0; i < len; i++) {
839 op.addr.val <<= 8;
840 op.addr.val |= (u32)write_buf[i];
841 }
842 op.data.nbytes = 0;
843 }
844
845 priv->spi_exec_op_cmd(priv, flash, &op);
846 return 0;
847 }
848
849 aspeed_spi_start_user(priv, flash);
850 aspeed_spi_write_to_ahb(flash->ahb_base, &opcode, 1);
851 aspeed_spi_write_to_ahb(flash->ahb_base, write_buf, len);
852 aspeed_spi_stop_user(priv, flash);
853
854 debug("=== write opcode [%x] ==== \n", opcode);
855 switch(opcode) {
856 case SPINOR_OP_EN4B:
857 /* For ast2600, if 2 chips ABR mode is enabled,
858 * turn on 3B mode auto clear in order to avoid
859 * the scenario where spi controller is at 4B mode
860 * and flash site is at 3B mode after 3rd switch.
861 */
862 if (priv->new_ver == 1 && (readl(SPI_3B_AUTO_CLR_REG) & SPI_3B_AUTO_CLR))
863 writel(readl(&priv->regs->soft_rst_cmd_ctrl) | SOFT_RST_CMD_EN,
864 &priv->regs->soft_rst_cmd_ctrl);
865
866 writel(readl(&priv->regs->ctrl) | (0x11 << flash->cs), &priv->regs->ctrl);
867 break;
868 case SPINOR_OP_EX4B:
869 writel(readl(&priv->regs->ctrl) & ~(0x11 << flash->cs), &priv->regs->ctrl);
870 break;
871 }
872 return 0;
873 }
874
aspeed_spi_send_cmd_addr(struct aspeed_spi_priv * priv,struct aspeed_spi_flash * flash,const u8 * cmdbuf,unsigned int cmdlen,uint32_t flag)875 static void aspeed_spi_send_cmd_addr(struct aspeed_spi_priv *priv,
876 struct aspeed_spi_flash *flash,
877 const u8 *cmdbuf, unsigned int cmdlen, uint32_t flag)
878 {
879 int i;
880
881 /* First, send the opcode */
882 aspeed_spi_write_to_ahb(flash->ahb_base, &cmdbuf[0], 1);
883
884 if(flash->write_iomode == CE_CTRL_IO_QUAD_ADDR_DATA && (flag & SPI_WRITE_TO_FLASH))
885 writel(flash->ce_ctrl_user | flash->write_iomode, &priv->regs->ce_ctrl[flash->cs]);
886 else if(flash->read_iomode == CE_CTRL_IO_QUAD_ADDR_DATA && (flag & SPI_READ_FROM_FLASH))
887 writel(flash->ce_ctrl_user | flash->read_iomode, &priv->regs->ce_ctrl[flash->cs]);
888
889 /* Then the address */
890 for (i = 1 ; i < cmdlen; i++)
891 aspeed_spi_write_to_ahb(flash->ahb_base, &cmdbuf[i], 1);
892 }
893
aspeed_spi_read_user(struct aspeed_spi_priv * priv,struct aspeed_spi_flash * flash,unsigned int cmdlen,const u8 * cmdbuf,unsigned int len,u8 * read_buf)894 static ssize_t aspeed_spi_read_user(struct aspeed_spi_priv *priv,
895 struct aspeed_spi_flash *flash,
896 unsigned int cmdlen, const u8 *cmdbuf,
897 unsigned int len, u8 *read_buf)
898 {
899 u8 dummy = 0x00;
900 int i;
901 struct aspeed_spi_op op =
902 ASPEED_SPI_OP(flash->read_iomode,
903 ASPEED_SPI_OP_CMD(cmdbuf[0]),
904 ASPEED_SPI_OP_ADDR(0, 0),
905 ASPEED_SPI_OP_DUMMY(flash->spi->read_dummy / 8),
906 ASPEED_SPI_OP_DATA_IN(len, read_buf));
907
908 if (priv->spi_exec_op_cmd) {
909 op.addr.nbytes = cmdlen - 1 - op.dummy.nbytes;
910 op.addr.val = aspeed_spi_flash_to_addr(flash, cmdbuf, op.addr.nbytes + 1);
911 priv->spi_exec_op_cmd(priv, flash, &op);
912 return 0;
913 }
914
915 aspeed_spi_start_user(priv, flash);
916
917 /* cmd buffer = cmd + addr + dummies */
918 aspeed_spi_send_cmd_addr(priv, flash, cmdbuf,
919 cmdlen - (flash->spi->read_dummy / 8), SPI_READ_FROM_FLASH);
920
921 for (i = 0; i < (flash->spi->read_dummy / 8); i++)
922 aspeed_spi_write_to_ahb(flash->ahb_base, &dummy, 1);
923
924 if (flash->read_iomode) {
925 clrbits_le32(&priv->regs->ce_ctrl[flash->cs],
926 CE_CTRL_IO_MODE_MASK);
927 setbits_le32(&priv->regs->ce_ctrl[flash->cs], flash->read_iomode);
928 }
929
930 aspeed_spi_read_from_ahb(flash->ahb_base, read_buf, len);
931 aspeed_spi_stop_user(priv, flash);
932
933 return 0;
934 }
935
aspeed_spi_read_sfdp(struct aspeed_spi_priv * priv,struct aspeed_spi_flash * flash,unsigned int cmdlen,const u8 * cmdbuf,unsigned int len,u8 * read_buf)936 static ssize_t aspeed_spi_read_sfdp(struct aspeed_spi_priv *priv,
937 struct aspeed_spi_flash *flash,
938 unsigned int cmdlen, const u8 *cmdbuf,
939 unsigned int len, u8 *read_buf)
940 {
941 u8 dummy = 0x00;
942 int i;
943 struct aspeed_spi_op op =
944 ASPEED_SPI_OP(flash->read_iomode,
945 ASPEED_SPI_OP_CMD(cmdbuf[0]),
946 ASPEED_SPI_OP_ADDR(0, 3),
947 ASPEED_SPI_OP_DUMMY(flash->spi->read_dummy / 8),
948 ASPEED_SPI_OP_DATA_IN(len, read_buf));
949
950 if (priv->spi_exec_op_cmd) {
951 op.addr.val = aspeed_spi_flash_to_addr(flash, cmdbuf, op.addr.nbytes + 1);
952 priv->spi_exec_op_cmd(priv, flash, &op);
953 return 0;
954 }
955
956 /* only 1-1-1 mode is used to read SFDP */
957 aspeed_spi_start_user(priv, flash);
958
959 /* cmd buffer = cmd + addr + dummies */
960 aspeed_spi_send_cmd_addr(priv, flash, cmdbuf,
961 cmdlen - (flash->spi->read_dummy / 8), 0);
962
963 for (i = 0; i < (flash->spi->read_dummy / 8); i++)
964 aspeed_spi_write_to_ahb(flash->ahb_base, &dummy, 1);
965
966 aspeed_spi_read_from_ahb(flash->ahb_base, read_buf, len);
967 aspeed_spi_stop_user(priv, flash);
968
969 return 0;
970 }
971
aspeed_spi_write_user(struct aspeed_spi_priv * priv,struct aspeed_spi_flash * flash,unsigned int cmdlen,const u8 * cmdbuf,unsigned int len,const u8 * write_buf)972 static ssize_t aspeed_spi_write_user(struct aspeed_spi_priv *priv,
973 struct aspeed_spi_flash *flash,
974 unsigned int cmdlen, const u8 *cmdbuf,
975 unsigned int len, const u8 *write_buf)
976 {
977 struct aspeed_spi_op op =
978 ASPEED_SPI_OP(flash->write_iomode,
979 ASPEED_SPI_OP_CMD(cmdbuf[0]),
980 ASPEED_SPI_OP_ADDR(0, 0),
981 ASPEED_SPI_OP_DUMMY(0),
982 ASPEED_SPI_OP_DATA_OUT(len, write_buf));
983
984 if (priv->spi_exec_op_cmd) {
985 op.addr.nbytes = cmdlen - 1;
986 op.addr.val = aspeed_spi_flash_to_addr(flash, cmdbuf, op.addr.nbytes + 1);
987 priv->spi_exec_op_cmd(priv, flash, &op);
988 return 0;
989 }
990
991 aspeed_spi_start_user(priv, flash);
992
993 /* cmd buffer = cmd + addr : normally cmd is use signle mode*/
994 aspeed_spi_send_cmd_addr(priv, flash, cmdbuf, cmdlen, SPI_WRITE_TO_FLASH);
995
996 /* data will use io mode */
997 if(flash->write_iomode == CE_CTRL_IO_QUAD_DATA)
998 writel(flash->ce_ctrl_user | flash->write_iomode, &priv->regs->ce_ctrl[flash->cs]);
999
1000 aspeed_spi_write_to_ahb(flash->ahb_base, write_buf, len);
1001
1002 aspeed_spi_stop_user(priv, flash);
1003
1004 return 0;
1005 }
1006
aspeed_spi_flash_to_addr(struct aspeed_spi_flash * flash,const u8 * cmdbuf,unsigned int cmdlen)1007 static u32 aspeed_spi_flash_to_addr(struct aspeed_spi_flash *flash,
1008 const u8 *cmdbuf, unsigned int cmdlen)
1009 {
1010 u8 addrlen = cmdlen - 1;
1011 u32 addr = (cmdbuf[1] << 16) | (cmdbuf[2] << 8) | cmdbuf[3];
1012
1013 /*
1014 * U-Boot SPI Flash layer uses 3 bytes addresses, but it might
1015 * change one day
1016 */
1017 if (addrlen == 4)
1018 addr = (addr << 8) | cmdbuf[4];
1019
1020 return addr;
1021 }
1022
1023 /* TODO(clg@kaod.org): add support for XFER_MMAP instead ? */
aspeed_spi_read(struct aspeed_spi_priv * priv,struct aspeed_spi_flash * flash,unsigned int cmdlen,const u8 * cmdbuf,unsigned int len,u8 * read_buf)1024 static ssize_t aspeed_spi_read(struct aspeed_spi_priv *priv,
1025 struct aspeed_spi_flash *flash,
1026 unsigned int cmdlen, const u8 *cmdbuf,
1027 unsigned int len, u8 *read_buf)
1028 {
1029 /* cmd buffer = cmd + addr + dummies */
1030 u32 offset = aspeed_spi_flash_to_addr(flash, cmdbuf,
1031 cmdlen - (flash->spi->read_dummy/8));
1032 struct aspeed_spi_op op =
1033 ASPEED_SPI_OP(flash->read_iomode,
1034 ASPEED_SPI_OP_CMD(cmdbuf[0]),
1035 ASPEED_SPI_OP_ADDR(0, 0),
1036 ASPEED_SPI_OP_DUMMY(flash->spi->read_dummy / 8),
1037 ASPEED_SPI_OP_DATA_IN(len, read_buf));
1038
1039 if (priv->spi_exec_op_cmd) {
1040 op.addr.nbytes = cmdlen - 1 - op.dummy.nbytes;
1041 op.addr.val = aspeed_spi_flash_to_addr(flash, cmdbuf, op.addr.nbytes + 1);
1042 priv->spi_exec_op_cmd(priv, flash, &op);
1043 return 0;
1044 }
1045
1046 /*
1047 * Switch to USER command mode:
1048 * - if read SFDP content.
1049 * - if the AHB window configured for the device is
1050 * too small for the read operation
1051 * - if read offset is smaller than the decoded start address
1052 * and the decoded range is not multiple of flash size.
1053 */
1054 if ((offset + len >= flash->ahb_size) || \
1055 (offset < ((int)flash->ahb_base & 0x0FFFFFFF) && \
1056 (((int)flash->ahb_base & 0x0FFFFFFF) % flash->spi->size) != 0)) {
1057 return aspeed_spi_read_user(priv, flash, cmdlen, cmdbuf,
1058 len, read_buf);
1059 }
1060
1061 memcpy_fromio(read_buf, flash->ahb_base + offset, len);
1062
1063 return 0;
1064 }
1065
aspeed_spi_exec_op_cmd_mode(struct aspeed_spi_priv * priv,struct aspeed_spi_flash * flash,struct aspeed_spi_op * op)1066 int aspeed_spi_exec_op_cmd_mode(struct aspeed_spi_priv *priv,
1067 struct aspeed_spi_flash *flash,
1068 struct aspeed_spi_op *op)
1069 {
1070 uint32_t cs = flash->cs;
1071 uint32_t ctrl_val;
1072 uint32_t addr_mode_reg, addr_mode_reg_backup;
1073 uint32_t addr_data_mask = 0;
1074 void __iomem *op_addr;
1075 const void *data_buf;
1076 uint32_t data_byte = 0;
1077 uint32_t dummy_data = 0;
1078
1079 debug("iomode: %08x, cmd:%02x, addr:%08x, dummy:%d, data_len:%x, dir: %s\n",
1080 op->io_mode, op->cmd.opcode, op->addr.val, op->dummy.nbytes,
1081 op->data.nbytes, op->data.dir == ASPEED_SPI_DIR_IN ? "in" : "out");
1082
1083 addr_mode_reg = readl(&priv->regs->ctrl);
1084 addr_mode_reg_backup = addr_mode_reg;
1085 addr_data_mask = readl(&priv->regs->cmd_ctrl);
1086
1087 ctrl_val = flash->ce_ctrl_fread & (~0xf0ff40c7);
1088 ctrl_val |= op->io_mode;
1089 /* configure opcode */
1090 ctrl_val |= op->cmd.opcode << 16;
1091
1092 /* configure operation address, address length and address mask */
1093 if (op->addr.nbytes != 0) {
1094 if (op->addr.nbytes == 3)
1095 addr_mode_reg &= ~(0x11 << cs);
1096 else
1097 addr_mode_reg |= (0x11 << cs);
1098
1099 addr_data_mask &= 0x0f;
1100 op_addr = flash->ahb_base + op->addr.val;
1101 } else {
1102 addr_data_mask |= 0xf0;
1103 op_addr = flash->ahb_base;
1104 }
1105
1106 if (op->dummy.nbytes != 0) {
1107 ctrl_val |= ((op->dummy.nbytes & 0x3) << 6 |
1108 ((op->dummy.nbytes & 0x4) >> 2) << 14);
1109 }
1110
1111 /* configure data io mode and data mask */
1112 if (op->data.nbytes != 0) {
1113 addr_data_mask &= 0xF0;
1114 if (op->data.nbytes < 4)
1115 addr_data_mask |= ~((1 << op->data.nbytes) - 1);
1116
1117 data_byte = op->data.nbytes;
1118 if (op->data.dir == ASPEED_SPI_DIR_OUT) {
1119 if (data_byte % 4 != 0) {
1120 memset(priv->tmp_buf, 0xff, ((data_byte / 4) + 1) * 4);
1121 memcpy(priv->tmp_buf, op->data.buf.out, data_byte);
1122 data_buf = priv->tmp_buf;
1123 data_byte = ((data_byte / 4) + 1) * 4;
1124 } else {
1125 data_buf = op->data.buf.out;
1126 }
1127 } else {
1128 data_buf = op->data.buf.in;
1129 }
1130 } else {
1131 addr_data_mask |= 0x0f;
1132 data_byte = 1;
1133 data_buf = &dummy_data;
1134 }
1135
1136 /* configure command mode */
1137 if (op->data.dir == ASPEED_SPI_DIR_OUT)
1138 ctrl_val |= CE_CTRL_WRITEMODE;
1139 else
1140 ctrl_val |= CE_CTRL_FREADMODE;
1141
1142 /* set controller registers */
1143 writel(ctrl_val, &priv->regs->ce_ctrl[cs]);
1144 writel(addr_mode_reg, &priv->regs->ctrl);
1145 writel(addr_data_mask, &priv->regs->cmd_ctrl);
1146
1147 debug("ctrl: 0x%08x, addr_mode: 0x%x, mask: 0x%x, addr:0x%08x\n",
1148 ctrl_val, addr_mode_reg, addr_data_mask, (uint32_t)op_addr);
1149
1150 /* trigger spi transmission or reception sequence */
1151 if (op->data.dir == ASPEED_SPI_DIR_OUT)
1152 memcpy_toio(op_addr, data_buf, data_byte);
1153 else
1154 memcpy_fromio((void *)data_buf, op_addr, data_byte);
1155
1156 /* restore controller setting */
1157 writel(flash->ce_ctrl_fread, &priv->regs->ce_ctrl[cs]);
1158 writel(addr_mode_reg_backup, &priv->regs->ctrl);
1159 writel(0x0, &priv->regs->cmd_ctrl);
1160
1161 return 0;
1162 }
1163
aspeed_spi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)1164 static int aspeed_spi_xfer(struct udevice *dev, unsigned int bitlen,
1165 const void *dout, void *din, unsigned long flags)
1166 {
1167 struct udevice *bus = dev->parent;
1168 struct aspeed_spi_priv *priv = dev_get_priv(bus);
1169 struct aspeed_spi_flash *flash;
1170 u8 *cmd_buf = priv->cmd_buf;
1171 size_t data_bytes;
1172 int err = 0;
1173 u32 iomode;
1174
1175 flash = aspeed_spi_get_flash(dev);
1176 if (!flash)
1177 return -ENXIO;
1178
1179 if (flags & SPI_XFER_BEGIN) {
1180 /* save command in progress */
1181 priv->cmd_len = bitlen / 8;
1182 memcpy(cmd_buf, dout, priv->cmd_len);
1183 }
1184
1185 if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) {
1186 /* if start and end bit are set, the data bytes is 0. */
1187 data_bytes = 0;
1188 } else {
1189 data_bytes = bitlen / 8;
1190 }
1191
1192 debug("CS%u: %s cmd %zu bytes data %zu bytes\n", flash->cs,
1193 din ? "read" : "write", priv->cmd_len, data_bytes);
1194
1195 if ((flags & SPI_XFER_END) || flags == 0) {
1196 if (priv->cmd_len == 0) {
1197 pr_err("No command is progress !\n");
1198 return -1;
1199 }
1200
1201 if (din && data_bytes) {
1202 if (priv->cmd_len == 1) {
1203 err = aspeed_spi_read_reg(priv, flash,
1204 cmd_buf[0],
1205 din, data_bytes);
1206 } else if (cmd_buf[0] == SPINOR_OP_RDSFDP) {
1207 err = aspeed_spi_read_sfdp(priv, flash,
1208 priv->cmd_len,
1209 cmd_buf, data_bytes,
1210 din);
1211 } else if (cmd_buf[0] == SPINOR_OP_RDAR) {
1212 /* only for Cypress flash */
1213 iomode = flash->read_iomode;
1214 flash->read_iomode = 0;
1215 err = aspeed_spi_read_user(priv, flash,
1216 priv->cmd_len,
1217 cmd_buf, data_bytes,
1218 din);
1219 flash->read_iomode = iomode;
1220 } else {
1221 err = aspeed_spi_read(priv, flash,
1222 priv->cmd_len,
1223 cmd_buf, data_bytes,
1224 din);
1225 }
1226 } else if (dout) {
1227 if (priv->cmd_len == 1) {
1228 err = aspeed_spi_write_reg(priv, flash,
1229 cmd_buf[0],
1230 dout, data_bytes);
1231 } else {
1232 err = aspeed_spi_write_user(priv, flash,
1233 priv->cmd_len,
1234 cmd_buf, data_bytes,
1235 dout);
1236 }
1237 }
1238
1239 if (flags & SPI_XFER_END) {
1240 /* clear command */
1241 memset(cmd_buf, 0, sizeof(priv->cmd_buf));
1242 priv->cmd_len = 0;
1243 }
1244 }
1245
1246 return err;
1247 }
1248
1249 #ifdef CONFIG_ASPEED_SPI_FLASH_WRITE_PROTECTION
aspeed_spi_fill_FQCD(struct aspeed_spi_priv * priv,u8 cmd)1250 static void aspeed_spi_fill_FQCD(struct aspeed_spi_priv *priv, u8 cmd)
1251 {
1252 u32 reg_val;
1253 u32 i;
1254
1255 for (i = 0; i < 20; i++) {
1256 reg_val = readl(&priv->regs->fully_qualified_cmd[i]);
1257 if ((u8)(reg_val & 0xff) == cmd ||
1258 (u8)((reg_val & 0xff00) >> 8) == cmd) {
1259 if ((reg_val & 0x80000000) == 0x80000000) {
1260 debug("cmd: %02x already exists in FQCD.\n", cmd);
1261 return;
1262 }
1263 }
1264 }
1265
1266 for (i = 0; i < 20; i++) {
1267 reg_val = readl(&priv->regs->fully_qualified_cmd[i]);
1268 if ((reg_val & 0x80000000) == 0x80000000) {
1269 if ((u8)(reg_val & 0xff) == 0x0) {
1270 reg_val |= (u32)cmd;
1271 debug("[%d]fill %02x cmd in FQCD%02d.\n", __LINE__, cmd, i);
1272 writel(reg_val, &priv->regs->fully_qualified_cmd[i]);
1273 return;
1274 } else if ((u8)((reg_val & 0xff00) >> 8) == 0x0) {
1275 reg_val |= ((u32)cmd) << 8;
1276 debug("[%d]fill %02x cmd in FQCD%02d.\n", __LINE__, cmd, i);
1277 writel(reg_val, &priv->regs->fully_qualified_cmd[i]);
1278 return;
1279 }
1280 }
1281 }
1282
1283 for (i = 0; i < 20; i++) {
1284 reg_val = readl(&priv->regs->fully_qualified_cmd[i]);
1285 if (reg_val == 0) {
1286 reg_val = 0x80000000 | (u32)cmd;
1287 debug("[%d]fill %02x cmd in FQCD%02d.\n", __LINE__, cmd, i);
1288 writel(reg_val, &priv->regs->fully_qualified_cmd[i]);
1289 return;
1290 }
1291 }
1292 }
1293
aspeed_spi_fill_AQCD(struct aspeed_spi_priv * priv,u8 cmd,u8 addr_width)1294 static void aspeed_spi_fill_AQCD(struct aspeed_spi_priv *priv, u8 cmd, u8 addr_width)
1295 {
1296 u32 reg_val;
1297 u32 i;
1298 u32 bit_offset;
1299
1300 if (addr_width != 3 && addr_width != 4) {
1301 printf("wrong address width: %d.\n", addr_width);
1302 return;
1303 }
1304
1305 bit_offset = (addr_width - 3) * 8;
1306
1307 for (i = 0; i < 12; i++) {
1308 reg_val = readl(&priv->regs->addr_qualified_cmd[i]);
1309 if ((reg_val & 0x80000000) == 0x80000000) {
1310 if ((u8)((reg_val & (0xff << bit_offset)) >> bit_offset) == cmd) {
1311 debug("cmd: %02x already exists in AQCD.\n", cmd);
1312 return;
1313 }
1314 }
1315 }
1316
1317 for (i = 0; i < 12; i++) {
1318 reg_val = readl(&priv->regs->addr_qualified_cmd[i]);
1319 if ((reg_val & 0x80000000) == 0x80000000) {
1320 if ((u8)((reg_val & (0xff << bit_offset)) >> bit_offset) == 0x0) {
1321 reg_val |= ((u32)cmd << bit_offset);
1322 debug("fill %02x cmd in AQCD%02d.\n", cmd, i);
1323 writel(reg_val, &priv->regs->addr_qualified_cmd[i]);
1324 return;
1325 }
1326 }
1327
1328 if (reg_val == 0) {
1329 reg_val = 0x80000000 | ((u32)cmd << bit_offset);
1330 debug("fill %02x cmd in AQCD%02d.\n", cmd, i);
1331 writel(reg_val, &priv->regs->addr_qualified_cmd[i]);
1332 return;
1333 }
1334 }
1335 }
1336
aspeed_spi_cmd_filter_config(struct aspeed_spi_priv * priv,u32 cs,bool enable)1337 static void aspeed_spi_cmd_filter_config(struct aspeed_spi_priv *priv,
1338 u32 cs, bool enable)
1339 {
1340 u32 reg_val;
1341
1342 reg_val = readl(&priv->regs->write_cmd_filter_ctrl);
1343
1344 if (enable)
1345 reg_val |= BIT(cs);
1346 else
1347 reg_val &= ~BIT(cs);
1348
1349 writel(reg_val, &priv->regs->write_cmd_filter_ctrl);
1350 }
1351
aspeed_spi_write_addr_ftr_sanity(struct aspeed_spi_priv * priv,u32 offset,size_t len)1352 static int aspeed_spi_write_addr_ftr_sanity(struct aspeed_spi_priv *priv,
1353 u32 offset, size_t len)
1354 {
1355 u32 addr_ftr_ctrl;
1356 u32 reg_val;
1357 u32 start;
1358 u32 end;
1359 u32 i;
1360
1361 addr_ftr_ctrl = readl(&priv->regs->write_addr_filter_ctrl);
1362 for (i = 0; i < 8; i++) {
1363 if ((addr_ftr_ctrl & (0x3 << (i * 2))) == 0)
1364 continue;
1365 reg_val = readl(&priv->regs->write_addr_filter[i]);
1366 start = (reg_val & 0xffff) << 12;
1367 end = (((reg_val & 0xffff0000) >> 16) << 12) | 0xFFF;
1368
1369 if (offset >= start && offset < end)
1370 return -1;
1371 else if ((offset + len) > start && (offset + len) < end)
1372 return -1;
1373 }
1374
1375 return 0;
1376 }
1377
aspeed_add_write_addr_ftr(struct aspeed_spi_priv * priv,u32 offset,size_t len)1378 static int aspeed_add_write_addr_ftr(struct aspeed_spi_priv *priv,
1379 u32 offset, size_t len)
1380 {
1381 u32 addr_ftr_ctrl;
1382 u32 reg_val;
1383 u32 start;
1384 u32 end;
1385 u32 i;
1386
1387 if ((offset & 0xfff) != 0) {
1388 offset &= 0xfffff000;
1389 printf("protected start address will be entend to 0x%08x.\n",
1390 offset);
1391 }
1392
1393 if ((len & 0xfff) != 0) {
1394 len &= 0xfff;
1395 printf("protected len will be trimed to 0x%x.\n", len);
1396 }
1397
1398 if (len == 0) {
1399 printf("invalid protect len: 0x%x.\n", len);
1400 return -1;
1401 }
1402
1403 addr_ftr_ctrl = readl(&priv->regs->write_addr_filter_ctrl);
1404 for (i = 0; i < 8; i++) {
1405 if ((addr_ftr_ctrl & (0x3 << (i * 2))) == 0) {
1406 start = offset;
1407 end = offset + len - 1;
1408
1409 reg_val = (start >> 12) | ((end >> 12) << 16);
1410
1411 debug("start: 0x%08x, end: 0x%08x, val: 0x%08x.\n",
1412 start, end, reg_val);
1413
1414 writel(reg_val, &priv->regs->write_addr_filter[i]);
1415 addr_ftr_ctrl |= 0x3 << (i * 2);
1416 writel(addr_ftr_ctrl, &priv->regs->write_addr_filter_ctrl);
1417
1418 printf("apply write lock from offset, 0x%08x, with len, 0x%08x.\n",
1419 offset, (u32)len);
1420
1421 break;
1422 }
1423 }
1424
1425 if (i == 8) {
1426 printf("insufficient write address filter register.\n");
1427 return -1;
1428 }
1429
1430 return 0;
1431 }
1432
aspeed_remove_write_addr_ftr(struct aspeed_spi_priv * priv,u32 offset,size_t len)1433 static int aspeed_remove_write_addr_ftr(struct aspeed_spi_priv *priv,
1434 u32 offset, size_t len)
1435 {
1436 u32 addr_ftr_ctrl;
1437 u32 reg_val;
1438 u32 bit_mask;
1439 u32 start;
1440 u32 end;
1441 u32 i;
1442
1443 if ((offset & 0xfff) != 0) {
1444 printf("start address should be aligned to 0x1000.\n");
1445 return -1;
1446 }
1447
1448 if ((len & 0xfff) != 0) {
1449 printf("removed length should be aligned to 0x1000.\n");
1450 return -1;
1451 }
1452
1453 if (len == 0) {
1454 printf("invalid removed length!\n");
1455 return -1;
1456 }
1457
1458 addr_ftr_ctrl = readl(&priv->regs->write_addr_filter_ctrl);
1459 for (i = 0; i < 8; i++) {
1460 bit_mask = 0x3 << (i * 2);
1461 if ((addr_ftr_ctrl & bit_mask) != bit_mask)
1462 continue;
1463
1464 reg_val = readl(&priv->regs->write_addr_filter[i]);
1465 start = (reg_val & 0xffff) << 12;
1466 end = (((reg_val & 0xffff0000) >> 16) << 12) + 0x1000;
1467
1468 if (offset != start || offset + len != end)
1469 continue;
1470
1471 addr_ftr_ctrl &= ~(0x3 << (i * 2));
1472 writel(addr_ftr_ctrl, &priv->regs->write_addr_filter_ctrl);
1473 writel(0x0, &priv->regs->write_addr_filter[i]);
1474 printf("remove write lock from offset, 0x%08x, with len, 0x%08x.\n",
1475 offset, (u32)len);
1476 break;
1477 }
1478
1479 if (i == 8) {
1480 printf("cannot find expected removed region.\n");
1481 return -1;
1482 }
1483
1484 return 0;
1485 }
1486
aspeed_spi_mem_wlock(struct udevice * dev,u32 offset,size_t len)1487 static int aspeed_spi_mem_wlock(struct udevice *dev, u32 offset, size_t len)
1488 {
1489 struct udevice *bus = dev->parent;
1490 struct aspeed_spi_priv *priv = dev_get_priv(bus);
1491 struct aspeed_spi_flash *flash;
1492 struct spi_nor *nor;
1493 int ret;
1494
1495 debug("%s offset: 0x%08x, len: 0x%08x.\n", __func__, offset, (u32)len);
1496
1497 flash = aspeed_spi_get_flash(dev);
1498 if (!flash)
1499 return -ENXIO;
1500
1501 nor = flash->spi;
1502
1503 debug("name: %s, read cmd: %02x, erase cmd: %02x, write cmd: %02x.\n",
1504 nor->name, nor->read_opcode, nor->erase_opcode, nor->program_opcode);
1505
1506 /* enable address filter */
1507 aspeed_spi_fill_FQCD(priv, nor->read_opcode);
1508 aspeed_spi_fill_AQCD(priv, nor->erase_opcode, nor->addr_width);
1509 aspeed_spi_fill_AQCD(priv, nor->program_opcode, nor->addr_width);
1510 aspeed_spi_cmd_filter_config(priv, flash->cs, true);
1511
1512 ret = aspeed_spi_write_addr_ftr_sanity(priv, offset, len);
1513 if (ret < 0) {
1514 printf("The expected protect region overlays with the existed regions!\n");
1515 return ret;
1516 }
1517
1518 ret = aspeed_add_write_addr_ftr(priv, offset, len);
1519 if (ret < 0)
1520 return -1;
1521
1522 return 0;
1523 }
1524
aspeed_spi_mem_wunlock(struct udevice * dev,u32 offset,size_t len)1525 static int aspeed_spi_mem_wunlock(struct udevice *dev, u32 offset, size_t len)
1526 {
1527 struct udevice *bus = dev->parent;
1528 struct aspeed_spi_priv *priv = dev_get_priv(bus);
1529 int ret;
1530
1531 ret = aspeed_remove_write_addr_ftr(priv, offset, len);
1532 if (ret < 0)
1533 return -1;
1534
1535 return 0;
1536 }
1537 #endif
1538
aspeed_spi_child_pre_probe(struct udevice * dev)1539 static int aspeed_spi_child_pre_probe(struct udevice *dev)
1540 {
1541 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
1542
1543 debug("pre_probe slave device on CS%u, max_hz %u, mode 0x%x.\n",
1544 slave_plat->cs, slave_plat->max_hz, slave_plat->mode);
1545
1546 if (!aspeed_spi_get_flash(dev))
1547 return -ENXIO;
1548
1549 return 0;
1550 }
1551
1552 /*
1553 * AST2600 SPI memory controllers support multiple chip selects.
1554 * The start address of a decode range should be multiple
1555 * of its related flash size. Namely, the total decoded size
1556 * from flash 0 to flash N should be multiple of (N + 1) flash size.
1557 */
aspeed_g6_adjust_decode_sz(u32 decode_sz_arr[],int len)1558 void aspeed_g6_adjust_decode_sz(u32 decode_sz_arr[], int len)
1559 {
1560 int cs, j;
1561 u32 sz;
1562
1563 for (cs = len - 1; cs >= 0; cs--) {
1564 sz = 0;
1565 for (j = 0; j < cs; j++)
1566 sz += decode_sz_arr[j];
1567
1568 if (sz % decode_sz_arr[cs] != 0)
1569 decode_sz_arr[0] += (sz % decode_sz_arr[cs]);
1570 }
1571 }
1572
1573 /*
1574 * It is possible to automatically define a contiguous address space
1575 * on top of all CEs in the AHB window of the controller but it would
1576 * require much more work. Let's start with a simple mapping scheme
1577 * which should work fine for a single flash device.
1578 *
1579 * More complex schemes should probably be defined with the device
1580 * tree.
1581 */
aspeed_spi_flash_set_segment(struct aspeed_spi_priv * priv,struct aspeed_spi_flash * flash)1582 static int aspeed_spi_flash_set_segment(struct aspeed_spi_priv *priv,
1583 struct aspeed_spi_flash *flash)
1584 {
1585 u32 seg_addr;
1586 u32 decode_sz_arr[ASPEED_SPI_MAX_CS];
1587 u32 reg_val;
1588 u32 cs;
1589 u32 total_decode_sz = 0;
1590 u32 cur_offset = 0;
1591
1592 /* could be configured through the device tree */
1593 flash->ahb_size = flash->spi->size;
1594
1595 if (priv->new_ver) {
1596 for (cs = 0; cs < ASPEED_SPI_MAX_CS; cs++) {
1597 reg_val = readl(&priv->regs->segment_addr[cs]);
1598 if (reg_val != 0 &&
1599 G6_SEGMENT_ADDR_END(reg_val) > G6_SEGMENT_ADDR_START(reg_val)) {
1600 decode_sz_arr[cs] =
1601 G6_SEGMENT_ADDR_END(reg_val) - G6_SEGMENT_ADDR_START(reg_val);
1602 } else {
1603 decode_sz_arr[cs] = 0;
1604 }
1605 }
1606
1607 decode_sz_arr[flash->cs] = flash->ahb_size;
1608 aspeed_g6_adjust_decode_sz(decode_sz_arr, flash->cs + 1);
1609
1610 for (cs = 0; cs < ASPEED_SPI_MAX_CS; cs++)
1611 total_decode_sz += decode_sz_arr[cs];
1612
1613 if (total_decode_sz > priv->ahb_size) {
1614 printf("err: Total decoded size, 0x%x, is too large.\n", total_decode_sz);
1615 return -ENOMEM;
1616 }
1617
1618 for (cs = 0; cs < ASPEED_SPI_MAX_CS; cs++) {
1619 struct aspeed_spi_flash *flash = &priv->flashes[cs];
1620
1621 flash->ahb_base = (void __iomem *)((u32)priv->ahb_base + cur_offset);
1622
1623 if (decode_sz_arr[cs] != 0) {
1624 seg_addr = G6_SEGMENT_ADDR_VALUE((u32)flash->ahb_base,
1625 (u32)flash->ahb_base + decode_sz_arr[cs]);
1626 } else {
1627 seg_addr = 0;
1628 }
1629
1630 writel(seg_addr, &priv->regs->segment_addr[cs]);
1631 flash->ahb_size = decode_sz_arr[cs];
1632 cur_offset += decode_sz_arr[cs];
1633 }
1634 } else {
1635 seg_addr = SEGMENT_ADDR_VALUE((u32)flash->ahb_base,
1636 (u32)flash->ahb_base + flash->ahb_size);
1637 writel(seg_addr, &priv->regs->segment_addr[flash->cs]);
1638 }
1639
1640 return 0;
1641 }
1642
aspeed_spi_flash_init(struct aspeed_spi_priv * priv,struct aspeed_spi_flash * flash,struct udevice * dev)1643 static int aspeed_spi_flash_init(struct aspeed_spi_priv *priv,
1644 struct aspeed_spi_flash *flash,
1645 struct udevice *dev)
1646 {
1647 int ret;
1648 struct spi_flash *spi_flash = dev_get_uclass_priv(dev);
1649 struct spi_slave *slave = dev_get_parent_priv(dev);
1650 struct udevice *bus = dev->parent;
1651 u32 read_hclk;
1652
1653 flash->spi = spi_flash;
1654
1655 /*
1656 * The flash device has not been probed yet. Initial transfers
1657 * to read the JEDEC of the device will use the initial
1658 * default settings of the registers.
1659 */
1660 if (!spi_flash->name)
1661 return 0;
1662
1663 /*
1664 * The SPI flash device slave should not change, so initialize
1665 * it only once.
1666 */
1667 if (flash->init)
1668 return 0;
1669
1670 debug("CS%u: init %s flags:%x size:%d page:%d sector:%d erase:%d",
1671 flash->cs,
1672 spi_flash->name, spi_flash->flags, spi_flash->size,
1673 spi_flash->page_size, spi_flash->sector_size,
1674 spi_flash->erase_size);
1675 debug(" cmds [ erase:%x read=%x write:%x ] dummy:%d, speed:%d\n",
1676 spi_flash->erase_opcode,
1677 spi_flash->read_opcode, spi_flash->program_opcode,
1678 spi_flash->read_dummy, slave->speed);
1679
1680 flash->ce_ctrl_user = CE_CTRL_USERMODE;
1681 flash->max_freq = slave->speed;
1682
1683 if(priv->new_ver)
1684 read_hclk = aspeed_g6_spi_hclk_divisor(priv, slave->speed);
1685 else
1686 read_hclk = aspeed_spi_hclk_divisor(priv, slave->speed);
1687
1688 switch(flash->spi->read_opcode) {
1689 case SPINOR_OP_READ:
1690 case SPINOR_OP_READ_4B:
1691 flash->read_iomode = CE_CTRL_IO_SINGLE;
1692 break;
1693 case SPINOR_OP_READ_1_1_2:
1694 case SPINOR_OP_READ_1_1_2_4B:
1695 flash->read_iomode = CE_CTRL_IO_DUAL_DATA;
1696 break;
1697 case SPINOR_OP_READ_1_1_4:
1698 case SPINOR_OP_READ_1_1_4_4B:
1699 flash->read_iomode = CE_CTRL_IO_QUAD_DATA;
1700 break;
1701 case SPINOR_OP_READ_1_4_4:
1702 case SPINOR_OP_READ_1_4_4_4B:
1703 flash->read_iomode = CE_CTRL_IO_QUAD_ADDR_DATA;
1704 printf("need modify dummy for 3 bytes\n");
1705 break;
1706 }
1707
1708 switch(flash->spi->program_opcode) {
1709 case SPINOR_OP_PP:
1710 case SPINOR_OP_PP_4B:
1711 flash->write_iomode = CE_CTRL_IO_SINGLE;
1712 break;
1713 case SPINOR_OP_PP_1_1_4:
1714 case SPINOR_OP_PP_1_1_4_4B:
1715 flash->write_iomode = CE_CTRL_IO_QUAD_DATA;
1716 break;
1717 case SPINOR_OP_PP_1_4_4:
1718 case SPINOR_OP_PP_1_4_4_4B:
1719 flash->write_iomode = CE_CTRL_IO_QUAD_ADDR_DATA;
1720 printf("need modify dummy for 3 bytes");
1721 break;
1722 }
1723
1724 if(priv->new_ver) {
1725 flash->ce_ctrl_fread = CE_G6_CTRL_CLOCK_FREQ(read_hclk) |
1726 flash->read_iomode |
1727 CE_CTRL_CMD(flash->spi->read_opcode) |
1728 CE_CTRL_DUMMY((flash->spi->read_dummy/8)) |
1729 CE_CTRL_FREADMODE;
1730 flash->ce_ctrl_user |= CE_G6_CTRL_CLOCK_FREQ(read_hclk);
1731 } else {
1732 flash->ce_ctrl_fread = CE_CTRL_CLOCK_FREQ(read_hclk) |
1733 flash->read_iomode |
1734 CE_CTRL_CMD(flash->spi->read_opcode) |
1735 CE_CTRL_DUMMY((flash->spi->read_dummy/8)) |
1736 CE_CTRL_FREADMODE;
1737 }
1738
1739 if (flash->spi->addr_width == 4)
1740 writel(readl(&priv->regs->ctrl) | 0x11 << flash->cs, &priv->regs->ctrl);
1741
1742 debug("CS%u: USER mode 0x%08x FREAD mode 0x%08x\n", flash->cs,
1743 flash->ce_ctrl_user, flash->ce_ctrl_fread);
1744
1745 /* Set the CE Control Register default (FAST READ) */
1746 writel(flash->ce_ctrl_fread, &priv->regs->ce_ctrl[flash->cs]);
1747
1748 /* Set Address Segment Register for direct AHB accesses */
1749 ret = aspeed_spi_flash_set_segment(priv, flash);
1750 if (ret != 0)
1751 return ret;
1752
1753 /*
1754 * Set the Read Timing Compensation Register. This setting
1755 * applies to all devices.
1756 */
1757 if (!dev_read_bool(bus, "timing-calibration-disabled")) {
1758 ret = aspeed_spi_timing_calibration(priv, flash);
1759 if (ret != 0)
1760 return ret;
1761 }
1762
1763 /* All done */
1764 flash->init = true;
1765
1766 return 0;
1767 }
1768
aspeed_spi_claim_bus(struct udevice * dev)1769 static int aspeed_spi_claim_bus(struct udevice *dev)
1770 {
1771 struct udevice *bus = dev->parent;
1772 struct aspeed_spi_priv *priv = dev_get_priv(bus);
1773 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
1774 struct aspeed_spi_flash *flash;
1775 struct spi_slave *slave = dev_get_parent_priv(dev);
1776 u32 read_hclk;
1777
1778 debug("%s: claim bus CS%u\n", bus->name, slave_plat->cs);
1779
1780 flash = aspeed_spi_get_flash(dev);
1781 if (!flash)
1782 return -ENODEV;
1783
1784 if (priv->new_ver) {
1785 if (dev_read_bool(bus, "timing-calibration-disabled")) {
1786 read_hclk = aspeed_g6_spi_hclk_divisor(priv, slave->speed);
1787 flash->ce_ctrl_user &= CE_CTRL_FREQ_MASK;
1788 flash->ce_ctrl_user |= CE_G6_CTRL_CLOCK_FREQ(read_hclk);
1789 flash->ce_ctrl_fread &= CE_CTRL_FREQ_MASK;
1790 flash->ce_ctrl_fread |= CE_G6_CTRL_CLOCK_FREQ(read_hclk);
1791 }
1792 }
1793
1794 return aspeed_spi_flash_init(priv, flash, dev);
1795 }
1796
aspeed_spi_release_bus(struct udevice * dev)1797 static int aspeed_spi_release_bus(struct udevice *dev)
1798 {
1799 struct udevice *bus = dev->parent;
1800 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
1801
1802 debug("%s: release bus CS%u\n", bus->name, slave_plat->cs);
1803
1804 if (!aspeed_spi_get_flash(dev))
1805 return -ENODEV;
1806
1807 return 0;
1808 }
1809
aspeed_spi_set_mode(struct udevice * bus,uint mode)1810 static int aspeed_spi_set_mode(struct udevice *bus, uint mode)
1811 {
1812 debug("%s: setting mode to %x\n", bus->name, mode);
1813
1814 if (mode & (SPI_RX_QUAD | SPI_TX_QUAD)) {
1815 #ifndef CONFIG_ASPEED_AST2600
1816 pr_err("%s invalid QUAD IO mode\n", bus->name);
1817 return -EINVAL;
1818 #endif
1819 }
1820
1821 /* The CE Control Register is set in claim_bus() */
1822 return 0;
1823 }
1824
aspeed_spi_set_speed(struct udevice * bus,uint hz)1825 static int aspeed_spi_set_speed(struct udevice *bus, uint hz)
1826 {
1827 debug("%s: setting speed to %u\n", bus->name, hz);
1828
1829 /* The CE Control Register is set in claim_bus() */
1830 return 0;
1831 }
1832
aspeed_spi_count_flash_devices(struct udevice * bus)1833 static int aspeed_spi_count_flash_devices(struct udevice *bus)
1834 {
1835 ofnode node;
1836 int count = 0;
1837
1838 dev_for_each_subnode(node, bus) {
1839 if (ofnode_is_available(node) &&
1840 (ofnode_device_is_compatible(node, "spi-flash") ||
1841 ofnode_device_is_compatible(node, "jedec,spi-nor")))
1842 count++;
1843 }
1844
1845 return count;
1846 }
1847
aspeed_spi_bind(struct udevice * bus)1848 static int aspeed_spi_bind(struct udevice *bus)
1849 {
1850 debug("%s assigned req_seq=%d seq=%d\n", bus->name, bus->req_seq,
1851 bus->seq);
1852
1853 return 0;
1854 }
1855
aspeed_spi_probe(struct udevice * bus)1856 static int aspeed_spi_probe(struct udevice *bus)
1857 {
1858 struct resource res_regs, res_ahb;
1859 struct aspeed_spi_priv *priv = dev_get_priv(bus);
1860 struct clk hclk;
1861 int ret;
1862
1863 ret = dev_read_resource(bus, 0, &res_regs);
1864 if (ret < 0)
1865 return ret;
1866
1867 priv->regs = (void __iomem *)res_regs.start;
1868
1869 ret = dev_read_resource(bus, 1, &res_ahb);
1870 if (ret < 0)
1871 return ret;
1872
1873 priv->ahb_base = (void __iomem *)res_ahb.start;
1874 priv->ahb_size = res_ahb.end - res_ahb.start + 1;
1875
1876 ret = clk_get_by_index(bus, 0, &hclk);
1877 if (ret < 0) {
1878 pr_err("%s could not get clock: %d\n", bus->name, ret);
1879 return ret;
1880 }
1881
1882 priv->hclk_rate = clk_get_rate(&hclk);
1883 clk_free(&hclk);
1884
1885 priv->num_cs = dev_read_u32_default(bus, "num-cs", ASPEED_SPI_MAX_CS);
1886
1887 priv->flash_count = aspeed_spi_count_flash_devices(bus);
1888 if (priv->flash_count > priv->num_cs) {
1889 pr_err("%s has too many flash devices: %d\n", bus->name,
1890 priv->flash_count);
1891 return -EINVAL;
1892 }
1893
1894 if (!priv->flash_count) {
1895 pr_err("%s has no flash devices ?!\n", bus->name);
1896 return -ENODEV;
1897 }
1898
1899 if (device_is_compatible(bus, "aspeed,ast2600-fmc") ||
1900 device_is_compatible(bus, "aspeed,ast2600-spi")) {
1901 priv->new_ver = 1;
1902 }
1903
1904 if (dev_read_bool(bus, "aspeed-spi-command-mode")) {
1905 debug("adopt command mode\n");
1906 priv->tmp_buf = memalign(4, 512);
1907 priv->spi_exec_op_cmd = aspeed_spi_exec_op_cmd_mode;
1908 } else {
1909 priv->spi_exec_op_cmd = NULL;
1910 }
1911
1912 /*
1913 * There are some slight differences between the FMC and the
1914 * SPI controllers
1915 */
1916 priv->is_fmc = dev_get_driver_data(bus);
1917 priv->disable_fmc_wdt2 =
1918 device_is_compatible(bus, "aspeed,ast2600-fmc") &&
1919 dev_read_bool(bus, "aspeed,abr-watchdog-disable");
1920
1921 ret = aspeed_spi_controller_init(priv);
1922 if (ret)
1923 return ret;
1924
1925 debug("%s probed regs=%p ahb_base=%p cs_num=%d seq=%d\n",
1926 bus->name, priv->regs, priv->ahb_base, priv->flash_count, bus->seq);
1927
1928 return 0;
1929 }
1930
1931 static const struct dm_spi_ops aspeed_spi_ops = {
1932 .claim_bus = aspeed_spi_claim_bus,
1933 .release_bus = aspeed_spi_release_bus,
1934 .set_mode = aspeed_spi_set_mode,
1935 .set_speed = aspeed_spi_set_speed,
1936 .xfer = aspeed_spi_xfer,
1937 #ifdef CONFIG_ASPEED_SPI_FLASH_WRITE_PROTECTION
1938 .mem_ctrl_wlock = aspeed_spi_mem_wlock,
1939 .mem_ctrl_wunlock = aspeed_spi_mem_wunlock,
1940 #endif
1941 };
1942
1943 static const struct udevice_id aspeed_spi_ids[] = {
1944 { .compatible = "aspeed,ast2600-fmc", .data = 1 },
1945 { .compatible = "aspeed,ast2600-spi", .data = 0 },
1946 { .compatible = "aspeed,ast2500-fmc", .data = 1 },
1947 { .compatible = "aspeed,ast2500-spi", .data = 0 },
1948 { .compatible = "aspeed,ast2400-fmc", .data = 1 },
1949 { }
1950 };
1951
1952 U_BOOT_DRIVER(aspeed_spi) = {
1953 .name = "aspeed_spi",
1954 .id = UCLASS_SPI,
1955 .of_match = aspeed_spi_ids,
1956 .ops = &aspeed_spi_ops,
1957 .priv_auto_alloc_size = sizeof(struct aspeed_spi_priv),
1958 .child_pre_probe = aspeed_spi_child_pre_probe,
1959 .bind = aspeed_spi_bind,
1960 .probe = aspeed_spi_probe,
1961 };
1962