| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr_smu_msg.c | 114 smu_print("SMU Test message: %d\n", input); in dcn30_smu_test_message()
126 smu_print("SMU Get SMU version\n"); in dcn30_smu_get_smu_version()
131 smu_print("SMU version: %d\n", *version); in dcn30_smu_get_smu_version()
144 smu_print("SMU Check driver if version\n"); in dcn30_smu_check_driver_if_version()
149 smu_print("SMU driver if version: %d\n", response); in dcn30_smu_check_driver_if_version()
163 smu_print("SMU Check msg header version\n"); in dcn30_smu_check_msg_header_version()
187 smu_print("SMU Set DRAM addr low: %d\n", addr_low); in dcn30_smu_set_dram_addr_low()
195 smu_print("SMU Transfer WM table SMU 2 DRAM\n"); in dcn30_smu_transfer_wm_table_smu_2_dram()
203 smu_print("SMU Transfer WM table DRAM 2 SMU\n"); in dcn30_smu_transfer_wm_table_dram_2_smu()
271 smu_print("SMU dpm freq: %d MHz\n", response); in dcn30_smu_get_dpm_freq_by_index()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr_smu_msg.c | 42 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
95 smu_print("FCLK P-state support value is : %d\n", enable); in dcn32_smu_send_fclk_pstate_message()
106 smu_print("Numways for SubVP : %d\n", num_ways); in dcn32_smu_send_cab_for_uclk_message()
111 smu_print("SMU Transfer WM table DRAM 2 SMU\n"); in dcn32_smu_transfer_wm_table_dram_2_smu()
119 smu_print("SMU Set PME workaround\n"); in dcn32_smu_set_pme_workaround()
133 smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz); in dcn32_smu_set_hard_min_by_freq()
138 smu_print("SMU Frequency set = %d KHz\n", response); in dcn32_smu_set_hard_min_by_freq()
145 smu_print("PMFW to wait for DMCUB ack for MCLK : %d\n", enable); in dcn32_smu_wait_for_dmub_ack_mclk()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_smu.c | 76 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
142 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result); in dcn315_smu_send_msg_with_param()
165 smu_print("SMU msg id write fail %x times. \n", i + 1); in dcn315_smu_send_msg_with_param()
219 …smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mh… in dcn315_smu_set_hard_min_dcfclk()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr_vbios_smu.c | 48 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
106 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result); in rn_vbios_smu_send_msg_with_param()
189 …smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mh… in rn_vbios_smu_set_hard_min_dcfclk()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | dcn301_smu.c | 48 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
106 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result); in dcn301_smu_send_msg_with_param()
184 …smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mh… in dcn301_smu_set_hard_min_dcfclk()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_smu.c | 63 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
127 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result); in dcn316_smu_send_msg_with_param()
193 …smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mh… in dcn316_smu_set_hard_min_dcfclk()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_smu.c | 47 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
113 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result); in dcn31_smu_send_msg_with_param()
206 …smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mh… in dcn31_smu_set_hard_min_dcfclk()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_smu.c | 62 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
128 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", in dcn314_smu_send_msg_with_param()
224 smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", in dcn314_smu_set_hard_min_dcfclk()
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