Searched refs:smstateen_acc_ok (Results 1 – 4 of 4) sorted by relevance
/openbmc/qemu/target/riscv/ |
H A D | zce_helper.c | 29 RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT); in HELPER()
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H A D | csr.c | 47 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit) in smstateen_acc_ok() function 88 return smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR); in fs() 179 RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT); in zcmt() 2075 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); in read_senvcfg() 2090 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); in write_senvcfg() 2104 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); in read_henvcfg() 2125 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); in write_henvcfg() 2144 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); in read_henvcfgh() 2162 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); in write_henvcfgh()
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H A D | cpu.h | 522 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit);
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H A D | cpu_helper.c | 125 fs = (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) == RISCV_EXCP_NONE) in cpu_get_tb_cpu_state()
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