1 /* 2 * Copyright (C) 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _nbio_2_3_DEFAULT_HEADER 22 #define _nbio_2_3_DEFAULT_HEADER 23 24 25 // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC 26 #define mmBIF_BX_PF_MM_INDEX_DEFAULT 0x00000000 27 #define mmBIF_BX_PF_MM_DATA_DEFAULT 0x00000000 28 #define mmBIF_BX_PF_MM_INDEX_HI_DEFAULT 0x00000000 29 30 31 // addressBlock: nbio_nbif0_bif_bx_SYSDEC 32 #define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000 33 #define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000 34 #define mmPCIE_INDEX_DEFAULT 0x00000000 35 #define mmPCIE_DATA_DEFAULT 0x00000000 36 #define mmPCIE_INDEX2_DEFAULT 0x00000000 37 #define mmPCIE_DATA2_DEFAULT 0x00000000 38 #define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000 39 #define mmSBIOS_SCRATCH_1_DEFAULT 0x00000000 40 #define mmSBIOS_SCRATCH_2_DEFAULT 0x00000000 41 #define mmSBIOS_SCRATCH_3_DEFAULT 0x00000000 42 #define mmBIOS_SCRATCH_0_DEFAULT 0x00000000 43 #define mmBIOS_SCRATCH_1_DEFAULT 0x00000000 44 #define mmBIOS_SCRATCH_2_DEFAULT 0x00000000 45 #define mmBIOS_SCRATCH_3_DEFAULT 0x00000000 46 #define mmBIOS_SCRATCH_4_DEFAULT 0x00000000 47 #define mmBIOS_SCRATCH_5_DEFAULT 0x00000000 48 #define mmBIOS_SCRATCH_6_DEFAULT 0x00000000 49 #define mmBIOS_SCRATCH_7_DEFAULT 0x00000000 50 #define mmBIOS_SCRATCH_8_DEFAULT 0x00000000 51 #define mmBIOS_SCRATCH_9_DEFAULT 0x00000000 52 #define mmBIOS_SCRATCH_10_DEFAULT 0x00000000 53 #define mmBIOS_SCRATCH_11_DEFAULT 0x00000000 54 #define mmBIOS_SCRATCH_12_DEFAULT 0x00000000 55 #define mmBIOS_SCRATCH_13_DEFAULT 0x00000000 56 #define mmBIOS_SCRATCH_14_DEFAULT 0x00000000 57 #define mmBIOS_SCRATCH_15_DEFAULT 0x00000000 58 #define mmBIF_RLC_INTR_CNTL_DEFAULT 0x00000000 59 #define mmBIF_VCE_INTR_CNTL_DEFAULT 0x00000000 60 #define mmBIF_UVD_INTR_CNTL_DEFAULT 0x00000000 61 #define mmGFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000 62 #define mmGFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000 63 #define mmGFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000 64 #define mmGFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000 65 #define mmGFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000 66 #define mmGFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000 67 #define mmGFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000 68 #define mmGFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000 69 #define mmGFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000 70 #define mmGFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000 71 #define mmGFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000 72 #define mmGFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000 73 #define mmGFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000 74 #define mmGFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000 75 #define mmGFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000 76 #define mmGFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000 77 #define mmGFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000 78 #define mmGFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000 79 #define mmGFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000 80 #define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000 81 82 83 // addressBlock: nbio_nbif0_syshub_mmreg_syshubdec 84 #define mmSYSHUB_INDEX_DEFAULT 0x00000000 85 #define mmSYSHUB_DATA_DEFAULT 0x00000000 86 87 88 // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 89 #define mmRCC_BIF_STRAP0_DEFAULT 0x00040a00 90 #define mmRCC_BIF_STRAP1_DEFAULT 0x00400108 91 #define mmRCC_BIF_STRAP2_DEFAULT 0x000a0079 92 #define mmRCC_BIF_STRAP3_DEFAULT 0x00000000 93 #define mmRCC_BIF_STRAP4_DEFAULT 0x00100010 94 #define mmRCC_BIF_STRAP5_DEFAULT 0x31130010 95 #define mmRCC_BIF_STRAP6_DEFAULT 0x00000000 96 #define mmRCC_DEV0_PORT_STRAP0_DEFAULT 0x54228f20 97 #define mmRCC_DEV0_PORT_STRAP1_DEFAULT 0x10221479 98 #define mmRCC_DEV0_PORT_STRAP2_DEFAULT 0x1c6fe009 99 #define mmRCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849 100 #define mmRCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000 101 #define mmRCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000 102 #define mmRCC_DEV0_PORT_STRAP6_DEFAULT 0x0000ff02 103 #define mmRCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000 104 #define mmRCC_DEV0_PORT_STRAP8_DEFAULT 0x00000000 105 #define mmRCC_DEV0_PORT_STRAP9_DEFAULT 0x00000000 106 #define mmRCC_DEV0_EPF0_STRAP0_DEFAULT 0x30007310 107 #define mmRCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000 108 #define mmRCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000 109 #define mmRCC_DEV0_EPF0_STRAP2_DEFAULT 0x02002000 110 #define mmRCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b5cc41 111 #define mmRCC_DEV0_EPF0_STRAP4_DEFAULT 0x1f000000 112 #define mmRCC_DEV0_EPF0_STRAP5_DEFAULT 0x00001002 113 #define mmRCC_DEV0_EPF0_STRAP8_DEFAULT 0xcb026001 114 #define mmRCC_DEV0_EPF0_STRAP9_DEFAULT 0x00000100 115 #define mmRCC_DEV0_EPF1_STRAP0_DEFAULT 0x3000ab38 116 #define mmRCC_DEV0_EPF1_STRAP10_DEFAULT 0x00000000 117 #define mmRCC_DEV0_EPF1_STRAP11_DEFAULT 0x00000000 118 #define mmRCC_DEV0_EPF1_STRAP12_DEFAULT 0x00000000 119 #define mmRCC_DEV0_EPF1_STRAP13_DEFAULT 0x00000000 120 #define mmRCC_DEV0_EPF1_STRAP2_DEFAULT 0x00002000 121 #define mmRCC_DEV0_EPF1_STRAP3_DEFAULT 0x0806ace1 122 #define mmRCC_DEV0_EPF1_STRAP4_DEFAULT 0x2f000000 123 #define mmRCC_DEV0_EPF1_STRAP5_DEFAULT 0x00001002 124 #define mmRCC_DEV0_EPF1_STRAP6_DEFAULT 0x00000000 125 #define mmRCC_DEV0_EPF1_STRAP7_DEFAULT 0x00000000 126 127 128 // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 129 #define mmEP_PCIE_SCRATCH_DEFAULT 0x00000000 130 #define mmEP_PCIE_CNTL_DEFAULT 0x00000000 131 #define mmEP_PCIE_INT_CNTL_DEFAULT 0x00000000 132 #define mmEP_PCIE_INT_STATUS_DEFAULT 0x00000000 133 #define mmEP_PCIE_RX_CNTL2_DEFAULT 0x00000000 134 #define mmEP_PCIE_BUS_CNTL_DEFAULT 0x00000080 135 #define mmEP_PCIE_CFG_CNTL_DEFAULT 0x00000000 136 #define mmEP_PCIE_TX_LTR_CNTL_DEFAULT 0x00007468 137 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa 138 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 139 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 140 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 141 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b 142 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 143 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 144 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a 145 #define mmEP_PCIE_STRAP_MISC_DEFAULT 0x00000000 146 #define mmEP_PCIE_STRAP_MISC2_DEFAULT 0x00000000 147 #define mmEP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000 148 #define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0 149 #define mmEP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100 150 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa 151 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 152 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 153 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 154 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b 155 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 156 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 157 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a 158 #define mmEP_PCIE_PME_CONTROL_DEFAULT 0x00000000 159 #define mmEP_PCIEP_RESERVED_DEFAULT 0x00000000 160 #define mmEP_PCIE_TX_CNTL_DEFAULT 0x00000000 161 #define mmEP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 162 #define mmEP_PCIE_ERR_CNTL_DEFAULT 0x00000500 163 #define mmEP_PCIE_RX_CNTL_DEFAULT 0x01000000 164 #define mmEP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 165 166 167 // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 168 #define mmDN_PCIE_RESERVED_DEFAULT 0x00000000 169 #define mmDN_PCIE_SCRATCH_DEFAULT 0x00000000 170 #define mmDN_PCIE_CNTL_DEFAULT 0x00000000 171 #define mmDN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000 172 #define mmDN_PCIE_RX_CNTL2_DEFAULT 0x00000000 173 #define mmDN_PCIE_BUS_CNTL_DEFAULT 0x00000080 174 #define mmDN_PCIE_CFG_CNTL_DEFAULT 0x00000000 175 #define mmDN_PCIE_STRAP_F0_DEFAULT 0x00000001 176 #define mmDN_PCIE_STRAP_MISC_DEFAULT 0x00000000 177 #define mmDN_PCIE_STRAP_MISC2_DEFAULT 0x00000000 178 179 180 // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 181 #define mmPCIE_ERR_CNTL_DEFAULT 0x00000500 182 #define mmPCIE_RX_CNTL_DEFAULT 0x00000000 183 #define mmPCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 184 #define mmPCIE_LC_CNTL2_DEFAULT 0x00000000 185 #define mmPCIEP_STRAP_MISC_DEFAULT 0x00000000 186 #define mmLTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000 187 188 189 // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975] 190 #define mmRCC_DEV0_EPF0_RCC_ERR_LOG_DEFAULT 0x00000000 191 #define mmRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 192 #define mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 193 #define mmRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 194 #define mmRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 195 196 197 // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 198 #define mmRCC_ERR_INT_CNTL_DEFAULT 0x00000000 199 #define mmRCC_BACO_CNTL_MISC_DEFAULT 0x00000000 200 #define mmRCC_RESET_EN_DEFAULT 0x00008000 201 #define mmRCC_VDM_SUPPORT_DEFAULT 0x00000000 202 #define mmRCC_MARGIN_PARAM_CNTL0_DEFAULT 0x0a80a0df 203 #define mmRCC_MARGIN_PARAM_CNTL1_DEFAULT 0x0000f000 204 #define mmRCC_GPUIOV_REGION_DEFAULT 0x00000000 205 #define mmRCC_PEER_REG_RANGE0_DEFAULT 0xffff0000 206 #define mmRCC_PEER_REG_RANGE1_DEFAULT 0xffff0000 207 #define mmRCC_BUS_CNTL_DEFAULT 0x00000000 208 #define mmRCC_CONFIG_CNTL_DEFAULT 0x00000000 209 #define mmRCC_CONFIG_F0_BASE_DEFAULT 0x00000000 210 #define mmRCC_CONFIG_APER_SIZE_DEFAULT 0x00000000 211 #define mmRCC_CONFIG_REG_APER_SIZE_DEFAULT 0x00000000 212 #define mmRCC_XDMA_LO_DEFAULT 0x00000000 213 #define mmRCC_XDMA_HI_DEFAULT 0x00000000 214 #define mmRCC_FEATURES_CONTROL_MISC_DEFAULT 0x00000000 215 #define mmRCC_BUSNUM_CNTL1_DEFAULT 0x00000000 216 #define mmRCC_BUSNUM_LIST0_DEFAULT 0x00000000 217 #define mmRCC_BUSNUM_LIST1_DEFAULT 0x00000000 218 #define mmRCC_BUSNUM_CNTL2_DEFAULT 0x00000000 219 #define mmRCC_CAPTURE_HOST_BUSNUM_DEFAULT 0x00000000 220 #define mmRCC_HOST_BUSNUM_DEFAULT 0x00000000 221 #define mmRCC_PEER0_FB_OFFSET_HI_DEFAULT 0x00000000 222 #define mmRCC_PEER0_FB_OFFSET_LO_DEFAULT 0x00000000 223 #define mmRCC_PEER1_FB_OFFSET_HI_DEFAULT 0x00000000 224 #define mmRCC_PEER1_FB_OFFSET_LO_DEFAULT 0x00000000 225 #define mmRCC_PEER2_FB_OFFSET_HI_DEFAULT 0x00000000 226 #define mmRCC_PEER2_FB_OFFSET_LO_DEFAULT 0x00000000 227 #define mmRCC_PEER3_FB_OFFSET_HI_DEFAULT 0x00000000 228 #define mmRCC_PEER3_FB_OFFSET_LO_DEFAULT 0x00000000 229 #define mmRCC_DEVFUNCNUM_LIST0_DEFAULT 0x00000000 230 #define mmRCC_DEVFUNCNUM_LIST1_DEFAULT 0x00000000 231 #define mmRCC_DEV0_LINK_CNTL_DEFAULT 0x00000000 232 #define mmRCC_CMN_LINK_CNTL_DEFAULT 0x00400000 233 #define mmRCC_EP_REQUESTERID_RESTORE_DEFAULT 0x00000000 234 #define mmRCC_LTR_LSWITCH_CNTL_DEFAULT 0x00000000 235 #define mmRCC_MH_ARB_CNTL_DEFAULT 0x00000000 236 237 238 // addressBlock: nbio_nbif0_bif_bx_BIFDEC1 239 #define mmCC_BIF_BX_STRAP0_DEFAULT 0x00000000 240 #define mmCC_BIF_BX_PINSTRAP0_DEFAULT 0x00000000 241 #define mmBIF_MM_INDACCESS_CNTL_DEFAULT 0x00000000 242 #define mmBUS_CNTL_DEFAULT 0x00000000 243 #define mmBIF_SCRATCH0_DEFAULT 0x00000000 244 #define mmBIF_SCRATCH1_DEFAULT 0x00000000 245 #define mmBX_RESET_EN_DEFAULT 0x00010000 246 #define mmMM_CFGREGS_CNTL_DEFAULT 0x00000000 247 #define mmBX_RESET_CNTL_DEFAULT 0x00000000 248 #define mmINTERRUPT_CNTL_DEFAULT 0x00000000 249 #define mmINTERRUPT_CNTL2_DEFAULT 0x00000000 250 #define mmCLKREQB_PAD_CNTL_DEFAULT 0x000008e0 251 #define mmBIF_FEATURES_CONTROL_MISC_DEFAULT 0x00800000 252 #define mmBIF_DOORBELL_CNTL_DEFAULT 0x00000000 253 #define mmBIF_DOORBELL_INT_CNTL_DEFAULT 0x00000000 254 #define mmBIF_FB_EN_DEFAULT 0x00000000 255 #define mmBIF_INTR_CNTL_DEFAULT 0x00000000 256 #define mmBIF_MST_TRANS_PENDING_VF_DEFAULT 0x00000000 257 #define mmBIF_SLV_TRANS_PENDING_VF_DEFAULT 0x00000000 258 #define mmBACO_CNTL_DEFAULT 0x00000000 259 #define mmBIF_BACO_EXIT_TIME0_DEFAULT 0x00000100 260 #define mmBIF_BACO_EXIT_TIMER1_DEFAULT 0x1c000200 261 #define mmBIF_BACO_EXIT_TIMER2_DEFAULT 0x00000300 262 #define mmBIF_BACO_EXIT_TIMER3_DEFAULT 0x00000500 263 #define mmBIF_BACO_EXIT_TIMER4_DEFAULT 0x00000400 264 #define mmMEM_TYPE_CNTL_DEFAULT 0x00000000 265 #define mmNBIF_GFX_ADDR_LUT_CNTL_DEFAULT 0x00000000 266 #define mmNBIF_GFX_ADDR_LUT_0_DEFAULT 0x00000000 267 #define mmNBIF_GFX_ADDR_LUT_1_DEFAULT 0x00000001 268 #define mmNBIF_GFX_ADDR_LUT_2_DEFAULT 0x00000002 269 #define mmNBIF_GFX_ADDR_LUT_3_DEFAULT 0x00000003 270 #define mmNBIF_GFX_ADDR_LUT_4_DEFAULT 0x00000004 271 #define mmNBIF_GFX_ADDR_LUT_5_DEFAULT 0x00000005 272 #define mmNBIF_GFX_ADDR_LUT_6_DEFAULT 0x00000006 273 #define mmNBIF_GFX_ADDR_LUT_7_DEFAULT 0x00000007 274 #define mmNBIF_GFX_ADDR_LUT_8_DEFAULT 0x00000008 275 #define mmNBIF_GFX_ADDR_LUT_9_DEFAULT 0x00000009 276 #define mmNBIF_GFX_ADDR_LUT_10_DEFAULT 0x0000000a 277 #define mmNBIF_GFX_ADDR_LUT_11_DEFAULT 0x0000000b 278 #define mmNBIF_GFX_ADDR_LUT_12_DEFAULT 0x0000000c 279 #define mmNBIF_GFX_ADDR_LUT_13_DEFAULT 0x0000000d 280 #define mmNBIF_GFX_ADDR_LUT_14_DEFAULT 0x0000000e 281 #define mmNBIF_GFX_ADDR_LUT_15_DEFAULT 0x0000000f 282 #define mmREMAP_HDP_MEM_FLUSH_CNTL_DEFAULT 0x0000385c 283 #define mmREMAP_HDP_REG_FLUSH_CNTL_DEFAULT 0x00003858 284 #define mmBIF_RB_CNTL_DEFAULT 0x00000000 285 #define mmBIF_RB_BASE_DEFAULT 0x00000000 286 #define mmBIF_RB_RPTR_DEFAULT 0x00000000 287 #define mmBIF_RB_WPTR_DEFAULT 0x00000000 288 #define mmBIF_RB_WPTR_ADDR_HI_DEFAULT 0x00000000 289 #define mmBIF_RB_WPTR_ADDR_LO_DEFAULT 0x00000000 290 #define mmMAILBOX_INDEX_DEFAULT 0x00000000 291 #define mmBIF_MP1_INTR_CTRL_DEFAULT 0x00000000 292 #define mmBIF_UVD_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 293 #define mmBIF_VCE_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 294 #define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 295 #define mmBIF_PERSTB_PAD_CNTL_DEFAULT 0x000000c0 296 #define mmBIF_PX_EN_PAD_CNTL_DEFAULT 0x00000031 297 #define mmBIF_REFPADKIN_PAD_CNTL_DEFAULT 0x00000007 298 #define mmBIF_CLKREQB_PAD_CNTL_DEFAULT 0x00600100 299 #define mmBIF_PWRBRK_PAD_CNTL_DEFAULT 0x00000071 300 #define mmBIF_WAKEB_PAD_CNTL_DEFAULT 0x00000031 301 #define mmBIF_VAUX_PRESENT_PAD_CNTL_DEFAULT 0x0000000d 302 303 304 // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 305 #define mmBIF_BX_PF_BIF_BME_STATUS_DEFAULT 0x00000000 306 #define mmBIF_BX_PF_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 307 #define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 308 #define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 309 #define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 310 #define mmBIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 311 #define mmBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 312 #define mmBIF_BX_PF_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 313 #define mmBIF_BX_PF_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 314 #define mmBIF_BX_PF_BIF_TRANS_PENDING_DEFAULT 0x00000000 315 #define mmBIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 316 #define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 317 #define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 318 #define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 319 #define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 320 #define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 321 #define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 322 #define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 323 #define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 324 #define mmBIF_BX_PF_MAILBOX_CONTROL_DEFAULT 0x00000000 325 #define mmBIF_BX_PF_MAILBOX_INT_CNTL_DEFAULT 0x00000000 326 #define mmBIF_BX_PF_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 327 328 329 // addressBlock: nbio_nbif0_gdc_GDCDEC 330 #define mmA2S_CNTL_CL0_DEFAULT 0x02a80540 331 #define mmA2S_CNTL_CL1_DEFAULT 0x02a825a0 332 #define mmA2S_CNTL3_CL0_DEFAULT 0x00000000 333 #define mmA2S_CNTL3_CL1_DEFAULT 0x00000008 334 #define mmA2S_CNTL_SW0_DEFAULT 0x04040000 335 #define mmA2S_CNTL_SW1_DEFAULT 0x04040200 336 #define mmA2S_CNTL_SW2_DEFAULT 0x04040200 337 #define mmA2S_CPLBUF_ALLOC_CNTL_DEFAULT 0x11100001 338 #define mmA2S_TAG_ALLOC_0_DEFAULT 0x00000000 339 #define mmA2S_TAG_ALLOC_1_DEFAULT 0x00000000 340 #define mmA2S_MISC_CNTL_DEFAULT 0x0005000b 341 #define mmNGDC_SDP_PORT_CTRL_DEFAULT 0x0000003f 342 #define mmSHUB_REGS_IF_CTL_DEFAULT 0x00000000 343 #define mmNGDC_MGCG_CTRL_DEFAULT 0x00000100 344 #define mmNGDC_RESERVED_0_DEFAULT 0x00000000 345 #define mmNGDC_RESERVED_1_DEFAULT 0x00000000 346 #define mmNGDC_SDP_PORT_CTRL_SOCCLK_DEFAULT 0x0000003f 347 #define mmBIF_SDMA0_DOORBELL_RANGE_DEFAULT 0x00000000 348 #define mmBIF_SDMA1_DOORBELL_RANGE_DEFAULT 0x00000000 349 #define mmBIF_IH_DOORBELL_RANGE_DEFAULT 0x00000000 350 #define mmBIF_MMSCH0_DOORBELL_RANGE_DEFAULT 0x00000000 351 #define mmBIF_ACV_DOORBELL_RANGE_DEFAULT 0x00000000 352 #define mmBIF_DOORBELL_FENCE_CNTL_DEFAULT 0x00000000 353 #define mmS2A_MISC_CNTL_DEFAULT 0x00000000 354 #define mmNGDC_PG_MISC_CTRL_DEFAULT 0x14006000 355 #define mmNGDC_PGMST_CTRL_DEFAULT 0x00000000 356 #define mmNGDC_PGSLV_CTRL_DEFAULT 0x00001084 357 358 359 // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2 360 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 361 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 362 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 363 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 364 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 365 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 366 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 367 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 368 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 369 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 370 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 371 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 372 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 373 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 374 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 375 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 376 #define mmRCC_DEV0_EPF0_GFXMSIX_PBA_DEFAULT 0x00000000 377 378 379 // addressBlock: nbio_pcie0_pswuscfg0_cfgdecp 380 #define cfgPSWUSCFG0_0_VENDOR_ID_DEFAULT 0x00000000 381 #define cfgPSWUSCFG0_0_DEVICE_ID_DEFAULT 0x00000000 382 #define cfgPSWUSCFG0_0_COMMAND_DEFAULT 0x00000000 383 #define cfgPSWUSCFG0_0_STATUS_DEFAULT 0x00000000 384 #define cfgPSWUSCFG0_0_REVISION_ID_DEFAULT 0x00000000 385 #define cfgPSWUSCFG0_0_PROG_INTERFACE_DEFAULT 0x00000000 386 #define cfgPSWUSCFG0_0_SUB_CLASS_DEFAULT 0x00000000 387 #define cfgPSWUSCFG0_0_BASE_CLASS_DEFAULT 0x00000000 388 #define cfgPSWUSCFG0_0_CACHE_LINE_DEFAULT 0x00000000 389 #define cfgPSWUSCFG0_0_LATENCY_DEFAULT 0x00000000 390 #define cfgPSWUSCFG0_0_HEADER_DEFAULT 0x00000000 391 #define cfgPSWUSCFG0_0_BIST_DEFAULT 0x00000000 392 #define cfgPSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 393 #define cfgPSWUSCFG0_0_IO_BASE_LIMIT_DEFAULT 0x00000000 394 #define cfgPSWUSCFG0_0_SECONDARY_STATUS_DEFAULT 0x00000000 395 #define cfgPSWUSCFG0_0_MEM_BASE_LIMIT_DEFAULT 0x00000000 396 #define cfgPSWUSCFG0_0_PREF_BASE_LIMIT_DEFAULT 0x00000000 397 #define cfgPSWUSCFG0_0_PREF_BASE_UPPER_DEFAULT 0x00000000 398 #define cfgPSWUSCFG0_0_PREF_LIMIT_UPPER_DEFAULT 0x00000000 399 #define cfgPSWUSCFG0_0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 400 #define cfgPSWUSCFG0_0_CAP_PTR_DEFAULT 0x00000000 401 #define cfgPSWUSCFG0_0_ROM_BASE_ADDR_DEFAULT 0x00000000 402 #define cfgPSWUSCFG0_0_INTERRUPT_LINE_DEFAULT 0x000000ff 403 #define cfgPSWUSCFG0_0_INTERRUPT_PIN_DEFAULT 0x00000000 404 #define cfgPSWUSCFG0_0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 405 #define cfgPSWUSCFG0_0_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 406 #define cfgPSWUSCFG0_0_VENDOR_CAP_LIST_DEFAULT 0x00000000 407 #define cfgPSWUSCFG0_0_ADAPTER_ID_W_DEFAULT 0x00000000 408 #define cfgPSWUSCFG0_0_PMI_CAP_LIST_DEFAULT 0x00000000 409 #define cfgPSWUSCFG0_0_PMI_CAP_DEFAULT 0x00000000 410 #define cfgPSWUSCFG0_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 411 #define cfgPSWUSCFG0_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 412 #define cfgPSWUSCFG0_0_PCIE_CAP_DEFAULT 0x00000002 413 #define cfgPSWUSCFG0_0_DEVICE_CAP_DEFAULT 0x00000000 414 #define cfgPSWUSCFG0_0_DEVICE_CNTL_DEFAULT 0x00002910 415 #define cfgPSWUSCFG0_0_DEVICE_STATUS_DEFAULT 0x00000000 416 #define cfgPSWUSCFG0_0_LINK_CAP_DEFAULT 0x00011c04 417 #define cfgPSWUSCFG0_0_LINK_CNTL_DEFAULT 0x00000000 418 #define cfgPSWUSCFG0_0_LINK_STATUS_DEFAULT 0x00000001 419 #define cfgPSWUSCFG0_0_DEVICE_CAP2_DEFAULT 0x00000000 420 #define cfgPSWUSCFG0_0_DEVICE_CNTL2_DEFAULT 0x00000000 421 #define cfgPSWUSCFG0_0_DEVICE_STATUS2_DEFAULT 0x00000000 422 #define cfgPSWUSCFG0_0_LINK_CAP2_DEFAULT 0x0000001e 423 #define cfgPSWUSCFG0_0_LINK_CNTL2_DEFAULT 0x00000004 424 #define cfgPSWUSCFG0_0_LINK_STATUS2_DEFAULT 0x00000000 425 #define cfgPSWUSCFG0_0_MSI_CAP_LIST_DEFAULT 0x0000c000 426 #define cfgPSWUSCFG0_0_MSI_MSG_CNTL_DEFAULT 0x00000000 427 #define cfgPSWUSCFG0_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 428 #define cfgPSWUSCFG0_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 429 #define cfgPSWUSCFG0_0_MSI_MSG_DATA_DEFAULT 0x00000000 430 #define cfgPSWUSCFG0_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 431 #define cfgPSWUSCFG0_0_SSID_CAP_LIST_DEFAULT 0x0000c800 432 #define cfgPSWUSCFG0_0_SSID_CAP_DEFAULT 0x00000000 433 #define cfgPSWUSCFG0_0_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 434 #define cfgPSWUSCFG0_0_MSI_MAP_CAP_DEFAULT 0x00000000 435 #define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 436 #define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 437 #define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 438 #define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 439 #define cfgPSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 440 #define cfgPSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 441 #define cfgPSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 442 #define cfgPSWUSCFG0_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 443 #define cfgPSWUSCFG0_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 444 #define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 445 #define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe 446 #define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 447 #define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 448 #define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 449 #define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 450 #define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 451 #define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 452 #define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 453 #define cfgPSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 454 #define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 455 #define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x04400000 456 #define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 457 #define cfgPSWUSCFG0_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 458 #define cfgPSWUSCFG0_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 459 #define cfgPSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 460 #define cfgPSWUSCFG0_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 461 #define cfgPSWUSCFG0_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 462 #define cfgPSWUSCFG0_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 463 #define cfgPSWUSCFG0_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 464 #define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 465 #define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 466 #define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 467 #define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 468 #define cfgPSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 469 #define cfgPSWUSCFG0_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 470 #define cfgPSWUSCFG0_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 471 #define cfgPSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 472 #define cfgPSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 473 #define cfgPSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 474 #define cfgPSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 475 #define cfgPSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 476 #define cfgPSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 477 #define cfgPSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 478 #define cfgPSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 479 #define cfgPSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 480 #define cfgPSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 481 #define cfgPSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 482 #define cfgPSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 483 #define cfgPSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 484 #define cfgPSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 485 #define cfgPSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 486 #define cfgPSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 487 #define cfgPSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 488 #define cfgPSWUSCFG0_0_PCIE_ACS_CAP_DEFAULT 0x00000000 489 #define cfgPSWUSCFG0_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 490 #define cfgPSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 491 #define cfgPSWUSCFG0_0_PCIE_MC_CAP_DEFAULT 0x00000000 492 #define cfgPSWUSCFG0_0_PCIE_MC_CNTL_DEFAULT 0x00000000 493 #define cfgPSWUSCFG0_0_PCIE_MC_ADDR0_DEFAULT 0x00000000 494 #define cfgPSWUSCFG0_0_PCIE_MC_ADDR1_DEFAULT 0x00000000 495 #define cfgPSWUSCFG0_0_PCIE_MC_RCV0_DEFAULT 0x00000000 496 #define cfgPSWUSCFG0_0_PCIE_MC_RCV1_DEFAULT 0x00000000 497 #define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 498 #define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 499 #define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 500 #define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 501 #define cfgPSWUSCFG0_0_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 502 #define cfgPSWUSCFG0_0_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 503 #define cfgPSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 504 #define cfgPSWUSCFG0_0_PCIE_LTR_CAP_DEFAULT 0x00000000 505 #define cfgPSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x38000000 506 #define cfgPSWUSCFG0_0_PCIE_ARI_CAP_DEFAULT 0x00000000 507 #define cfgPSWUSCFG0_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 508 #define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x3c400000 509 #define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 510 #define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 511 #define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 512 #define cfgPSWUSCFG0_0_PCIE_ESM_CAP_LIST_DEFAULT 0x40000000 513 #define cfgPSWUSCFG0_0_PCIE_ESM_HEADER_1_DEFAULT 0x00000000 514 #define cfgPSWUSCFG0_0_PCIE_ESM_HEADER_2_DEFAULT 0x00000000 515 #define cfgPSWUSCFG0_0_PCIE_ESM_STATUS_DEFAULT 0x00000000 516 #define cfgPSWUSCFG0_0_PCIE_ESM_CTRL_DEFAULT 0x00000000 517 #define cfgPSWUSCFG0_0_PCIE_ESM_CAP_1_DEFAULT 0x00000000 518 #define cfgPSWUSCFG0_0_PCIE_ESM_CAP_2_DEFAULT 0x00000000 519 #define cfgPSWUSCFG0_0_PCIE_ESM_CAP_3_DEFAULT 0x00000000 520 #define cfgPSWUSCFG0_0_PCIE_ESM_CAP_4_DEFAULT 0x00000000 521 #define cfgPSWUSCFG0_0_PCIE_ESM_CAP_5_DEFAULT 0x00000000 522 #define cfgPSWUSCFG0_0_PCIE_ESM_CAP_6_DEFAULT 0x00000000 523 #define cfgPSWUSCFG0_0_PCIE_ESM_CAP_7_DEFAULT 0x00000000 524 #define cfgPSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41000000 525 #define cfgPSWUSCFG0_0_DATA_LINK_FEATURE_CAP_DEFAULT 0x80000001 526 #define cfgPSWUSCFG0_0_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000 527 #define cfgPSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44000000 528 #define cfgPSWUSCFG0_0_LINK_CAP_16GT_DEFAULT 0x00000000 529 #define cfgPSWUSCFG0_0_LINK_CNTL_16GT_DEFAULT 0x00000000 530 #define cfgPSWUSCFG0_0_LINK_STATUS_16GT_DEFAULT 0x00000000 531 #define cfgPSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 532 #define cfgPSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 533 #define cfgPSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 534 #define cfgPSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 535 #define cfgPSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 536 #define cfgPSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 537 #define cfgPSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 538 #define cfgPSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 539 #define cfgPSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 540 #define cfgPSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 541 #define cfgPSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 542 #define cfgPSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 543 #define cfgPSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 544 #define cfgPSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 545 #define cfgPSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 546 #define cfgPSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 547 #define cfgPSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 548 #define cfgPSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 549 #define cfgPSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 550 #define cfgPSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x00000000 551 #define cfgPSWUSCFG0_0_MARGINING_PORT_CAP_DEFAULT 0x00000000 552 #define cfgPSWUSCFG0_0_MARGINING_PORT_STATUS_DEFAULT 0x00000000 553 #define cfgPSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 554 #define cfgPSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000 555 #define cfgPSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 556 #define cfgPSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000 557 #define cfgPSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 558 #define cfgPSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000 559 #define cfgPSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 560 #define cfgPSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000 561 #define cfgPSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 562 #define cfgPSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000 563 #define cfgPSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 564 #define cfgPSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000 565 #define cfgPSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 566 #define cfgPSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000 567 #define cfgPSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 568 #define cfgPSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000 569 #define cfgPSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 570 #define cfgPSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000 571 #define cfgPSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 572 #define cfgPSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000 573 #define cfgPSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 574 #define cfgPSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000 575 #define cfgPSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 576 #define cfgPSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000 577 #define cfgPSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 578 #define cfgPSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000 579 #define cfgPSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 580 #define cfgPSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000 581 #define cfgPSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 582 #define cfgPSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000 583 #define cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 584 #define cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000 585 #define cfgPSWUSCFG0_0_PCIE_CCIX_CAP_LIST_DEFAULT 0x00000000 586 #define cfgPSWUSCFG0_0_PCIE_CCIX_HEADER_1_DEFAULT 0x00000000 587 #define cfgPSWUSCFG0_0_PCIE_CCIX_HEADER_2_DEFAULT 0x00000000 588 #define cfgPSWUSCFG0_0_PCIE_CCIX_CAP_DEFAULT 0x00000000 589 #define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP_DEFAULT 0x00000000 590 #define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_OPTL_CAP_DEFAULT 0x00000000 591 #define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_STATUS_DEFAULT 0x00000000 592 #define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_CNTL_DEFAULT 0x00000000 593 #define cfgPSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 594 #define cfgPSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 595 #define cfgPSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 596 #define cfgPSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 597 #define cfgPSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 598 #define cfgPSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 599 #define cfgPSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 600 #define cfgPSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 601 #define cfgPSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 602 #define cfgPSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 603 #define cfgPSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 604 #define cfgPSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 605 #define cfgPSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 606 #define cfgPSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 607 #define cfgPSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 608 #define cfgPSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 609 #define cfgPSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 610 #define cfgPSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 611 #define cfgPSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 612 #define cfgPSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 613 #define cfgPSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 614 #define cfgPSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 615 #define cfgPSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 616 #define cfgPSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 617 #define cfgPSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 618 #define cfgPSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 619 #define cfgPSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 620 #define cfgPSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 621 #define cfgPSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 622 #define cfgPSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 623 #define cfgPSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 624 #define cfgPSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 625 #define cfgPSWUSCFG0_0_PCIE_CCIX_TRANS_CAP_DEFAULT 0x00000000 626 #define cfgPSWUSCFG0_0_PCIE_CCIX_TRANS_CNTL_DEFAULT 0x00000000 627 628 629 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp 630 #define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_ID_DEFAULT 0x00001002 631 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_ID_DEFAULT 0x00007310 632 #define cfgBIF_CFG_DEV0_EPF0_0_COMMAND_DEFAULT 0x00000000 633 #define cfgBIF_CFG_DEV0_EPF0_0_STATUS_DEFAULT 0x00000000 634 #define cfgBIF_CFG_DEV0_EPF0_0_REVISION_ID_DEFAULT 0x00000000 635 #define cfgBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE_DEFAULT 0x00000000 636 #define cfgBIF_CFG_DEV0_EPF0_0_SUB_CLASS_DEFAULT 0x00000000 637 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_CLASS_DEFAULT 0x00000000 638 #define cfgBIF_CFG_DEV0_EPF0_0_CACHE_LINE_DEFAULT 0x00000000 639 #define cfgBIF_CFG_DEV0_EPF0_0_LATENCY_DEFAULT 0x00000000 640 #define cfgBIF_CFG_DEV0_EPF0_0_HEADER_DEFAULT 0x00000080 641 #define cfgBIF_CFG_DEV0_EPF0_0_BIST_DEFAULT 0x00000000 642 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1_DEFAULT 0x00000000 643 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2_DEFAULT 0x00000000 644 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3_DEFAULT 0x00000000 645 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4_DEFAULT 0x00000000 646 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5_DEFAULT 0x00000000 647 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6_DEFAULT 0x00000000 648 #define cfgBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 649 #define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_DEFAULT 0x73101002 650 #define cfgBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR_DEFAULT 0x00000000 651 #define cfgBIF_CFG_DEV0_EPF0_0_CAP_PTR_DEFAULT 0x00000048 652 #define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE_DEFAULT 0x000000ff 653 #define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN_DEFAULT 0x00000001 654 #define cfgBIF_CFG_DEV0_EPF0_0_MIN_GRANT_DEFAULT 0x00000000 655 #define cfgBIF_CFG_DEV0_EPF0_0_MAX_LATENCY_DEFAULT 0x00000000 656 #define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST_DEFAULT 0x00000000 657 #define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W_DEFAULT 0x73101002 658 #define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST_DEFAULT 0x00006400 659 #define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_DEFAULT 0x0000f000 660 #define cfgBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 661 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 662 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_DEFAULT 0x00000012 663 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP_DEFAULT 0x00000f81 664 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL_DEFAULT 0x00002810 665 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS_DEFAULT 0x00000000 666 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_DEFAULT 0x00000d04 667 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_DEFAULT 0x00000000 668 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_DEFAULT 0x00000001 669 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2_DEFAULT 0x00010000 670 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2_DEFAULT 0x00000000 671 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2_DEFAULT 0x00000000 672 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP2_DEFAULT 0x0000001e 673 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL2_DEFAULT 0x00000004 674 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS2_DEFAULT 0x00000001 675 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST_DEFAULT 0x0000c000 676 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL_DEFAULT 0x00000084 677 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 678 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 679 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_DEFAULT 0x00000000 680 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_DEFAULT 0x00000000 681 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 682 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_64_DEFAULT 0x00000000 683 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_DEFAULT 0x00000000 684 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64_DEFAULT 0x00000000 685 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST_DEFAULT 0x00000000 686 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 687 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_TABLE_DEFAULT 0x00000000 688 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_PBA_DEFAULT 0x00000000 689 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 690 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 691 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 692 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 693 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 694 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 695 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 696 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 697 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 698 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 699 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe 700 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 701 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 702 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 703 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 704 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 705 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 706 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 707 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 708 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 709 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 710 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 711 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 712 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 713 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 714 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 715 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 716 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 717 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 718 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 719 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 720 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 721 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 722 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 723 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP_DEFAULT 0x00000000 724 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020 725 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP_DEFAULT 0x00000000 726 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000 727 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP_DEFAULT 0x00000000 728 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000 729 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP_DEFAULT 0x00000000 730 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000 731 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP_DEFAULT 0x00000000 732 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000 733 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP_DEFAULT 0x00000000 734 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000 735 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 736 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 737 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 738 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 739 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 740 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP_DEFAULT 0x00000000 741 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 742 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS_DEFAULT 0x00000100 743 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL_DEFAULT 0x00000000 744 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 745 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 746 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 747 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 748 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 749 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 750 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 751 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 752 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 753 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 754 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 755 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 756 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 757 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 758 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 759 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 760 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 761 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 762 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 763 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 764 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 765 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 766 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 767 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 768 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 769 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 770 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 771 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 772 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP_DEFAULT 0x00000000 773 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 774 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 775 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP_DEFAULT 0x00000000 776 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 777 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000 778 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 779 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000100 780 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000 781 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 782 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000 783 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP_DEFAULT 0x00001000 784 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL_DEFAULT 0x00000000 785 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 786 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP_DEFAULT 0x00000000 787 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL_DEFAULT 0x00000000 788 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0_DEFAULT 0x00000000 789 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1_DEFAULT 0x00000000 790 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0_DEFAULT 0x00000000 791 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1_DEFAULT 0x00000000 792 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 793 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 794 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 795 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 796 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 797 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP_DEFAULT 0x00000000 798 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 799 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP_DEFAULT 0x00000000 800 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 801 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x37000000 802 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP_DEFAULT 0x00000000 803 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000 804 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS_DEFAULT 0x00000000 805 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000 806 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000 807 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000 808 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000 809 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000 810 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000 811 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000 812 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000553 813 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001 814 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000 815 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000 816 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000 817 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000 818 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000 819 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000 820 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000 821 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000 822 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000 823 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 824 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41010025 825 #define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP_DEFAULT 0x00000001 826 #define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000 827 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44010026 828 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT_DEFAULT 0x00000000 829 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT_DEFAULT 0x00000000 830 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT_DEFAULT 0x00000000 831 #define cfgBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 832 #define cfgBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 833 #define cfgBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 834 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 835 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 836 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 837 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 838 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 839 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 840 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 841 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 842 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 843 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 844 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 845 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 846 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 847 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 848 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 849 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 850 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x4c010027 851 #define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP_DEFAULT 0x00000000 852 #define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS_DEFAULT 0x00000000 853 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 854 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000 855 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 856 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000 857 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 858 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000 859 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 860 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000 861 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 862 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000 863 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 864 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000 865 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 866 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000 867 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 868 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000 869 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 870 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000 871 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 872 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000 873 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 874 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000 875 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 876 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000 877 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 878 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000 879 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 880 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000 881 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 882 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000 883 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 884 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000 885 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_DEFAULT 0x00000000 886 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP_DEFAULT 0x00000000 887 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL_DEFAULT 0x00000020 888 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP_DEFAULT 0x00000000 889 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL_DEFAULT 0x00000000 890 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP_DEFAULT 0x00000000 891 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL_DEFAULT 0x00000000 892 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP_DEFAULT 0x00000000 893 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL_DEFAULT 0x00000000 894 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP_DEFAULT 0x00000000 895 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL_DEFAULT 0x00000000 896 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP_DEFAULT 0x00000000 897 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL_DEFAULT 0x00000000 898 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000 899 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000 900 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000 901 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000 902 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000 903 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000 904 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000 905 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000 906 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000 907 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000 908 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000 909 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x0012000c 910 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_DEFAULT 0x00000000 911 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_DEFAULT 0x00000000 912 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000 913 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000 914 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000 915 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000 916 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000 917 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000 918 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000 919 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000 920 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000 921 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000 922 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000 923 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000 924 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000 925 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000 926 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000 927 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000 928 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_DEFAULT 0x00000000 929 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_DEFAULT 0x00000000 930 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_DEFAULT 0x00000000 931 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_DEFAULT 0x00000000 932 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_DEFAULT 0x00000000 933 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_DEFAULT 0x00000000 934 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_DEFAULT 0x00000000 935 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_DEFAULT 0x00000000 936 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_DEFAULT 0x00000000 937 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_DEFAULT 0x00000000 938 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_DEFAULT 0x00000000 939 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_DEFAULT 0x00000000 940 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_DEFAULT 0x00000000 941 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_DEFAULT 0x00000000 942 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_DEFAULT 0x00000000 943 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000 944 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000 945 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000 946 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000 947 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000 948 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000 949 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000 950 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000 951 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000 952 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000 953 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000 954 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000 955 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000 956 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000 957 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000 958 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000 959 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000 960 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000 961 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000 962 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000 963 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000 964 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000 965 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000 966 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000 967 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000 968 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000 969 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000 970 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0_DEFAULT 0x00000000 971 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1_DEFAULT 0x00000000 972 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2_DEFAULT 0x00000000 973 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3_DEFAULT 0x00000000 974 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4_DEFAULT 0x00000000 975 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5_DEFAULT 0x00000000 976 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6_DEFAULT 0x00000000 977 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7_DEFAULT 0x00000000 978 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8_DEFAULT 0x00000000 979 980 981 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp 982 #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID_DEFAULT 0x00001002 983 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID_DEFAULT 0x0000ab38 984 #define cfgBIF_CFG_DEV0_EPF1_0_COMMAND_DEFAULT 0x00000000 985 #define cfgBIF_CFG_DEV0_EPF1_0_STATUS_DEFAULT 0x00000000 986 #define cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID_DEFAULT 0x00000000 987 #define cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE_DEFAULT 0x00000000 988 #define cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS_DEFAULT 0x00000000 989 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS_DEFAULT 0x00000000 990 #define cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE_DEFAULT 0x00000000 991 #define cfgBIF_CFG_DEV0_EPF1_0_LATENCY_DEFAULT 0x00000000 992 #define cfgBIF_CFG_DEV0_EPF1_0_HEADER_DEFAULT 0x00000080 993 #define cfgBIF_CFG_DEV0_EPF1_0_BIST_DEFAULT 0x00000000 994 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1_DEFAULT 0x00000000 995 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2_DEFAULT 0x00000000 996 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3_DEFAULT 0x00000000 997 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4_DEFAULT 0x00000000 998 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5_DEFAULT 0x00000000 999 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6_DEFAULT 0x00000000 1000 #define cfgBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 1001 #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_DEFAULT 0xab381002 1002 #define cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR_DEFAULT 0x00000000 1003 #define cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR_DEFAULT 0x00000048 1004 #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE_DEFAULT 0x000000ff 1005 #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN_DEFAULT 0x00000002 1006 #define cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT_DEFAULT 0x00000000 1007 #define cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY_DEFAULT 0x00000000 1008 #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST_DEFAULT 0x00000000 1009 #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W_DEFAULT 0xab381002 1010 #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST_DEFAULT 0x00006400 1011 #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_DEFAULT 0x0000f000 1012 #define cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 1013 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 1014 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_DEFAULT 0x00000012 1015 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP_DEFAULT 0x00000f81 1016 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL_DEFAULT 0x00002810 1017 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS_DEFAULT 0x00000000 1018 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP_DEFAULT 0x00000d04 1019 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL_DEFAULT 0x00000000 1020 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS_DEFAULT 0x00000001 1021 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2_DEFAULT 0x00010000 1022 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2_DEFAULT 0x00000000 1023 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2_DEFAULT 0x00000000 1024 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2_DEFAULT 0x0000001e 1025 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2_DEFAULT 0x00000004 1026 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2_DEFAULT 0x00000001 1027 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST_DEFAULT 0x0000c000 1028 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL_DEFAULT 0x00000080 1029 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 1030 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 1031 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_DEFAULT 0x00000000 1032 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_DEFAULT 0x00000000 1033 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 1034 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64_DEFAULT 0x00000000 1035 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_DEFAULT 0x00000000 1036 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64_DEFAULT 0x00000000 1037 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST_DEFAULT 0x00000000 1038 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 1039 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE_DEFAULT 0x00000000 1040 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA_DEFAULT 0x00000000 1041 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 1042 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 1043 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 1044 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 1045 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 1046 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 1047 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 1048 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 1049 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 1050 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 1051 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe 1052 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 1053 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 1054 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 1055 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 1056 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 1057 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 1058 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 1059 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 1060 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 1061 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 1062 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 1063 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 1064 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 1065 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 1066 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 1067 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 1068 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 1069 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 1070 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 1071 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 1072 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 1073 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 1074 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 1075 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP_DEFAULT 0x00000000 1076 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020 1077 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP_DEFAULT 0x00000000 1078 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000 1079 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP_DEFAULT 0x00000000 1080 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000 1081 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP_DEFAULT 0x00000000 1082 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000 1083 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP_DEFAULT 0x00000000 1084 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000 1085 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP_DEFAULT 0x00000000 1086 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000 1087 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 1088 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 1089 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 1090 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 1091 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 1092 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP_DEFAULT 0x00000000 1093 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 1094 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS_DEFAULT 0x00000100 1095 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL_DEFAULT 0x00000000 1096 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 1097 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 1098 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 1099 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 1100 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 1101 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 1102 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 1103 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 1104 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 1105 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 1106 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 1107 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 1108 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 1109 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 1110 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 1111 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 1112 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 1113 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 1114 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 1115 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 1116 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 1117 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 1118 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 1119 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 1120 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 1121 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 1122 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 1123 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 1124 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP_DEFAULT 0x00000000 1125 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 1126 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 1127 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP_DEFAULT 0x00000000 1128 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 1129 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000 1130 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 1131 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000100 1132 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000 1133 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 1134 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000 1135 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP_DEFAULT 0x00001000 1136 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL_DEFAULT 0x00000000 1137 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 1138 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP_DEFAULT 0x00000000 1139 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL_DEFAULT 0x00000000 1140 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0_DEFAULT 0x00000000 1141 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1_DEFAULT 0x00000000 1142 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0_DEFAULT 0x00000000 1143 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1_DEFAULT 0x00000000 1144 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 1145 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 1146 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 1147 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 1148 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 1149 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP_DEFAULT 0x00000000 1150 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 1151 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP_DEFAULT 0x00000000 1152 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 1153 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x37000000 1154 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP_DEFAULT 0x00000000 1155 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000 1156 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS_DEFAULT 0x00000000 1157 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000 1158 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000 1159 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000 1160 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000 1161 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000 1162 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000 1163 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000 1164 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000 1165 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001 1166 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000 1167 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000 1168 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000 1169 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000 1170 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000 1171 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000 1172 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000 1173 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000 1174 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000 1175 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 1176 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41010025 1177 #define cfgBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP_DEFAULT 0x00000001 1178 #define cfgBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000 1179 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44010026 1180 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT_DEFAULT 0x00000000 1181 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT_DEFAULT 0x00000000 1182 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT_DEFAULT 0x00000000 1183 #define cfgBIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 1184 #define cfgBIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 1185 #define cfgBIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 1186 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 1187 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 1188 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 1189 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 1190 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 1191 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 1192 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 1193 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 1194 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 1195 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 1196 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 1197 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 1198 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 1199 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 1200 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 1201 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 1202 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x4c010027 1203 #define cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP_DEFAULT 0x00000000 1204 #define cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS_DEFAULT 0x00000000 1205 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 1206 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000 1207 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 1208 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000 1209 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 1210 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000 1211 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 1212 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000 1213 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 1214 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000 1215 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 1216 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000 1217 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 1218 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000 1219 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 1220 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000 1221 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 1222 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000 1223 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 1224 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000 1225 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 1226 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000 1227 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 1228 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000 1229 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 1230 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000 1231 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 1232 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000 1233 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 1234 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000 1235 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 1236 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000 1237 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_DEFAULT 0x00000000 1238 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP_DEFAULT 0x00000000 1239 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL_DEFAULT 0x00000020 1240 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP_DEFAULT 0x00000000 1241 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL_DEFAULT 0x00000000 1242 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP_DEFAULT 0x00000000 1243 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL_DEFAULT 0x00000000 1244 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP_DEFAULT 0x00000000 1245 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL_DEFAULT 0x00000000 1246 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP_DEFAULT 0x00000000 1247 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL_DEFAULT 0x00000000 1248 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP_DEFAULT 0x00000000 1249 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL_DEFAULT 0x00000000 1250 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000 1251 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000 1252 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000 1253 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000 1254 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000 1255 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000 1256 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000 1257 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000 1258 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000 1259 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000 1260 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000 1261 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x0012000c 1262 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_DEFAULT 0x00000000 1263 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_DEFAULT 0x00000000 1264 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000 1265 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000 1266 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000 1267 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000 1268 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000 1269 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000 1270 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000 1271 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000 1272 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000 1273 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000 1274 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000 1275 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000 1276 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000 1277 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000 1278 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000 1279 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000 1280 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_DEFAULT 0x00000000 1281 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_DEFAULT 0x00000000 1282 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_DEFAULT 0x00000000 1283 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_DEFAULT 0x00000000 1284 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_DEFAULT 0x00000000 1285 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_DEFAULT 0x00000000 1286 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_DEFAULT 0x00000000 1287 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_DEFAULT 0x00000000 1288 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_DEFAULT 0x00000000 1289 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_DEFAULT 0x00000000 1290 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_DEFAULT 0x00000000 1291 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_DEFAULT 0x00000000 1292 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_DEFAULT 0x00000000 1293 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_DEFAULT 0x00000000 1294 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_DEFAULT 0x00000000 1295 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000 1296 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000 1297 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000 1298 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000 1299 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000 1300 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000 1301 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000 1302 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000 1303 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000 1304 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000 1305 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000 1306 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000 1307 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000 1308 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000 1309 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000 1310 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000 1311 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000 1312 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000 1313 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000 1314 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000 1315 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000 1316 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000 1317 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000 1318 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000 1319 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000 1320 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000 1321 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000 1322 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0_DEFAULT 0x00000000 1323 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1_DEFAULT 0x00000000 1324 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2_DEFAULT 0x00000000 1325 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3_DEFAULT 0x00000000 1326 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4_DEFAULT 0x00000000 1327 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5_DEFAULT 0x00000000 1328 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6_DEFAULT 0x00000000 1329 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7_DEFAULT 0x00000000 1330 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8_DEFAULT 0x00000000 1331 1332 1333 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp 1334 #define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_ID_DEFAULT 0x00001002 1335 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_ID_DEFAULT 0x00007316 1336 #define cfgBIF_CFG_DEV0_EPF2_0_COMMAND_DEFAULT 0x00000000 1337 #define cfgBIF_CFG_DEV0_EPF2_0_STATUS_DEFAULT 0x00000000 1338 #define cfgBIF_CFG_DEV0_EPF2_0_REVISION_ID_DEFAULT 0x00000000 1339 #define cfgBIF_CFG_DEV0_EPF2_0_PROG_INTERFACE_DEFAULT 0x00000030 1340 #define cfgBIF_CFG_DEV0_EPF2_0_SUB_CLASS_DEFAULT 0x00000003 1341 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_CLASS_DEFAULT 0x0000000c 1342 #define cfgBIF_CFG_DEV0_EPF2_0_CACHE_LINE_DEFAULT 0x00000000 1343 #define cfgBIF_CFG_DEV0_EPF2_0_LATENCY_DEFAULT 0x00000000 1344 #define cfgBIF_CFG_DEV0_EPF2_0_HEADER_DEFAULT 0x00000080 1345 #define cfgBIF_CFG_DEV0_EPF2_0_BIST_DEFAULT 0x00000000 1346 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_1_DEFAULT 0x00000000 1347 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_2_DEFAULT 0x00000000 1348 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_3_DEFAULT 0x00000000 1349 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_4_DEFAULT 0x00000000 1350 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_5_DEFAULT 0x00000000 1351 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_6_DEFAULT 0x00000000 1352 #define cfgBIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 1353 #define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_DEFAULT 0x73161002 1354 #define cfgBIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR_DEFAULT 0x00000000 1355 #define cfgBIF_CFG_DEV0_EPF2_0_CAP_PTR_DEFAULT 0x00000048 1356 #define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE_DEFAULT 0x00000000 1357 #define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN_DEFAULT 0x00000003 1358 #define cfgBIF_CFG_DEV0_EPF2_0_MIN_GRANT_DEFAULT 0x00000000 1359 #define cfgBIF_CFG_DEV0_EPF2_0_MAX_LATENCY_DEFAULT 0x00000000 1360 #define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST_DEFAULT 0x00000000 1361 #define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W_DEFAULT 0x73161002 1362 #define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST_DEFAULT 0x00006400 1363 #define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP_DEFAULT 0x0000c800 1364 #define cfgBIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 1365 #define cfgBIF_CFG_DEV0_EPF2_0_SBRN_DEFAULT 0x00000000 1366 #define cfgBIF_CFG_DEV0_EPF2_0_FLADJ_DEFAULT 0x00000020 1367 #define cfgBIF_CFG_DEV0_EPF2_0_DBESL_DBESLD_DEFAULT 0x00000000 1368 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 1369 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP_DEFAULT 0x00000002 1370 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP_DEFAULT 0x00000f81 1371 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL_DEFAULT 0x00002810 1372 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS_DEFAULT 0x00000000 1373 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP_DEFAULT 0x00000d04 1374 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL_DEFAULT 0x00000000 1375 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS_DEFAULT 0x00000001 1376 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP2_DEFAULT 0x00010000 1377 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2_DEFAULT 0x00000000 1378 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2_DEFAULT 0x00000000 1379 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP2_DEFAULT 0x0000001e 1380 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL2_DEFAULT 0x00000004 1381 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS2_DEFAULT 0x00000001 1382 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST_DEFAULT 0x0000c000 1383 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL_DEFAULT 0x00000086 1384 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 1385 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 1386 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_DEFAULT 0x00000000 1387 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK_DEFAULT 0x00000000 1388 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 1389 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK_64_DEFAULT 0x00000000 1390 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING_DEFAULT 0x00000000 1391 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING_64_DEFAULT 0x00000000 1392 #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST_DEFAULT 0x00000000 1393 #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 1394 #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_TABLE_DEFAULT 0x00000000 1395 #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_PBA_DEFAULT 0x00000000 1396 #define cfgBIF_CFG_DEV0_EPF2_0_SATA_CAP_0_DEFAULT 0x00000000 1397 #define cfgBIF_CFG_DEV0_EPF2_0_SATA_CAP_1_DEFAULT 0x00000000 1398 #define cfgBIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX_DEFAULT 0x00000000 1399 #define cfgBIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA_DEFAULT 0x00000000 1400 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 1401 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 1402 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 1403 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 1404 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 1405 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 1406 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 1407 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 1408 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 1409 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 1410 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 1411 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 1412 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 1413 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 1414 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 1415 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 1416 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 1417 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 1418 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 1419 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 1420 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP_DEFAULT 0x00000000 1421 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020 1422 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP_DEFAULT 0x00000000 1423 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000 1424 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP_DEFAULT 0x00000000 1425 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000 1426 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP_DEFAULT 0x00000000 1427 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000 1428 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP_DEFAULT 0x00000000 1429 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000 1430 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP_DEFAULT 0x00000000 1431 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000 1432 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 1433 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 1434 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 1435 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 1436 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 1437 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP_DEFAULT 0x00000000 1438 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 1439 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS_DEFAULT 0x00000100 1440 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL_DEFAULT 0x00000000 1441 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 1442 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 1443 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 1444 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 1445 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 1446 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 1447 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 1448 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 1449 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 1450 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP_DEFAULT 0x00000000 1451 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 1452 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000 1453 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP_DEFAULT 0x00001000 1454 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL_DEFAULT 0x00000000 1455 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 1456 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP_DEFAULT 0x00000000 1457 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 1458 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000 1459 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000 1460 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 1461 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0_DEFAULT 0x00000000 1462 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1_DEFAULT 0x00000000 1463 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2_DEFAULT 0x00000000 1464 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3_DEFAULT 0x00000000 1465 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4_DEFAULT 0x00000000 1466 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5_DEFAULT 0x00000000 1467 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6_DEFAULT 0x00000000 1468 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7_DEFAULT 0x00000000 1469 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8_DEFAULT 0x00000000 1470 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9_DEFAULT 0x00000000 1471 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10_DEFAULT 0x00000000 1472 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11_DEFAULT 0x00000000 1473 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12_DEFAULT 0x00000000 1474 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13_DEFAULT 0x00000000 1475 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14_DEFAULT 0x00000000 1476 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15_DEFAULT 0x00000000 1477 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16_DEFAULT 0x00000000 1478 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17_DEFAULT 0x00000000 1479 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18_DEFAULT 0x00000000 1480 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19_DEFAULT 0x00000000 1481 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20_DEFAULT 0x00000000 1482 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21_DEFAULT 0x00000000 1483 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22_DEFAULT 0x00000000 1484 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23_DEFAULT 0x00000000 1485 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24_DEFAULT 0x00000000 1486 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25_DEFAULT 0x00000000 1487 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26_DEFAULT 0x00000000 1488 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27_DEFAULT 0x00000000 1489 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28_DEFAULT 0x00000000 1490 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29_DEFAULT 0x00000000 1491 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30_DEFAULT 0x00000000 1492 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31_DEFAULT 0x00000000 1493 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32_DEFAULT 0x00000000 1494 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33_DEFAULT 0x00000000 1495 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34_DEFAULT 0x00000000 1496 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35_DEFAULT 0x00000000 1497 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36_DEFAULT 0x00000000 1498 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37_DEFAULT 0x00000000 1499 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38_DEFAULT 0x00000000 1500 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39_DEFAULT 0x00000000 1501 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40_DEFAULT 0x00000000 1502 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41_DEFAULT 0x00000000 1503 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42_DEFAULT 0x00000000 1504 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43_DEFAULT 0x00000000 1505 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44_DEFAULT 0x00000000 1506 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45_DEFAULT 0x00000000 1507 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46_DEFAULT 0x00000000 1508 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47_DEFAULT 0x00000000 1509 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48_DEFAULT 0x00000000 1510 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49_DEFAULT 0x00000000 1511 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50_DEFAULT 0x00000000 1512 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51_DEFAULT 0x00000000 1513 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52_DEFAULT 0x00000000 1514 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53_DEFAULT 0x00000000 1515 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54_DEFAULT 0x00000000 1516 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55_DEFAULT 0x00000000 1517 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56_DEFAULT 0x00000000 1518 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57_DEFAULT 0x00000000 1519 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58_DEFAULT 0x00000000 1520 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59_DEFAULT 0x00000000 1521 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60_DEFAULT 0x00000000 1522 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61_DEFAULT 0x00000000 1523 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62_DEFAULT 0x00000000 1524 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63_DEFAULT 0x00000000 1525 1526 1527 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp 1528 #define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_ID_DEFAULT 0x00001002 1529 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_ID_DEFAULT 0x00007314 1530 #define cfgBIF_CFG_DEV0_EPF3_0_COMMAND_DEFAULT 0x00000000 1531 #define cfgBIF_CFG_DEV0_EPF3_0_STATUS_DEFAULT 0x00000000 1532 #define cfgBIF_CFG_DEV0_EPF3_0_REVISION_ID_DEFAULT 0x00000000 1533 #define cfgBIF_CFG_DEV0_EPF3_0_PROG_INTERFACE_DEFAULT 0x00000000 1534 #define cfgBIF_CFG_DEV0_EPF3_0_SUB_CLASS_DEFAULT 0x00000080 1535 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_CLASS_DEFAULT 0x0000000c 1536 #define cfgBIF_CFG_DEV0_EPF3_0_CACHE_LINE_DEFAULT 0x00000000 1537 #define cfgBIF_CFG_DEV0_EPF3_0_LATENCY_DEFAULT 0x00000000 1538 #define cfgBIF_CFG_DEV0_EPF3_0_HEADER_DEFAULT 0x00000080 1539 #define cfgBIF_CFG_DEV0_EPF3_0_BIST_DEFAULT 0x00000000 1540 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_1_DEFAULT 0x00000000 1541 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_2_DEFAULT 0x00000000 1542 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_3_DEFAULT 0x00000000 1543 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_4_DEFAULT 0x00000000 1544 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_5_DEFAULT 0x00000000 1545 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_6_DEFAULT 0x00000000 1546 #define cfgBIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 1547 #define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_DEFAULT 0x73141002 1548 #define cfgBIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR_DEFAULT 0x00000000 1549 #define cfgBIF_CFG_DEV0_EPF3_0_CAP_PTR_DEFAULT 0x00000048 1550 #define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE_DEFAULT 0x00000000 1551 #define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN_DEFAULT 0x00000004 1552 #define cfgBIF_CFG_DEV0_EPF3_0_MIN_GRANT_DEFAULT 0x00000000 1553 #define cfgBIF_CFG_DEV0_EPF3_0_MAX_LATENCY_DEFAULT 0x00000000 1554 #define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST_DEFAULT 0x00000000 1555 #define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W_DEFAULT 0x73141002 1556 #define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST_DEFAULT 0x00006400 1557 #define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP_DEFAULT 0x00000000 1558 #define cfgBIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 1559 #define cfgBIF_CFG_DEV0_EPF3_0_SBRN_DEFAULT 0x00000000 1560 #define cfgBIF_CFG_DEV0_EPF3_0_FLADJ_DEFAULT 0x00000020 1561 #define cfgBIF_CFG_DEV0_EPF3_0_DBESL_DBESLD_DEFAULT 0x00000000 1562 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 1563 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP_DEFAULT 0x00000002 1564 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP_DEFAULT 0x00000f81 1565 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL_DEFAULT 0x00002810 1566 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS_DEFAULT 0x00000000 1567 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP_DEFAULT 0x00000d04 1568 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL_DEFAULT 0x00000000 1569 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS_DEFAULT 0x00000001 1570 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP2_DEFAULT 0x00010000 1571 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2_DEFAULT 0x00000000 1572 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2_DEFAULT 0x00000000 1573 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP2_DEFAULT 0x0000001e 1574 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL2_DEFAULT 0x00000004 1575 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS2_DEFAULT 0x00000001 1576 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST_DEFAULT 0x0000c000 1577 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL_DEFAULT 0x00000082 1578 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 1579 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 1580 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_DEFAULT 0x00000000 1581 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK_DEFAULT 0x00000000 1582 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 1583 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK_64_DEFAULT 0x00000000 1584 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING_DEFAULT 0x00000000 1585 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING_64_DEFAULT 0x00000000 1586 #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST_DEFAULT 0x00000000 1587 #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 1588 #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_TABLE_DEFAULT 0x00000000 1589 #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_PBA_DEFAULT 0x00000000 1590 #define cfgBIF_CFG_DEV0_EPF3_0_SATA_CAP_0_DEFAULT 0x00000000 1591 #define cfgBIF_CFG_DEV0_EPF3_0_SATA_CAP_1_DEFAULT 0x00000000 1592 #define cfgBIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX_DEFAULT 0x00000000 1593 #define cfgBIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA_DEFAULT 0x00000000 1594 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 1595 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 1596 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 1597 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 1598 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 1599 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 1600 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 1601 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 1602 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 1603 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 1604 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 1605 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 1606 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 1607 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 1608 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 1609 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 1610 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 1611 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 1612 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 1613 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 1614 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP_DEFAULT 0x00000000 1615 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020 1616 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP_DEFAULT 0x00000000 1617 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000 1618 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP_DEFAULT 0x00000000 1619 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000 1620 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP_DEFAULT 0x00000000 1621 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000 1622 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP_DEFAULT 0x00000000 1623 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000 1624 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP_DEFAULT 0x00000000 1625 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000 1626 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 1627 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 1628 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 1629 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 1630 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 1631 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP_DEFAULT 0x00000000 1632 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 1633 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS_DEFAULT 0x00000100 1634 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL_DEFAULT 0x00000000 1635 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 1636 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 1637 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 1638 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 1639 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 1640 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 1641 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 1642 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 1643 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 1644 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP_DEFAULT 0x00000000 1645 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 1646 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000 1647 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP_DEFAULT 0x00001000 1648 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL_DEFAULT 0x00000000 1649 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 1650 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP_DEFAULT 0x00000000 1651 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 1652 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000 1653 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000 1654 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 1655 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0_DEFAULT 0x00000000 1656 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1_DEFAULT 0x00000000 1657 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2_DEFAULT 0x00000000 1658 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3_DEFAULT 0x00000000 1659 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4_DEFAULT 0x00000000 1660 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5_DEFAULT 0x00000000 1661 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6_DEFAULT 0x00000000 1662 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7_DEFAULT 0x00000000 1663 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8_DEFAULT 0x00000000 1664 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9_DEFAULT 0x00000000 1665 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10_DEFAULT 0x00000000 1666 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11_DEFAULT 0x00000000 1667 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12_DEFAULT 0x00000000 1668 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13_DEFAULT 0x00000000 1669 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14_DEFAULT 0x00000000 1670 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15_DEFAULT 0x00000000 1671 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16_DEFAULT 0x00000000 1672 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17_DEFAULT 0x00000000 1673 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18_DEFAULT 0x00000000 1674 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19_DEFAULT 0x00000000 1675 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20_DEFAULT 0x00000000 1676 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21_DEFAULT 0x00000000 1677 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22_DEFAULT 0x00000000 1678 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23_DEFAULT 0x00000000 1679 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24_DEFAULT 0x00000000 1680 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25_DEFAULT 0x00000000 1681 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26_DEFAULT 0x00000000 1682 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27_DEFAULT 0x00000000 1683 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28_DEFAULT 0x00000000 1684 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29_DEFAULT 0x00000000 1685 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30_DEFAULT 0x00000000 1686 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31_DEFAULT 0x00000000 1687 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32_DEFAULT 0x00000000 1688 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33_DEFAULT 0x00000000 1689 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34_DEFAULT 0x00000000 1690 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35_DEFAULT 0x00000000 1691 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36_DEFAULT 0x00000000 1692 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37_DEFAULT 0x00000000 1693 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38_DEFAULT 0x00000000 1694 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39_DEFAULT 0x00000000 1695 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40_DEFAULT 0x00000000 1696 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41_DEFAULT 0x00000000 1697 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42_DEFAULT 0x00000000 1698 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43_DEFAULT 0x00000000 1699 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44_DEFAULT 0x00000000 1700 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45_DEFAULT 0x00000000 1701 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46_DEFAULT 0x00000000 1702 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47_DEFAULT 0x00000000 1703 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48_DEFAULT 0x00000000 1704 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49_DEFAULT 0x00000000 1705 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50_DEFAULT 0x00000000 1706 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51_DEFAULT 0x00000000 1707 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52_DEFAULT 0x00000000 1708 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53_DEFAULT 0x00000000 1709 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54_DEFAULT 0x00000000 1710 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55_DEFAULT 0x00000000 1711 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56_DEFAULT 0x00000000 1712 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57_DEFAULT 0x00000000 1713 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58_DEFAULT 0x00000000 1714 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59_DEFAULT 0x00000000 1715 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60_DEFAULT 0x00000000 1716 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61_DEFAULT 0x00000000 1717 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62_DEFAULT 0x00000000 1718 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63_DEFAULT 0x00000000 1719 1720 1721 // addressBlock: nbio_nbif0_gdc_GDCDEC 1722 #define smnA2S_CNTL_CL0_DEFAULT 0x02a80540 1723 #define smnA2S_CNTL_CL1_DEFAULT 0x02a825a0 1724 #define smnA2S_CNTL3_CL0_DEFAULT 0x00000000 1725 #define smnA2S_CNTL3_CL1_DEFAULT 0x00000008 1726 #define smnA2S_CNTL_SW0_DEFAULT 0x04040000 1727 #define smnA2S_CNTL_SW1_DEFAULT 0x04040200 1728 #define smnA2S_CNTL_SW2_DEFAULT 0x04040200 1729 #define smnA2S_CPLBUF_ALLOC_CNTL_DEFAULT 0x11100001 1730 #define smnA2S_TAG_ALLOC_0_DEFAULT 0x00000000 1731 #define smnA2S_TAG_ALLOC_1_DEFAULT 0x00000000 1732 #define smnA2S_MISC_CNTL_DEFAULT 0x0005000b 1733 #define smnNGDC_SDP_PORT_CTRL_DEFAULT 0x0000003f 1734 #define smnSHUB_REGS_IF_CTL_DEFAULT 0x00000000 1735 #define smnNGDC_MGCG_CTRL_DEFAULT 0x00000100 1736 #define smnNGDC_RESERVED_0_DEFAULT 0x00000000 1737 #define smnNGDC_RESERVED_1_DEFAULT 0x00000000 1738 #define smnNGDC_SDP_PORT_CTRL_SOCCLK_DEFAULT 0x0000003f 1739 #define smnBIF_SDMA0_DOORBELL_RANGE_DEFAULT 0x00000000 1740 #define smnBIF_SDMA1_DOORBELL_RANGE_DEFAULT 0x00000000 1741 #define smnBIF_IH_DOORBELL_RANGE_DEFAULT 0x00000000 1742 #define smnBIF_MMSCH0_DOORBELL_RANGE_DEFAULT 0x00000000 1743 #define smnBIF_ACV_DOORBELL_RANGE_DEFAULT 0x00000000 1744 #define smnBIF_DOORBELL_FENCE_CNTL_DEFAULT 0x00000000 1745 #define smnS2A_MISC_CNTL_DEFAULT 0x00000000 1746 #define smnNGDC_PG_MISC_CTRL_DEFAULT 0x14006000 1747 #define smnNGDC_PGMST_CTRL_DEFAULT 0x00000000 1748 #define smnNGDC_PGSLV_CTRL_DEFAULT 0x00001084 1749 1750 1751 // addressBlock: nbio_nbif0_syshub_mmreg_syshubdirect 1752 #define smnSYSHUB_DS_CTRL_SOCCLK_DEFAULT 0x00000000 1753 #define smnSYSHUB_DS_CTRL2_SOCCLK_DEFAULT 0x00000100 1754 #define smnSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT 0x00000000 1755 #define smnSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT 0x00000000 1756 #define smnSYSHUB_TRANS_IDLE_SOCCLK_DEFAULT 0x00000000 1757 #define smnSYSHUB_HP_TIMER_SOCCLK_DEFAULT 0x00000100 1758 #define smnSYSHUB_MGCG_CTRL_SOCCLK_DEFAULT 0x00000100 1759 #define smnSYSHUB_CPF_DOORBELL_RS_RESET_SOCCLK_DEFAULT 0x00000000 1760 #define smnSYSHUB_SCRATCH_SOCCLK_DEFAULT 0x00000040 1761 #define smnSYSHUB_CL_MASK_SOCCLK_DEFAULT 0x00000000 1762 #define smnSYSHUB_HANG_CNTL_SOCCLK_DEFAULT 0x00000000 1763 #define smnHST_CLK0_SW0_CL0_CNTL_DEFAULT 0x00000000 1764 #define smnHST_CLK0_SW0_CL1_CNTL_DEFAULT 0x00000000 1765 #define smnHST_CLK0_SW0_CL2_CNTL_DEFAULT 0x00000000 1766 #define smnHST_CLK0_SW1_CL0_CNTL_DEFAULT 0x00000000 1767 #define smnHST_CLK0_SW1_CL1_CNTL_DEFAULT 0x00000000 1768 #define smnHST_CLK0_SW1_CL2_CNTL_DEFAULT 0x00000000 1769 #define smnDMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e 1770 #define smnDMA_CLK0_SW0_CL0_CNTL_DEFAULT 0x20200000 1771 #define smnDMA_CLK0_SW0_CL1_CNTL_DEFAULT 0x20200000 1772 #define smnSYSHUB_DS_CTRL_SHUBCLK_DEFAULT 0x00000000 1773 #define smnSYSHUB_DS_CTRL2_SHUBCLK_DEFAULT 0x00000100 1774 #define smnSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT 0x00000000 1775 #define smnSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT 0x00000000 1776 #define smnSYSHUB_MGCG_CTRL_SHUBCLK_DEFAULT 0x00000100 1777 #define smnSYSHUB_SCRATCH_SHUBCLK_DEFAULT 0x00000040 1778 #define smnSYSHUB_SELECT_SHUBCLK_DEFAULT 0x00000000 1779 #define smnSYSHUB_SCRATCH_LCLK_DEFAULT 0x00000040 1780 #define smnNIC400_0_ASIB_0_FN_MOD_DEFAULT 0x00000000 1781 #define smnNIC400_0_AMIB_0_FN_MOD_BM_ISS_DEFAULT 0x00000000 1782 #define smnNIC400_0_AMIB_1_FN_MOD_BM_ISS_DEFAULT 0x00000000 1783 #define smnNIC400_0_AMIB_2_FN_MOD_BM_ISS_DEFAULT 0x00000000 1784 #define smnNIC400_0_IB_0_FN_MOD_DEFAULT 0x00000000 1785 #define smnNIC400_1_ASIB_0_FN_MOD_DEFAULT 0x00000000 1786 #define smnNIC400_1_AMIB_0_FN_MOD_BM_ISS_DEFAULT 0x00000000 1787 #define smnNIC400_1_AMIB_1_FN_MOD_BM_ISS_DEFAULT 0x00000000 1788 #define smnNIC400_1_AMIB_2_FN_MOD_BM_ISS_DEFAULT 0x00000000 1789 #define smnNIC400_1_IB_0_FN_MOD_DEFAULT 0x00000000 1790 #define smnNIC400_2_AMIB_0_FN_MOD_BM_ISS_DEFAULT 0x00000000 1791 #define smnNIC400_2_ASIB_0_FN_MOD_DEFAULT 0x00000000 1792 #define smnNIC400_2_ASIB_0_QOS_CNTL_DEFAULT 0x00000000 1793 #define smnNIC400_2_ASIB_0_MAX_OT_DEFAULT 0x00000000 1794 #define smnNIC400_2_ASIB_0_MAX_COMB_OT_DEFAULT 0x00000000 1795 #define smnNIC400_2_ASIB_0_AW_P_DEFAULT 0x00000000 1796 #define smnNIC400_2_ASIB_0_AW_B_DEFAULT 0x00000000 1797 #define smnNIC400_2_ASIB_0_AW_R_DEFAULT 0x00000000 1798 #define smnNIC400_2_ASIB_0_AR_P_DEFAULT 0x00000000 1799 #define smnNIC400_2_ASIB_0_AR_B_DEFAULT 0x00000000 1800 #define smnNIC400_2_ASIB_0_AR_R_DEFAULT 0x00000000 1801 #define smnNIC400_2_ASIB_0_TARGET_FC_DEFAULT 0x00000000 1802 #define smnNIC400_2_ASIB_0_KI_FC_DEFAULT 0x00000000 1803 #define smnNIC400_2_ASIB_0_QOS_RANGE_DEFAULT 0x00000000 1804 #define smnNIC400_2_ASIB_1_FN_MOD_DEFAULT 0x00000000 1805 #define smnNIC400_2_ASIB_1_QOS_CNTL_DEFAULT 0x00000000 1806 #define smnNIC400_2_ASIB_1_MAX_OT_DEFAULT 0x00000000 1807 #define smnNIC400_2_ASIB_1_MAX_COMB_OT_DEFAULT 0x00000000 1808 #define smnNIC400_2_ASIB_1_AW_P_DEFAULT 0x00000000 1809 #define smnNIC400_2_ASIB_1_AW_B_DEFAULT 0x00000000 1810 #define smnNIC400_2_ASIB_1_AW_R_DEFAULT 0x00000000 1811 #define smnNIC400_2_ASIB_1_AR_P_DEFAULT 0x00000000 1812 #define smnNIC400_2_ASIB_1_AR_B_DEFAULT 0x00000000 1813 #define smnNIC400_2_ASIB_1_AR_R_DEFAULT 0x00000000 1814 #define smnNIC400_2_ASIB_1_TARGET_FC_DEFAULT 0x00000000 1815 #define smnNIC400_2_ASIB_1_KI_FC_DEFAULT 0x00000000 1816 #define smnNIC400_2_ASIB_1_QOS_RANGE_DEFAULT 0x00000000 1817 #define smnNIC400_2_IB_0_FN_MOD_DEFAULT 0x00000000 1818 1819 1820 // addressBlock: nbio_nbif0_nbif_sion_SIONDEC 1821 #define smnSION_CL0_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 1822 #define smnSION_CL0_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 1823 #define smnSION_CL0_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 1824 #define smnSION_CL0_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 1825 #define smnSION_CL0_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 1826 #define smnSION_CL0_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 1827 #define smnSION_CL0_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 1828 #define smnSION_CL0_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 1829 #define smnSION_CL0_Req_BurstTarget_REG0_DEFAULT 0x00000000 1830 #define smnSION_CL0_Req_BurstTarget_REG1_DEFAULT 0x00000000 1831 #define smnSION_CL0_Req_TimeSlot_REG0_DEFAULT 0x00000000 1832 #define smnSION_CL0_Req_TimeSlot_REG1_DEFAULT 0x00000000 1833 #define smnSION_CL0_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 1834 #define smnSION_CL0_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 1835 #define smnSION_CL0_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 1836 #define smnSION_CL0_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 1837 #define smnSION_CL0_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 1838 #define smnSION_CL0_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 1839 #define smnSION_CL0_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 1840 #define smnSION_CL0_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 1841 #define smnSION_CL1_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 1842 #define smnSION_CL1_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 1843 #define smnSION_CL1_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 1844 #define smnSION_CL1_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 1845 #define smnSION_CL1_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 1846 #define smnSION_CL1_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 1847 #define smnSION_CL1_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 1848 #define smnSION_CL1_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 1849 #define smnSION_CL1_Req_BurstTarget_REG0_DEFAULT 0x00000000 1850 #define smnSION_CL1_Req_BurstTarget_REG1_DEFAULT 0x00000000 1851 #define smnSION_CL1_Req_TimeSlot_REG0_DEFAULT 0x00000000 1852 #define smnSION_CL1_Req_TimeSlot_REG1_DEFAULT 0x00000000 1853 #define smnSION_CL1_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 1854 #define smnSION_CL1_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 1855 #define smnSION_CL1_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 1856 #define smnSION_CL1_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 1857 #define smnSION_CL1_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 1858 #define smnSION_CL1_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 1859 #define smnSION_CL1_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 1860 #define smnSION_CL1_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 1861 #define smnSION_CL2_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 1862 #define smnSION_CL2_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 1863 #define smnSION_CL2_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 1864 #define smnSION_CL2_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 1865 #define smnSION_CL2_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 1866 #define smnSION_CL2_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 1867 #define smnSION_CL2_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 1868 #define smnSION_CL2_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 1869 #define smnSION_CL2_Req_BurstTarget_REG0_DEFAULT 0x00000000 1870 #define smnSION_CL2_Req_BurstTarget_REG1_DEFAULT 0x00000000 1871 #define smnSION_CL2_Req_TimeSlot_REG0_DEFAULT 0x00000000 1872 #define smnSION_CL2_Req_TimeSlot_REG1_DEFAULT 0x00000000 1873 #define smnSION_CL2_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 1874 #define smnSION_CL2_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 1875 #define smnSION_CL2_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 1876 #define smnSION_CL2_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 1877 #define smnSION_CL2_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 1878 #define smnSION_CL2_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 1879 #define smnSION_CL2_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 1880 #define smnSION_CL2_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 1881 #define smnSION_CL3_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 1882 #define smnSION_CL3_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 1883 #define smnSION_CL3_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 1884 #define smnSION_CL3_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 1885 #define smnSION_CL3_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 1886 #define smnSION_CL3_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 1887 #define smnSION_CL3_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 1888 #define smnSION_CL3_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 1889 #define smnSION_CL3_Req_BurstTarget_REG0_DEFAULT 0x00000000 1890 #define smnSION_CL3_Req_BurstTarget_REG1_DEFAULT 0x00000000 1891 #define smnSION_CL3_Req_TimeSlot_REG0_DEFAULT 0x00000000 1892 #define smnSION_CL3_Req_TimeSlot_REG1_DEFAULT 0x00000000 1893 #define smnSION_CL3_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 1894 #define smnSION_CL3_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 1895 #define smnSION_CL3_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 1896 #define smnSION_CL3_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 1897 #define smnSION_CL3_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 1898 #define smnSION_CL3_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 1899 #define smnSION_CL3_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 1900 #define smnSION_CL3_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 1901 #define smnSION_CNTL_REG0_DEFAULT 0x00000000 1902 #define smnSION_CNTL_REG1_DEFAULT 0x00000000 1903 1904 1905 // addressBlock: nbio_nbif0_gdc_rst_GDCRST_DEC 1906 #define smnSHUB_PF_FLR_RST_DEFAULT 0x00000000 1907 #define smnSHUB_GFX_DRV_VPU_RST_DEFAULT 0x00000000 1908 #define smnSHUB_LINK_RESET_DEFAULT 0x00000000 1909 #define smnSHUB_PF0_VF_FLR_RST_DEFAULT 0x00000000 1910 #define smnSHUB_HARD_RST_CTRL_DEFAULT 0x0000003b 1911 #define smnSHUB_SOFT_RST_CTRL_DEFAULT 0x00000009 1912 #define smnSHUB_SDP_PORT_RST_DEFAULT 0x00000000 1913 #define smnSHUB_RST_MISC_TRL_DEFAULT 0x00100001 1914 1915 1916 // addressBlock: nbio_nbif0_gdc_ras_gdc_ras_regblk 1917 #define smnGDCL_RAS_CENTRAL_STATUS_DEFAULT 0x00000000 1918 #define smnGDCSOC_RAS_CENTRAL_STATUS_DEFAULT 0x00000000 1919 #define smnGDCSOC_RAS_LEAF0_CTRL_DEFAULT 0x00000f61 1920 #define smnGDCSOC_RAS_LEAF1_CTRL_DEFAULT 0x00000f61 1921 #define smnGDCSOC_RAS_LEAF2_CTRL_DEFAULT 0x00010f01 1922 #define smnGDCSOC_RAS_LEAF3_CTRL_DEFAULT 0x00000f61 1923 #define smnGDCSOC_RAS_LEAF4_CTRL_DEFAULT 0x00000f61 1924 #define smnGDCSOC_RAS_LEAF5_CTRL_DEFAULT 0x00000f61 1925 #define smnGDCSOC_RAS_LEAF2_MISC_CTRL_DEFAULT 0x00000202 1926 #define smnGDCSOC_RAS_LEAF2_MISC_CTRL2_DEFAULT 0x0013ff21 1927 #define smnGDCSOC_RAS_LEAF0_STATUS_DEFAULT 0x00000000 1928 #define smnGDCSOC_RAS_LEAF1_STATUS_DEFAULT 0x00000000 1929 #define smnGDCSOC_RAS_LEAF2_STATUS_DEFAULT 0x00000000 1930 #define smnGDCSOC_RAS_LEAF3_STATUS_DEFAULT 0x00000000 1931 #define smnGDCSOC_RAS_LEAF4_STATUS_DEFAULT 0x00000000 1932 #define smnGDCSOC_RAS_LEAF5_STATUS_DEFAULT 0x00000000 1933 #define smnGDCSHUB_RAS_CENTRAL_STATUS_DEFAULT 0x00000000 1934 1935 1936 // addressBlock: nbio_nbif0_bif_cfg_dev0_swds_bifcfgdecp 1937 #define smnBIF_CFG_DEV0_SWDS_VENDOR_ID_DEFAULT 0x00001002 1938 #define smnBIF_CFG_DEV0_SWDS_DEVICE_ID_DEFAULT 0x00000000 1939 #define smnBIF_CFG_DEV0_SWDS_COMMAND_DEFAULT 0x00000000 1940 #define smnBIF_CFG_DEV0_SWDS_STATUS_DEFAULT 0x00000000 1941 #define smnBIF_CFG_DEV0_SWDS_REVISION_ID_DEFAULT 0x00000000 1942 #define smnBIF_CFG_DEV0_SWDS_PROG_INTERFACE_DEFAULT 0x00000000 1943 #define smnBIF_CFG_DEV0_SWDS_SUB_CLASS_DEFAULT 0x00000004 1944 #define smnBIF_CFG_DEV0_SWDS_BASE_CLASS_DEFAULT 0x00000006 1945 #define smnBIF_CFG_DEV0_SWDS_CACHE_LINE_DEFAULT 0x00000000 1946 #define smnBIF_CFG_DEV0_SWDS_LATENCY_DEFAULT 0x00000000 1947 #define smnBIF_CFG_DEV0_SWDS_HEADER_DEFAULT 0x00000000 1948 #define smnBIF_CFG_DEV0_SWDS_BIST_DEFAULT 0x00000000 1949 #define smnBIF_CFG_DEV0_SWDS_BASE_ADDR_1_DEFAULT 0x00000000 1950 #define smnBIF_CFG_DEV0_SWDS_BASE_ADDR_2_DEFAULT 0x00000000 1951 #define smnSUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 1952 #define smnIO_BASE_LIMIT_DEFAULT 0x00000000 1953 #define smnSECONDARY_STATUS_DEFAULT 0x00000000 1954 #define smnMEM_BASE_LIMIT_DEFAULT 0x00000000 1955 #define smnPREF_BASE_LIMIT_DEFAULT 0x00000000 1956 #define smnPREF_BASE_UPPER_DEFAULT 0x00000000 1957 #define smnPREF_LIMIT_UPPER_DEFAULT 0x00000000 1958 #define smnIO_BASE_LIMIT_HI_DEFAULT 0x00000000 1959 #define smnBIF_CFG_DEV0_SWDS_CAP_PTR_DEFAULT 0x00000000 1960 #define smnBIF_CFG_DEV0_SWDS_ROM_BASE_ADDR_DEFAULT 0x00000000 1961 #define smnBIF_CFG_DEV0_SWDS_INTERRUPT_LINE_DEFAULT 0x000000ff 1962 #define smnBIF_CFG_DEV0_SWDS_INTERRUPT_PIN_DEFAULT 0x00000000 1963 #define smnIRQ_BRIDGE_CNTL_DEFAULT 0x00000000 1964 #define smnBIF_CFG_DEV0_SWDS_PMI_CAP_LIST_DEFAULT 0x00000000 1965 #define smnBIF_CFG_DEV0_SWDS_PMI_CAP_DEFAULT 0x0000c800 1966 #define smnBIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL_DEFAULT 0x00000000 1967 #define smnBIF_CFG_DEV0_SWDS_PCIE_CAP_LIST_DEFAULT 0x0000a000 1968 #define smnBIF_CFG_DEV0_SWDS_PCIE_CAP_DEFAULT 0x00000062 1969 #define smnBIF_CFG_DEV0_SWDS_DEVICE_CAP_DEFAULT 0x00000000 1970 #define smnBIF_CFG_DEV0_SWDS_DEVICE_CNTL_DEFAULT 0x00002810 1971 #define smnBIF_CFG_DEV0_SWDS_DEVICE_STATUS_DEFAULT 0x00000000 1972 #define smnBIF_CFG_DEV0_SWDS_LINK_CAP_DEFAULT 0x00000d04 1973 #define smnBIF_CFG_DEV0_SWDS_LINK_CNTL_DEFAULT 0x00000000 1974 #define smnBIF_CFG_DEV0_SWDS_LINK_STATUS_DEFAULT 0x00002001 1975 #define smnSLOT_CAP_DEFAULT 0x00000000 1976 #define smnSLOT_CNTL_DEFAULT 0x00000000 1977 #define smnSLOT_STATUS_DEFAULT 0x00000000 1978 #define smnBIF_CFG_DEV0_SWDS_DEVICE_CAP2_DEFAULT 0x00010000 1979 #define smnBIF_CFG_DEV0_SWDS_DEVICE_CNTL2_DEFAULT 0x00000000 1980 #define smnBIF_CFG_DEV0_SWDS_DEVICE_STATUS2_DEFAULT 0x00000000 1981 #define smnBIF_CFG_DEV0_SWDS_LINK_CAP2_DEFAULT 0x0000001e 1982 #define smnBIF_CFG_DEV0_SWDS_LINK_CNTL2_DEFAULT 0x00000004 1983 #define smnBIF_CFG_DEV0_SWDS_LINK_STATUS2_DEFAULT 0x00000000 1984 #define smnSLOT_CAP2_DEFAULT 0x00000000 1985 #define smnSLOT_CNTL2_DEFAULT 0x00000000 1986 #define smnSLOT_STATUS2_DEFAULT 0x00000000 1987 #define smnBIF_CFG_DEV0_SWDS_MSI_CAP_LIST_DEFAULT 0x0000c000 1988 #define smnBIF_CFG_DEV0_SWDS_MSI_MSG_CNTL_DEFAULT 0x00000080 1989 #define smnBIF_CFG_DEV0_SWDS_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 1990 #define smnBIF_CFG_DEV0_SWDS_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 1991 #define smnBIF_CFG_DEV0_SWDS_MSI_MSG_DATA_DEFAULT 0x00000000 1992 #define smnBIF_CFG_DEV0_SWDS_MSI_MSG_DATA_64_DEFAULT 0x00000000 1993 #define smnSSID_CAP_LIST_DEFAULT 0x00000000 1994 #define smnSSID_CAP_DEFAULT 0x00000000 1995 #define smnBIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 1996 #define smnBIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 1997 #define smnBIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 1998 #define smnBIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 1999 #define smnBIF_CFG_DEV0_SWDS_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 2000 #define smnBIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 2001 #define smnBIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 2002 #define smnBIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 2003 #define smnBIF_CFG_DEV0_SWDS_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 2004 #define smnBIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 2005 #define smnBIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe 2006 #define smnBIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 2007 #define smnBIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 2008 #define smnBIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 2009 #define smnBIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 2010 #define smnBIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 2011 #define smnBIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 2012 #define smnBIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 2013 #define smnBIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 2014 #define smnBIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 2015 #define smnBIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 2016 #define smnBIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 2017 #define smnBIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 2018 #define smnBIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 2019 #define smnBIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 2020 #define smnBIF_CFG_DEV0_SWDS_PCIE_HDR_LOG0_DEFAULT 0x00000000 2021 #define smnBIF_CFG_DEV0_SWDS_PCIE_HDR_LOG1_DEFAULT 0x00000000 2022 #define smnBIF_CFG_DEV0_SWDS_PCIE_HDR_LOG2_DEFAULT 0x00000000 2023 #define smnBIF_CFG_DEV0_SWDS_PCIE_HDR_LOG3_DEFAULT 0x00000000 2024 #define smnBIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 2025 #define smnBIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 2026 #define smnBIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 2027 #define smnBIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 2028 #define smnBIF_CFG_DEV0_SWDS_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 2029 #define smnBIF_CFG_DEV0_SWDS_PCIE_LINK_CNTL3_DEFAULT 0x00000000 2030 #define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 2031 #define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 2032 #define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 2033 #define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 2034 #define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 2035 #define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 2036 #define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 2037 #define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 2038 #define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 2039 #define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 2040 #define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 2041 #define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 2042 #define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 2043 #define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 2044 #define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 2045 #define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 2046 #define smnBIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 2047 #define smnBIF_CFG_DEV0_SWDS_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 2048 #define smnBIF_CFG_DEV0_SWDS_PCIE_ACS_CAP_DEFAULT 0x00000000 2049 #define smnBIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL_DEFAULT 0x00000000 2050 #define smnBIF_CFG_DEV0_SWDS_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41000000 2051 #define smnBIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_CAP_DEFAULT 0x00000001 2052 #define smnBIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000 2053 #define smnBIF_CFG_DEV0_SWDS_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44000000 2054 #define smnBIF_CFG_DEV0_SWDS_LINK_CAP_16GT_DEFAULT 0x00000000 2055 #define smnBIF_CFG_DEV0_SWDS_LINK_CNTL_16GT_DEFAULT 0x00000000 2056 #define smnBIF_CFG_DEV0_SWDS_LINK_STATUS_16GT_DEFAULT 0x00000000 2057 #define smnBIF_CFG_DEV0_SWDS_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 2058 #define smnBIF_CFG_DEV0_SWDS_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 2059 #define smnBIF_CFG_DEV0_SWDS_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 2060 #define smnBIF_CFG_DEV0_SWDS_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 2061 #define smnBIF_CFG_DEV0_SWDS_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 2062 #define smnBIF_CFG_DEV0_SWDS_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 2063 #define smnBIF_CFG_DEV0_SWDS_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 2064 #define smnBIF_CFG_DEV0_SWDS_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 2065 #define smnBIF_CFG_DEV0_SWDS_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 2066 #define smnBIF_CFG_DEV0_SWDS_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 2067 #define smnBIF_CFG_DEV0_SWDS_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 2068 #define smnBIF_CFG_DEV0_SWDS_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 2069 #define smnBIF_CFG_DEV0_SWDS_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 2070 #define smnBIF_CFG_DEV0_SWDS_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 2071 #define smnBIF_CFG_DEV0_SWDS_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 2072 #define smnBIF_CFG_DEV0_SWDS_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 2073 #define smnBIF_CFG_DEV0_SWDS_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 2074 #define smnBIF_CFG_DEV0_SWDS_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 2075 #define smnBIF_CFG_DEV0_SWDS_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 2076 #define smnBIF_CFG_DEV0_SWDS_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x4c000000 2077 #define smnBIF_CFG_DEV0_SWDS_MARGINING_PORT_CAP_DEFAULT 0x00000000 2078 #define smnBIF_CFG_DEV0_SWDS_MARGINING_PORT_STATUS_DEFAULT 0x00000000 2079 #define smnBIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 2080 #define smnBIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000 2081 #define smnBIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 2082 #define smnBIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000 2083 #define smnBIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 2084 #define smnBIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000 2085 #define smnBIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 2086 #define smnBIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000 2087 #define smnBIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 2088 #define smnBIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000 2089 #define smnBIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 2090 #define smnBIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000 2091 #define smnBIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 2092 #define smnBIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000 2093 #define smnBIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 2094 #define smnBIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000 2095 #define smnBIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 2096 #define smnBIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000 2097 #define smnBIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 2098 #define smnBIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000 2099 #define smnBIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 2100 #define smnBIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000 2101 #define smnBIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 2102 #define smnBIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000 2103 #define smnBIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 2104 #define smnBIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000 2105 #define smnBIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 2106 #define smnBIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000 2107 #define smnBIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 2108 #define smnBIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000 2109 #define smnBIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 2110 #define smnBIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000 2111 2112 2113 // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC 2114 #define smnMM_INDEX_DEFAULT 0x00000000 2115 #define smnMM_DATA_DEFAULT 0x00000000 2116 #define smnMM_INDEX_HI_DEFAULT 0x00000000 2117 2118 2119 // addressBlock: nbio_nbif0_bif_bx_SYSDEC 2120 #define smnSYSHUB_INDEX_OVLP_DEFAULT 0x00000000 2121 #define smnSYSHUB_DATA_OVLP_DEFAULT 0x00000000 2122 #define smnPCIE_INDEX_DEFAULT 0x00000000 2123 #define smnPCIE_DATA_DEFAULT 0x00000000 2124 #define smnPCIE_INDEX2_DEFAULT 0x00000000 2125 #define smnPCIE_DATA2_DEFAULT 0x00000000 2126 #define smnSBIOS_SCRATCH_0_DEFAULT 0x00000000 2127 #define smnSBIOS_SCRATCH_1_DEFAULT 0x00000000 2128 #define smnSBIOS_SCRATCH_2_DEFAULT 0x00000000 2129 #define smnSBIOS_SCRATCH_3_DEFAULT 0x00000000 2130 #define smnBIOS_SCRATCH_0_DEFAULT 0x00000000 2131 #define smnBIOS_SCRATCH_1_DEFAULT 0x00000000 2132 #define smnBIOS_SCRATCH_2_DEFAULT 0x00000000 2133 #define smnBIOS_SCRATCH_3_DEFAULT 0x00000000 2134 #define smnBIOS_SCRATCH_4_DEFAULT 0x00000000 2135 #define smnBIOS_SCRATCH_5_DEFAULT 0x00000000 2136 #define smnBIOS_SCRATCH_6_DEFAULT 0x00000000 2137 #define smnBIOS_SCRATCH_7_DEFAULT 0x00000000 2138 #define smnBIOS_SCRATCH_8_DEFAULT 0x00000000 2139 #define smnBIOS_SCRATCH_9_DEFAULT 0x00000000 2140 #define smnBIOS_SCRATCH_10_DEFAULT 0x00000000 2141 #define smnBIOS_SCRATCH_11_DEFAULT 0x00000000 2142 #define smnBIOS_SCRATCH_12_DEFAULT 0x00000000 2143 #define smnBIOS_SCRATCH_13_DEFAULT 0x00000000 2144 #define smnBIOS_SCRATCH_14_DEFAULT 0x00000000 2145 #define smnBIOS_SCRATCH_15_DEFAULT 0x00000000 2146 #define smnBIF_RLC_INTR_CNTL_DEFAULT 0x00000000 2147 #define smnBIF_VCE_INTR_CNTL_DEFAULT 0x00000000 2148 #define smnBIF_UVD_INTR_CNTL_DEFAULT 0x00000000 2149 #define smnGFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000 2150 #define smnGFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000 2151 #define smnGFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000 2152 #define smnGFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000 2153 #define smnGFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000 2154 #define smnGFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000 2155 #define smnGFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000 2156 #define smnGFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000 2157 #define smnGFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000 2158 #define smnGFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000 2159 #define smnGFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000 2160 #define smnGFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000 2161 #define smnGFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000 2162 #define smnGFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000 2163 #define smnGFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000 2164 #define smnGFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000 2165 #define smnGFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000 2166 #define smnGFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000 2167 #define smnGFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000 2168 #define smnGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000 2169 2170 2171 // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 2172 #define smnRCC_STRAP0_RCC_BIF_STRAP0_DEFAULT 0x00040a00 2173 #define smnRCC_STRAP0_RCC_BIF_STRAP1_DEFAULT 0x00400108 2174 #define smnRCC_STRAP0_RCC_BIF_STRAP2_DEFAULT 0x000a0079 2175 #define smnRCC_STRAP0_RCC_BIF_STRAP3_DEFAULT 0x00000000 2176 #define smnRCC_STRAP0_RCC_BIF_STRAP4_DEFAULT 0x00100010 2177 #define smnRCC_STRAP0_RCC_BIF_STRAP5_DEFAULT 0x31130010 2178 #define smnRCC_STRAP0_RCC_BIF_STRAP6_DEFAULT 0x00000000 2179 #define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP0_DEFAULT 0x54228f20 2180 #define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP1_DEFAULT 0x10221479 2181 #define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP2_DEFAULT 0x1c6fe009 2182 #define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849 2183 #define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000 2184 #define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000 2185 #define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP6_DEFAULT 0x0000ff02 2186 #define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000 2187 #define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP8_DEFAULT 0x00000000 2188 #define smnRCC_STRAP0_RCC_DEV0_PORT_STRAP9_DEFAULT 0x00000000 2189 #define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_DEFAULT 0x30007310 2190 #define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000 2191 #define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000 2192 #define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP2_DEFAULT 0x02002000 2193 #define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b5cc41 2194 #define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP4_DEFAULT 0x1f000000 2195 #define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP5_DEFAULT 0x00001002 2196 #define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP8_DEFAULT 0xcb026001 2197 #define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP9_DEFAULT 0x00000100 2198 #define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP0_DEFAULT 0x3000ab38 2199 #define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP10_DEFAULT 0x00000000 2200 #define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP11_DEFAULT 0x00000000 2201 #define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP12_DEFAULT 0x00000000 2202 #define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP13_DEFAULT 0x00000000 2203 #define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP2_DEFAULT 0x00002000 2204 #define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP3_DEFAULT 0x0806ace1 2205 #define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP4_DEFAULT 0x2f000000 2206 #define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP5_DEFAULT 0x00001002 2207 #define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP6_DEFAULT 0x00000000 2208 #define smnRCC_STRAP0_RCC_DEV0_EPF1_STRAP7_DEFAULT 0x00000000 2209 2210 2211 // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 2212 #define smnRCC_EP_DEV0_0_EP_PCIE_SCRATCH_DEFAULT 0x00000000 2213 #define smnRCC_EP_DEV0_0_EP_PCIE_CNTL_DEFAULT 0x00000000 2214 #define smnRCC_EP_DEV0_0_EP_PCIE_INT_CNTL_DEFAULT 0x00000000 2215 #define smnRCC_EP_DEV0_0_EP_PCIE_INT_STATUS_DEFAULT 0x00000000 2216 #define smnRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2_DEFAULT 0x00000000 2217 #define smnRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL_DEFAULT 0x00000080 2218 #define smnRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL_DEFAULT 0x00000000 2219 #define smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL_DEFAULT 0x00007468 2220 #define smnPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa 2221 #define smnPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 2222 #define smnPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 2223 #define smnPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 2224 #define smnPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b 2225 #define smnPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 2226 #define smnPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 2227 #define smnPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a 2228 #define smnRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC_DEFAULT 0x00000000 2229 #define smnRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2_DEFAULT 0x00000000 2230 #define smnRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000 2231 #define smnRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0 2232 #define smnRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100 2233 #define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa 2234 #define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 2235 #define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 2236 #define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 2237 #define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b 2238 #define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 2239 #define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 2240 #define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a 2241 #define smnRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL_DEFAULT 0x00000000 2242 #define smnRCC_EP_DEV0_0_EP_PCIEP_RESERVED_DEFAULT 0x00000000 2243 #define smnRCC_EP_DEV0_0_EP_PCIE_TX_CNTL_DEFAULT 0x00000000 2244 #define smnRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 2245 #define smnRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL_DEFAULT 0x00000500 2246 #define smnRCC_EP_DEV0_0_EP_PCIE_RX_CNTL_DEFAULT 0x01000000 2247 #define smnRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 2248 2249 2250 // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 2251 #define smnRCC_DWN_DEV0_0_DN_PCIE_RESERVED_DEFAULT 0x00000000 2252 #define smnRCC_DWN_DEV0_0_DN_PCIE_SCRATCH_DEFAULT 0x00000000 2253 #define smnRCC_DWN_DEV0_0_DN_PCIE_CNTL_DEFAULT 0x00000000 2254 #define smnRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000 2255 #define smnRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2_DEFAULT 0x00000000 2256 #define smnRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL_DEFAULT 0x00000080 2257 #define smnRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL_DEFAULT 0x00000000 2258 #define smnRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0_DEFAULT 0x00000001 2259 #define smnRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC_DEFAULT 0x00000000 2260 #define smnRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2_DEFAULT 0x00000000 2261 2262 2263 // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 2264 #define smnRCC_DWNP_DEV0_0_PCIE_ERR_CNTL_DEFAULT 0x00000500 2265 #define smnRCC_DWNP_DEV0_0_PCIE_RX_CNTL_DEFAULT 0x00000000 2266 #define smnRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 2267 #define smnRCC_DWNP_DEV0_0_PCIE_LC_CNTL2_DEFAULT 0x00000000 2268 #define smnRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC_DEFAULT 0x00000000 2269 #define smnRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000 2270 2271 2272 // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 2273 #define smnRCC_ERR_INT_CNTL_DEFAULT 0x00000000 2274 #define smnRCC_BACO_CNTL_MISC_DEFAULT 0x00000000 2275 #define smnRCC_RESET_EN_DEFAULT 0x00008000 2276 #define smnRCC_DEV0_0_RCC_VDM_SUPPORT_DEFAULT 0x00000000 2277 #define smnRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0_DEFAULT 0x0a80a0df 2278 #define smnRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1_DEFAULT 0x0000f000 2279 #define smnRCC_GPUIOV_REGION_DEFAULT 0x00000000 2280 #define smnRCC_PEER_REG_RANGE0_DEFAULT 0xffff0000 2281 #define smnRCC_PEER_REG_RANGE1_DEFAULT 0xffff0000 2282 #define smnRCC_DEV0_0_RCC_BUS_CNTL_DEFAULT 0x00000000 2283 #define smnRCC_CONFIG_CNTL_DEFAULT 0x00000000 2284 #define smnRCC_CONFIG_F0_BASE_DEFAULT 0x00000000 2285 #define smnRCC_CONFIG_APER_SIZE_DEFAULT 0x00000000 2286 #define smnRCC_CONFIG_REG_APER_SIZE_DEFAULT 0x00000000 2287 #define smnRCC_XDMA_LO_DEFAULT 0x00000000 2288 #define smnRCC_XDMA_HI_DEFAULT 0x00000000 2289 #define smnRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC_DEFAULT 0x00000000 2290 #define smnRCC_BUSNUM_CNTL1_DEFAULT 0x00000000 2291 #define smnRCC_BUSNUM_LIST0_DEFAULT 0x00000000 2292 #define smnRCC_BUSNUM_LIST1_DEFAULT 0x00000000 2293 #define smnRCC_BUSNUM_CNTL2_DEFAULT 0x00000000 2294 #define smnRCC_CAPTURE_HOST_BUSNUM_DEFAULT 0x00000000 2295 #define smnRCC_HOST_BUSNUM_DEFAULT 0x00000000 2296 #define smnRCC_PEER0_FB_OFFSET_HI_DEFAULT 0x00000000 2297 #define smnRCC_PEER0_FB_OFFSET_LO_DEFAULT 0x00000000 2298 #define smnRCC_PEER1_FB_OFFSET_HI_DEFAULT 0x00000000 2299 #define smnRCC_PEER1_FB_OFFSET_LO_DEFAULT 0x00000000 2300 #define smnRCC_PEER2_FB_OFFSET_HI_DEFAULT 0x00000000 2301 #define smnRCC_PEER2_FB_OFFSET_LO_DEFAULT 0x00000000 2302 #define smnRCC_PEER3_FB_OFFSET_HI_DEFAULT 0x00000000 2303 #define smnRCC_PEER3_FB_OFFSET_LO_DEFAULT 0x00000000 2304 #define smnRCC_DEVFUNCNUM_LIST0_DEFAULT 0x00000000 2305 #define smnRCC_DEVFUNCNUM_LIST1_DEFAULT 0x00000000 2306 #define smnRCC_DEV0_0_RCC_DEV0_LINK_CNTL_DEFAULT 0x00000000 2307 #define smnRCC_DEV0_0_RCC_CMN_LINK_CNTL_DEFAULT 0x00400000 2308 #define smnRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE_DEFAULT 0x00000000 2309 #define smnRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL_DEFAULT 0x00000000 2310 #define smnRCC_DEV0_0_RCC_MH_ARB_CNTL_DEFAULT 0x00000000 2311 2312 2313 // addressBlock: nbio_nbif0_bif_bx_BIFDEC1 2314 #define smnCC_BIF_BX_STRAP0_DEFAULT 0x00000000 2315 #define smnCC_BIF_BX_PINSTRAP0_DEFAULT 0x00000000 2316 #define smnBIF_MM_INDACCESS_CNTL_DEFAULT 0x00000000 2317 #define smnBUS_CNTL_DEFAULT 0x00000000 2318 #define smnBIF_SCRATCH0_DEFAULT 0x00000000 2319 #define smnBIF_SCRATCH1_DEFAULT 0x00000000 2320 #define smnBX_RESET_EN_DEFAULT 0x00010000 2321 #define smnMM_CFGREGS_CNTL_DEFAULT 0x00000000 2322 #define smnBX_RESET_CNTL_DEFAULT 0x00000000 2323 #define smnINTERRUPT_CNTL_DEFAULT 0x00000000 2324 #define smnINTERRUPT_CNTL2_DEFAULT 0x00000000 2325 #define smnCLKREQB_PAD_CNTL_DEFAULT 0x000008e0 2326 #define smnBIF_FEATURES_CONTROL_MISC_DEFAULT 0x00800000 2327 #define smnBIF_DOORBELL_CNTL_DEFAULT 0x00000000 2328 #define smnBIF_DOORBELL_INT_CNTL_DEFAULT 0x00000000 2329 #define smnBIF_FB_EN_DEFAULT 0x00000000 2330 #define smnBIF_INTR_CNTL_DEFAULT 0x00000000 2331 #define smnBIF_MST_TRANS_PENDING_VF_DEFAULT 0x00000000 2332 #define smnBIF_SLV_TRANS_PENDING_VF_DEFAULT 0x00000000 2333 #define smnBACO_CNTL_DEFAULT 0x00000000 2334 #define smnBIF_BACO_EXIT_TIME0_DEFAULT 0x00000100 2335 #define smnBIF_BACO_EXIT_TIMER1_DEFAULT 0x1c000200 2336 #define smnBIF_BACO_EXIT_TIMER2_DEFAULT 0x00000300 2337 #define smnBIF_BACO_EXIT_TIMER3_DEFAULT 0x00000500 2338 #define smnBIF_BACO_EXIT_TIMER4_DEFAULT 0x00000400 2339 #define smnMEM_TYPE_CNTL_DEFAULT 0x00000000 2340 #define smnNBIF_GFX_ADDR_LUT_CNTL_DEFAULT 0x00000000 2341 #define smnNBIF_GFX_ADDR_LUT_0_DEFAULT 0x00000000 2342 #define smnNBIF_GFX_ADDR_LUT_1_DEFAULT 0x00000001 2343 #define smnNBIF_GFX_ADDR_LUT_2_DEFAULT 0x00000002 2344 #define smnNBIF_GFX_ADDR_LUT_3_DEFAULT 0x00000003 2345 #define smnNBIF_GFX_ADDR_LUT_4_DEFAULT 0x00000004 2346 #define smnNBIF_GFX_ADDR_LUT_5_DEFAULT 0x00000005 2347 #define smnNBIF_GFX_ADDR_LUT_6_DEFAULT 0x00000006 2348 #define smnNBIF_GFX_ADDR_LUT_7_DEFAULT 0x00000007 2349 #define smnNBIF_GFX_ADDR_LUT_8_DEFAULT 0x00000008 2350 #define smnNBIF_GFX_ADDR_LUT_9_DEFAULT 0x00000009 2351 #define smnNBIF_GFX_ADDR_LUT_10_DEFAULT 0x0000000a 2352 #define smnNBIF_GFX_ADDR_LUT_11_DEFAULT 0x0000000b 2353 #define smnNBIF_GFX_ADDR_LUT_12_DEFAULT 0x0000000c 2354 #define smnNBIF_GFX_ADDR_LUT_13_DEFAULT 0x0000000d 2355 #define smnNBIF_GFX_ADDR_LUT_14_DEFAULT 0x0000000e 2356 #define smnNBIF_GFX_ADDR_LUT_15_DEFAULT 0x0000000f 2357 #define smnREMAP_HDP_MEM_FLUSH_CNTL_DEFAULT 0x0000385c 2358 #define smnREMAP_HDP_REG_FLUSH_CNTL_DEFAULT 0x00003858 2359 #define smnBIF_RB_CNTL_DEFAULT 0x00000000 2360 #define smnBIF_RB_BASE_DEFAULT 0x00000000 2361 #define smnBIF_RB_RPTR_DEFAULT 0x00000000 2362 #define smnBIF_RB_WPTR_DEFAULT 0x00000000 2363 #define smnBIF_RB_WPTR_ADDR_HI_DEFAULT 0x00000000 2364 #define smnBIF_RB_WPTR_ADDR_LO_DEFAULT 0x00000000 2365 #define smnMAILBOX_INDEX_DEFAULT 0x00000000 2366 #define smnBIF_MP1_INTR_CTRL_DEFAULT 0x00000000 2367 #define smnBIF_UVD_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 2368 #define smnBIF_VCE_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 2369 #define smnBIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 2370 #define smnBIF_PERSTB_PAD_CNTL_DEFAULT 0x000000c0 2371 #define smnBIF_PX_EN_PAD_CNTL_DEFAULT 0x00000031 2372 #define smnBIF_REFPADKIN_PAD_CNTL_DEFAULT 0x00000007 2373 #define smnBIF_CLKREQB_PAD_CNTL_DEFAULT 0x00600100 2374 #define smnBIF_PWRBRK_PAD_CNTL_DEFAULT 0x00000071 2375 #define smnBIF_WAKEB_PAD_CNTL_DEFAULT 0x00000031 2376 #define smnBIF_VAUX_PRESENT_PAD_CNTL_DEFAULT 0x0000000d 2377 2378 2379 // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 2380 #define smnBIF_BME_STATUS_DEFAULT 0x00000000 2381 #define smnBIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 2382 #define smnDOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 2383 #define smnDOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 2384 #define smnDOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 2385 #define smnHDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 2386 #define smnHDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 2387 #define smnGPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 2388 #define smnGPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 2389 #define smnBIF_TRANS_PENDING_DEFAULT 0x00000000 2390 #define smnNBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 2391 #define smnMAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 2392 #define smnMAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 2393 #define smnMAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 2394 #define smnMAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 2395 #define smnMAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 2396 #define smnMAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 2397 #define smnMAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 2398 #define smnMAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 2399 #define smnMAILBOX_CONTROL_DEFAULT 0x00000000 2400 #define smnMAILBOX_INT_CNTL_DEFAULT 0x00000000 2401 #define smnBIF_VMHV_MAILBOX_DEFAULT 0x00000000 2402 2403 2404 // addressBlock: nbio_nbif0_rcc_shadow_reg_shadowdec 2405 #define smnSHADOW_COMMAND_DEFAULT 0x00000000 2406 #define smnSHADOW_BASE_ADDR_1_DEFAULT 0x00000000 2407 #define smnSHADOW_BASE_ADDR_2_DEFAULT 0x00000000 2408 #define smnSHADOW_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 2409 #define smnSHADOW_IO_BASE_LIMIT_DEFAULT 0x00000000 2410 #define smnSHADOW_MEM_BASE_LIMIT_DEFAULT 0x00000000 2411 #define smnSHADOW_PREF_BASE_LIMIT_DEFAULT 0x00000000 2412 #define smnSHADOW_PREF_BASE_UPPER_DEFAULT 0x00000000 2413 #define smnSHADOW_PREF_LIMIT_UPPER_DEFAULT 0x00000000 2414 #define smnSHADOW_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 2415 #define smnSHADOW_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 2416 #define smnSUC_INDEX_DEFAULT 0x00000000 2417 #define smnSUC_DATA_DEFAULT 0x00000000 2418 2419 2420 // addressBlock: nbio_nbif0_rcc_strap_rcc_strap_internal 2421 #define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP0_DEFAULT 0x54228f20 2422 #define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP1_DEFAULT 0x10221479 2423 #define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP2_DEFAULT 0x1c6fe009 2424 #define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849 2425 #define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000 2426 #define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000 2427 #define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP6_DEFAULT 0x0000ff02 2428 #define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000 2429 #define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP8_DEFAULT 0x00000000 2430 #define smnRCC_STRAP1_RCC_DEV0_PORT_STRAP9_DEFAULT 0x00000000 2431 #define smnRCC_DEV1_PORT_STRAP0_DEFAULT 0x00000000 2432 #define smnRCC_DEV1_PORT_STRAP1_DEFAULT 0x00000000 2433 #define smnRCC_DEV1_PORT_STRAP2_DEFAULT 0x00000000 2434 #define smnRCC_DEV1_PORT_STRAP3_DEFAULT 0x00000000 2435 #define smnRCC_DEV1_PORT_STRAP4_DEFAULT 0x00000000 2436 #define smnRCC_DEV1_PORT_STRAP5_DEFAULT 0x00000000 2437 #define smnRCC_DEV1_PORT_STRAP6_DEFAULT 0x00000000 2438 #define smnRCC_DEV1_PORT_STRAP7_DEFAULT 0x00000000 2439 #define smnRCC_DEV1_PORT_STRAP8_DEFAULT 0x00000000 2440 #define smnRCC_DEV1_PORT_STRAP9_DEFAULT 0x00000000 2441 #define smnRCC_DEV2_PORT_STRAP0_DEFAULT 0x00000000 2442 #define smnRCC_DEV2_PORT_STRAP1_DEFAULT 0x00000000 2443 #define smnRCC_DEV2_PORT_STRAP2_DEFAULT 0x00000000 2444 #define smnRCC_DEV2_PORT_STRAP3_DEFAULT 0x00000000 2445 #define smnRCC_DEV2_PORT_STRAP4_DEFAULT 0x00000000 2446 #define smnRCC_DEV2_PORT_STRAP5_DEFAULT 0x00000000 2447 #define smnRCC_DEV2_PORT_STRAP6_DEFAULT 0x00000000 2448 #define smnRCC_DEV2_PORT_STRAP7_DEFAULT 0x00000000 2449 #define smnRCC_DEV2_PORT_STRAP8_DEFAULT 0x00000000 2450 #define smnRCC_DEV2_PORT_STRAP9_DEFAULT 0x00000000 2451 #define smnRCC_STRAP1_RCC_BIF_STRAP0_DEFAULT 0x00040a00 2452 #define smnRCC_STRAP1_RCC_BIF_STRAP1_DEFAULT 0x00400108 2453 #define smnRCC_STRAP1_RCC_BIF_STRAP2_DEFAULT 0x000a0079 2454 #define smnRCC_STRAP1_RCC_BIF_STRAP3_DEFAULT 0x00000000 2455 #define smnRCC_STRAP1_RCC_BIF_STRAP4_DEFAULT 0x00100010 2456 #define smnRCC_STRAP1_RCC_BIF_STRAP5_DEFAULT 0x31130010 2457 #define smnRCC_STRAP1_RCC_BIF_STRAP6_DEFAULT 0x00000000 2458 #define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_DEFAULT 0x30007310 2459 #define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000 2460 #define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP2_DEFAULT 0x02002000 2461 #define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b5cc41 2462 #define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP4_DEFAULT 0x1f000000 2463 #define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP5_DEFAULT 0x00001002 2464 #define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP8_DEFAULT 0xcb026001 2465 #define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP9_DEFAULT 0x00000100 2466 #define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000 2467 #define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP0_DEFAULT 0x3000ab38 2468 #define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP2_DEFAULT 0x00002000 2469 #define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP3_DEFAULT 0x0806ace1 2470 #define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP4_DEFAULT 0x2f000000 2471 #define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP5_DEFAULT 0x00001002 2472 #define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP6_DEFAULT 0x00000000 2473 #define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP7_DEFAULT 0x00000000 2474 #define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP10_DEFAULT 0x00000000 2475 #define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP11_DEFAULT 0x00000000 2476 #define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP12_DEFAULT 0x00000000 2477 #define smnRCC_STRAP1_RCC_DEV0_EPF1_STRAP13_DEFAULT 0x00000000 2478 #define smnRCC_DEV0_EPF2_STRAP0_DEFAULT 0x10007316 2479 #define smnRCC_DEV0_EPF2_STRAP2_DEFAULT 0x03002000 2480 #define smnRCC_DEV0_EPF2_STRAP3_DEFAULT 0x0815cc59 2481 #define smnRCC_DEV0_EPF2_STRAP4_DEFAULT 0x3c800000 2482 #define smnRCC_DEV0_EPF2_STRAP5_DEFAULT 0x00001002 2483 #define smnRCC_DEV0_EPF2_STRAP6_DEFAULT 0x00000001 2484 #define smnRCC_DEV0_EPF2_STRAP7_DEFAULT 0x00000000 2485 #define smnRCC_DEV0_EPF2_STRAP13_DEFAULT 0x000c0330 2486 #define smnRCC_DEV0_EPF3_STRAP0_DEFAULT 0x10007314 2487 #define smnRCC_DEV0_EPF3_STRAP2_DEFAULT 0x01002000 2488 #define smnRCC_DEV0_EPF3_STRAP3_DEFAULT 0x0805cc51 2489 #define smnRCC_DEV0_EPF3_STRAP4_DEFAULT 0x40000000 2490 #define smnRCC_DEV0_EPF3_STRAP5_DEFAULT 0x00001002 2491 #define smnRCC_DEV0_EPF3_STRAP6_DEFAULT 0x00000001 2492 #define smnRCC_DEV0_EPF3_STRAP7_DEFAULT 0x00000000 2493 #define smnRCC_DEV0_EPF3_STRAP13_DEFAULT 0x000c8000 2494 #define smnRCC_DEV0_EPF4_STRAP0_DEFAULT 0x00000000 2495 #define smnRCC_DEV0_EPF4_STRAP2_DEFAULT 0x00000000 2496 #define smnRCC_DEV0_EPF4_STRAP3_DEFAULT 0x00000000 2497 #define smnRCC_DEV0_EPF4_STRAP4_DEFAULT 0x00000000 2498 #define smnRCC_DEV0_EPF4_STRAP5_DEFAULT 0x00000000 2499 #define smnRCC_DEV0_EPF4_STRAP6_DEFAULT 0x00000000 2500 #define smnRCC_DEV0_EPF4_STRAP7_DEFAULT 0x00000000 2501 #define smnRCC_DEV0_EPF4_STRAP13_DEFAULT 0x00000000 2502 #define smnRCC_DEV0_EPF5_STRAP0_DEFAULT 0x00000000 2503 #define smnRCC_DEV0_EPF5_STRAP2_DEFAULT 0x00000000 2504 #define smnRCC_DEV0_EPF5_STRAP3_DEFAULT 0x00000000 2505 #define smnRCC_DEV0_EPF5_STRAP4_DEFAULT 0x00000000 2506 #define smnRCC_DEV0_EPF5_STRAP5_DEFAULT 0x00000000 2507 #define smnRCC_DEV0_EPF5_STRAP6_DEFAULT 0x00000000 2508 #define smnRCC_DEV0_EPF5_STRAP7_DEFAULT 0x00000000 2509 #define smnRCC_DEV0_EPF5_STRAP13_DEFAULT 0x00000000 2510 #define smnRCC_DEV0_EPF6_STRAP0_DEFAULT 0x00000000 2511 #define smnRCC_DEV0_EPF6_STRAP2_DEFAULT 0x00000000 2512 #define smnRCC_DEV0_EPF6_STRAP3_DEFAULT 0x00000000 2513 #define smnRCC_DEV0_EPF6_STRAP4_DEFAULT 0x00000000 2514 #define smnRCC_DEV0_EPF6_STRAP5_DEFAULT 0x00000000 2515 #define smnRCC_DEV0_EPF6_STRAP6_DEFAULT 0x00000000 2516 #define smnRCC_DEV0_EPF6_STRAP13_DEFAULT 0x00000000 2517 #define smnRCC_DEV1_EPF0_STRAP0_DEFAULT 0x00000000 2518 #define smnRCC_DEV1_EPF0_STRAP2_DEFAULT 0x00000000 2519 #define smnRCC_DEV1_EPF0_STRAP3_DEFAULT 0x00000000 2520 #define smnRCC_DEV1_EPF0_STRAP4_DEFAULT 0x00000000 2521 #define smnRCC_DEV1_EPF0_STRAP5_DEFAULT 0x00000000 2522 #define smnRCC_DEV1_EPF0_STRAP6_DEFAULT 0x00000000 2523 #define smnRCC_DEV1_EPF0_STRAP7_DEFAULT 0x00000000 2524 #define smnRCC_DEV1_EPF0_STRAP13_DEFAULT 0x00000000 2525 #define smnRCC_DEV2_EPF0_STRAP0_DEFAULT 0x00000000 2526 #define smnRCC_DEV2_EPF0_STRAP2_DEFAULT 0x00000000 2527 #define smnRCC_DEV2_EPF0_STRAP3_DEFAULT 0x00000000 2528 #define smnRCC_DEV2_EPF0_STRAP4_DEFAULT 0x00000000 2529 #define smnRCC_DEV2_EPF0_STRAP5_DEFAULT 0x00000000 2530 #define smnRCC_DEV2_EPF0_STRAP6_DEFAULT 0x00000000 2531 #define smnRCC_DEV2_EPF0_STRAP7_DEFAULT 0x00000000 2532 #define smnRCC_DEV2_EPF0_STRAP13_DEFAULT 0x00000000 2533 2534 2535 // addressBlock: nbio_nbif0_rcc_dev0_RCCPORTDEC 2536 #define smnRCC_DEV0_1_RCC_VDM_SUPPORT_DEFAULT 0x00000000 2537 #define smnRCC_DEV0_1_RCC_BUS_CNTL_DEFAULT 0x00000000 2538 #define smnRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC_DEFAULT 0x00000000 2539 #define smnRCC_DEV0_1_RCC_DEV0_LINK_CNTL_DEFAULT 0x00000000 2540 #define smnRCC_DEV0_1_RCC_CMN_LINK_CNTL_DEFAULT 0x00400000 2541 #define smnRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE_DEFAULT 0x00000000 2542 #define smnRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL_DEFAULT 0x00000000 2543 #define smnRCC_DEV0_1_RCC_MH_ARB_CNTL_DEFAULT 0x00000000 2544 #define smnRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0_DEFAULT 0x0a80a0df 2545 #define smnRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1_DEFAULT 0x0000f000 2546 2547 2548 // addressBlock: nbio_nbif0_rcc_ep_dev0_RCCPORTDEC 2549 #define smnRCC_EP_DEV0_1_EP_PCIE_SCRATCH_DEFAULT 0x00000000 2550 #define smnRCC_EP_DEV0_1_EP_PCIE_CNTL_DEFAULT 0x00000000 2551 #define smnRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_DEFAULT 0x00000000 2552 #define smnRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_DEFAULT 0x00000000 2553 #define smnRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_DEFAULT 0x00000000 2554 #define smnRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_DEFAULT 0x00000080 2555 #define smnRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_DEFAULT 0x00000000 2556 #define smnRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_DEFAULT 0x00007468 2557 #define smnRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC_DEFAULT 0x00000000 2558 #define smnRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2_DEFAULT 0x00000000 2559 #define smnRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000 2560 #define smnRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0 2561 #define smnRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100 2562 #define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa 2563 #define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 2564 #define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 2565 #define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 2566 #define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b 2567 #define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 2568 #define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 2569 #define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a 2570 #define smnRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_DEFAULT 0x00000000 2571 #define smnRCC_EP_DEV0_1_EP_PCIEP_RESERVED_DEFAULT 0x00000000 2572 #define smnRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_DEFAULT 0x00000000 2573 #define smnRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 2574 #define smnRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_DEFAULT 0x00000500 2575 #define smnRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_DEFAULT 0x01000000 2576 #define smnRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 2577 2578 2579 // addressBlock: nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC 2580 #define smnRCC_DWN_DEV0_1_DN_PCIE_RESERVED_DEFAULT 0x00000000 2581 #define smnRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_DEFAULT 0x00000000 2582 #define smnRCC_DWN_DEV0_1_DN_PCIE_CNTL_DEFAULT 0x00000000 2583 #define smnRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000 2584 #define smnRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_DEFAULT 0x00000000 2585 #define smnRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_DEFAULT 0x00000080 2586 #define smnRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_DEFAULT 0x00000000 2587 #define smnRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0_DEFAULT 0x00000001 2588 #define smnRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC_DEFAULT 0x00000000 2589 #define smnRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2_DEFAULT 0x00000000 2590 2591 2592 // addressBlock: nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC 2593 #define smnRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_DEFAULT 0x00000500 2594 #define smnRCC_DWNP_DEV0_1_PCIE_RX_CNTL_DEFAULT 0x00000000 2595 #define smnRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 2596 #define smnRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_DEFAULT 0x00000000 2597 #define smnRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_DEFAULT 0x00000000 2598 #define smnRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000 2599 2600 2601 // addressBlock: nbio_nbif0_bif_misc_bif_misc_regblk 2602 #define smnMISC_SCRATCH_DEFAULT 0x00000000 2603 #define smnINTR_LINE_POLARITY_DEFAULT 0x00000000 2604 #define smnINTR_LINE_ENABLE_DEFAULT 0x000000ff 2605 #define smnOUTSTANDING_VC_ALLOC_DEFAULT 0x6f06c0cf 2606 #define smnBIFC_MISC_CTRL0_DEFAULT 0x08000024 2607 #define smnBIFC_MISC_CTRL1_DEFAULT 0x90108c04 2608 #define smnBIFC_BME_ERR_LOG_DEFAULT 0x00000000 2609 #define smnBIFC_RCCBIH_BME_ERR_LOG0_DEFAULT 0x00000000 2610 #define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_DEFAULT 0x80108010 2611 #define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_DEFAULT 0x80108010 2612 #define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_DEFAULT 0x80108010 2613 #define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_DEFAULT 0x80108010 2614 #define smnBIFC_DMA_ATTR_CNTL2_DEV0_DEFAULT 0x00000000 2615 #define smnBME_DUMMY_CNTL_0_DEFAULT 0x0000aaaa 2616 #define smnBIFC_THT_CNTL_DEFAULT 0x00000111 2617 #define smnBIFC_HSTARB_CNTL_DEFAULT 0x00000000 2618 #define smnBIFC_GSI_CNTL_DEFAULT 0x000057c0 2619 #define smnBIFC_PCIEFUNC_CNTL_DEFAULT 0x00000000 2620 #define smnBIFC_PASID_CHECK_DIS_DEFAULT 0x00000001 2621 #define smnBIFC_SDP_CNTL_0_DEFAULT 0x3f3f3f3f 2622 #define smnBIFC_SDP_CNTL_1_DEFAULT 0x00000000 2623 #define smnBIFC_PASID_STS_DEFAULT 0x00000002 2624 #define smnBIFC_ATHUB_ACT_CNTL_DEFAULT 0x00000004 2625 #define smnBIFC_PERF_CNTL_0_DEFAULT 0x00000000 2626 #define smnBIFC_PERF_CNTL_1_DEFAULT 0x00000000 2627 #define smnBIFC_PERF_CNT_MMIO_RD_DEFAULT 0x00000000 2628 #define smnBIFC_PERF_CNT_MMIO_WR_DEFAULT 0x00000000 2629 #define smnBIFC_PERF_CNT_DMA_RD_DEFAULT 0x00000000 2630 #define smnBIFC_PERF_CNT_DMA_WR_DEFAULT 0x00000000 2631 #define smnNBIF_REGIF_ERRSET_CTRL_DEFAULT 0x00000000 2632 #define smnNBIF_PGMST_CTRL_DEFAULT 0x00000000 2633 #define smnNBIF_PGSLV_CTRL_DEFAULT 0x00000004 2634 #define smnNBIF_PG_MISC_CTRL_DEFAULT 0x14006084 2635 #define smnSMN_MST_EP_CNTL3_DEFAULT 0x00000000 2636 #define smnSMN_MST_EP_CNTL4_DEFAULT 0x00000000 2637 #define smnSMN_MST_CNTL1_DEFAULT 0x00000000 2638 #define smnSMN_MST_EP_CNTL5_DEFAULT 0x00000000 2639 #define smnBIF_SELFRING_BUFFER_VID_DEFAULT 0x0061605f 2640 #define smnBIF_SELFRING_VECTOR_CNTL_DEFAULT 0x00000000 2641 #define smnNBIF_STRAP_WRITE_CTRL_DEFAULT 0x00000000 2642 #define smnNBIF_INTX_DSTATE_MISC_CNTL_DEFAULT 0x00000000 2643 #define smnNBIF_PENDING_MISC_CNTL_DEFAULT 0x00000000 2644 #define smnBIF_GMI_WRR_WEIGHT_DEFAULT 0x00000000 2645 #define smnBIF_GMI_WRR_WEIGHT2_DEFAULT 0x04040404 2646 #define smnBIF_GMI_WRR_WEIGHT3_DEFAULT 0x04040404 2647 #define smnNBIF_PWRBRK_REQUEST_DEFAULT 0x00000000 2648 #define smnBIF_ATOMIC_ERR_LOG_DEV0_F0_DEFAULT 0x00000000 2649 #define smnBIF_ATOMIC_ERR_LOG_DEV0_F1_DEFAULT 0x00000000 2650 #define smnBIF_ATOMIC_ERR_LOG_DEV0_F2_DEFAULT 0x00000000 2651 #define smnBIF_ATOMIC_ERR_LOG_DEV0_F3_DEFAULT 0x00000000 2652 #define smnBIF_ATOMIC_ERR_LOG_DEV0_F4_DEFAULT 0x00000000 2653 #define smnBIF_ATOMIC_ERR_LOG_DEV0_F5_DEFAULT 0x00000000 2654 #define smnBIF_ATOMIC_ERR_LOG_DEV0_F6_DEFAULT 0x00000000 2655 #define smnBIF_ATOMIC_ERR_LOG_DEV0_F7_DEFAULT 0x00000000 2656 #define smnBIF_DMA_MP4_ERR_LOG_DEFAULT 0x00000000 2657 #define smnBIF_PASID_ERR_LOG_DEFAULT 0x00000000 2658 #define smnBIF_PASID_ERR_CLR_DEFAULT 0x00000000 2659 #define smnNBIF_VWIRE_CTRL_DEFAULT 0x00000000 2660 #define smnNBIF_SMN_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000 2661 #define smnNBIF_SMN_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000 2662 #define smnNBIF_SMN_VWR_VCHG_TRIG_DEFAULT 0x00000000 2663 #define smnNBIF_SMN_VWR_WTRIG_CNTL_DEFAULT 0x00000000 2664 #define smnNBIF_SMN_VWR_VCHG_DIS_CTRL_1_DEFAULT 0x00000000 2665 #define smnNBIF_MGCG_CTRL_LCLK_DEFAULT 0x00000100 2666 #define smnNBIF_DS_CTRL_LCLK_DEFAULT 0x01000000 2667 #define smnSMN_MST_CNTL0_DEFAULT 0x00000001 2668 #define smnSMN_MST_EP_CNTL1_DEFAULT 0x00000000 2669 #define smnSMN_MST_EP_CNTL2_DEFAULT 0x00000000 2670 #define smnNBIF_SDP_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000 2671 #define smnNBIF_SDP_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000 2672 #define smnNBIF_SDP_VWR_VCHG_RST_CTRL1_DEFAULT 0x00000000 2673 #define smnNBIF_SDP_VWR_VCHG_TRIG_DEFAULT 0x00000000 2674 #define smnBIFC_A2S_SDP_PORT_CTRL_DEFAULT 0x0000003f 2675 #define smnBIFC_A2S_CNTL_SW0_DEFAULT 0x04040000 2676 #define smnBIFC_A2S_MISC_CNTL_DEFAULT 0x0000000b 2677 #define smnBIFC_A2S_TAG_ALLOC_0_DEFAULT 0x00000000 2678 #define smnBIFC_A2S_TAG_ALLOC_1_DEFAULT 0x00000000 2679 #define smnBIFC_A2S_CNTL_CL0_DEFAULT 0x00282540 2680 #define smnBIFC_A2S_CPLBUF_ALLOC_CNTL_DEFAULT 0x11100001 2681 2682 2683 // addressBlock: nbio_nbif0_rcc_pfc_amdgfx_RCCPFCDEC 2684 #define smnRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 2685 #define smnRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 2686 #define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 2687 #define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 2688 #define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 2689 #define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 2690 #define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 2691 #define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 2692 #define smnRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 2693 2694 2695 // addressBlock: nbio_nbif0_rcc_pfc_amdgfxaz_RCCPFCDEC 2696 #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 2697 #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 2698 #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 2699 #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 2700 #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 2701 #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 2702 #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 2703 #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 2704 #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 2705 2706 2707 // addressBlock: nbio_nbif0_rcc_pfc_usb_RCCPFCDEC 2708 #define smnRCC_PFC_USB_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 2709 #define smnRCC_PFC_USB_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 2710 #define smnRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 2711 #define smnRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 2712 #define smnRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 2713 #define smnRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 2714 #define smnRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 2715 #define smnRCC_PFC_USB_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 2716 #define smnRCC_PFC_USB_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 2717 2718 2719 // addressBlock: nbio_nbif0_rcc_pfc_pd_controller_RCCPFCDEC 2720 #define smnRCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 2721 #define smnRCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 2722 #define smnRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 2723 #define smnRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 2724 #define smnRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 2725 #define smnRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 2726 #define smnRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 2727 #define smnRCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 2728 #define smnRCC_PFC_PD_CONTROLLER_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 2729 2730 2731 // addressBlock: nbio_nbif0_bif_rst_bif_rst_regblk 2732 #define smnHARD_RST_CTRL_DEFAULT 0xb0000055 2733 #define smnSELF_SOFT_RST_DEFAULT 0x00000000 2734 #define smnBIF_GFX_DRV_VPU_RST_DEFAULT 0x00000000 2735 #define smnBIF_RST_MISC_CTRL_DEFAULT 0x000e0648 2736 #define smnBIF_RST_MISC_CTRL2_DEFAULT 0x80070000 2737 #define smnBIF_RST_MISC_CTRL3_DEFAULT 0x00104900 2738 #define smnBIF_RST_GFXVF_FLR_IDLE_DEFAULT 0x00000000 2739 #define smnDEV0_PF0_FLR_RST_CTRL_DEFAULT 0x8206a0a9 2740 #define smnDEV0_PF1_FLR_RST_CTRL_DEFAULT 0x02060009 2741 #define smnDEV0_PF2_FLR_RST_CTRL_DEFAULT 0x02060009 2742 #define smnDEV0_PF3_FLR_RST_CTRL_DEFAULT 0x02060009 2743 #define smnDEV0_PF4_FLR_RST_CTRL_DEFAULT 0x02060009 2744 #define smnDEV0_PF5_FLR_RST_CTRL_DEFAULT 0x02060009 2745 #define smnDEV0_PF6_FLR_RST_CTRL_DEFAULT 0x02060009 2746 #define smnDEV0_PF7_FLR_RST_CTRL_DEFAULT 0x02060009 2747 #define smnBIF_INST_RESET_INTR_STS_DEFAULT 0x00000000 2748 #define smnBIF_PF_FLR_INTR_STS_DEFAULT 0x00000000 2749 #define smnBIF_D3HOTD0_INTR_STS_DEFAULT 0x00000000 2750 #define smnBIF_POWER_INTR_STS_DEFAULT 0x00000000 2751 #define smnBIF_PF_DSTATE_INTR_STS_DEFAULT 0x00000000 2752 #define smnSELF_SOFT_RST_2_DEFAULT 0x00000000 2753 #define smnBIF_PF0_VF_FLR_INTR_STS_DEFAULT 0x00000000 2754 #define smnBIF_INST_RESET_INTR_MASK_DEFAULT 0x00000000 2755 #define smnBIF_PF_FLR_INTR_MASK_DEFAULT 0x00000000 2756 #define smnBIF_D3HOTD0_INTR_MASK_DEFAULT 0x000000ff 2757 #define smnBIF_POWER_INTR_MASK_DEFAULT 0x00000000 2758 #define smnBIF_PF_DSTATE_INTR_MASK_DEFAULT 0x00000000 2759 #define smnBIF_PF0_VF_FLR_INTR_MASK_DEFAULT 0x00000000 2760 #define smnBIF_PF_FLR_RST_DEFAULT 0x00000000 2761 #define smnBIF_PF0_VF_FLR_RST_DEFAULT 0x00000000 2762 #define smnBIF_DEV0_PF0_DSTATE_VALUE_DEFAULT 0x00000000 2763 #define smnBIF_DEV0_PF1_DSTATE_VALUE_DEFAULT 0x00000000 2764 #define smnBIF_DEV0_PF2_DSTATE_VALUE_DEFAULT 0x00000000 2765 #define smnBIF_DEV0_PF3_DSTATE_VALUE_DEFAULT 0x00000000 2766 #define smnBIF_DEV0_PF4_DSTATE_VALUE_DEFAULT 0x00000000 2767 #define smnBIF_DEV0_PF5_DSTATE_VALUE_DEFAULT 0x00000000 2768 #define smnBIF_DEV0_PF6_DSTATE_VALUE_DEFAULT 0x00000000 2769 #define smnBIF_DEV0_PF7_DSTATE_VALUE_DEFAULT 0x00000000 2770 #define smnDEV0_PF0_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b 2771 #define smnDEV0_PF1_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b 2772 #define smnDEV0_PF2_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b 2773 #define smnDEV0_PF3_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b 2774 #define smnDEV0_PF4_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b 2775 #define smnDEV0_PF5_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b 2776 #define smnDEV0_PF6_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b 2777 #define smnDEV0_PF7_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b 2778 #define smnBIF_PORT0_DSTATE_VALUE_DEFAULT 0x00000000 2779 #define smnBIF_USB_SHUB_RS_RESET_CNTL_DEFAULT 0x00000000 2780 2781 2782 // addressBlock: nbio_nbif0_bif_ras_bif_ras_regblk 2783 #define smnBIFL_RAS_CENTRAL_CNTL_DEFAULT 0x00000000 2784 #define smnBIFL_RAS_CENTRAL_STATUS_DEFAULT 0x00000000 2785 #define smnBIFL_RAS_LEAF0_CTRL_DEFAULT 0x00000f61 2786 #define smnBIFL_RAS_LEAF1_CTRL_DEFAULT 0x00000f61 2787 #define smnBIFL_RAS_LEAF2_CTRL_DEFAULT 0x00000f61 2788 #define smnBIFL_RAS_LEAF3_CTRL_DEFAULT 0x00000f61 2789 #define smnBIFL_RAS_LEAF4_CTRL_DEFAULT 0x00000f61 2790 #define smnBIFL_RAS_LEAF0_STATUS_DEFAULT 0x00000000 2791 #define smnBIFL_RAS_LEAF1_STATUS_DEFAULT 0x00000000 2792 #define smnBIFL_RAS_LEAF2_STATUS_DEFAULT 0x00000000 2793 #define smnBIFL_RAS_LEAF3_STATUS_DEFAULT 0x00000000 2794 #define smnBIFL_RAS_LEAF4_STATUS_DEFAULT 0x00000000 2795 #define smnBIFL_IOHUB_RAS_IH_CNTL_DEFAULT 0x00000000 2796 #define smnBIFL_RAS_VWR_FROM_IOHUB_DEFAULT 0x00000000 2797 2798 2799 // addressBlock: nbio_nbif0_bif_swus_SUMDEC 2800 #define smnSUM_INDEX_DEFAULT 0x00000000 2801 #define smnSUM_DATA_DEFAULT 0x00000000 2802 2803 2804 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp 2805 #define smnBIF_CFG_DEV0_EPF0_VENDOR_ID_DEFAULT 0x00001002 2806 #define smnBIF_CFG_DEV0_EPF0_DEVICE_ID_DEFAULT 0x00007310 2807 #define smnBIF_CFG_DEV0_EPF0_COMMAND_DEFAULT 0x00000000 2808 #define smnBIF_CFG_DEV0_EPF0_STATUS_DEFAULT 0x00000000 2809 #define smnBIF_CFG_DEV0_EPF0_REVISION_ID_DEFAULT 0x00000000 2810 #define smnBIF_CFG_DEV0_EPF0_PROG_INTERFACE_DEFAULT 0x00000000 2811 #define smnBIF_CFG_DEV0_EPF0_SUB_CLASS_DEFAULT 0x00000000 2812 #define smnBIF_CFG_DEV0_EPF0_BASE_CLASS_DEFAULT 0x00000000 2813 #define smnBIF_CFG_DEV0_EPF0_CACHE_LINE_DEFAULT 0x00000000 2814 #define smnBIF_CFG_DEV0_EPF0_LATENCY_DEFAULT 0x00000000 2815 #define smnBIF_CFG_DEV0_EPF0_HEADER_DEFAULT 0x00000080 2816 #define smnBIF_CFG_DEV0_EPF0_BIST_DEFAULT 0x00000000 2817 #define smnBIF_CFG_DEV0_EPF0_BASE_ADDR_1_DEFAULT 0x00000000 2818 #define smnBIF_CFG_DEV0_EPF0_BASE_ADDR_2_DEFAULT 0x00000000 2819 #define smnBIF_CFG_DEV0_EPF0_BASE_ADDR_3_DEFAULT 0x00000000 2820 #define smnBIF_CFG_DEV0_EPF0_BASE_ADDR_4_DEFAULT 0x00000000 2821 #define smnBIF_CFG_DEV0_EPF0_BASE_ADDR_5_DEFAULT 0x00000000 2822 #define smnBIF_CFG_DEV0_EPF0_BASE_ADDR_6_DEFAULT 0x00000000 2823 #define smnBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 2824 #define smnBIF_CFG_DEV0_EPF0_ADAPTER_ID_DEFAULT 0x73101002 2825 #define smnBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR_DEFAULT 0x00000000 2826 #define smnBIF_CFG_DEV0_EPF0_CAP_PTR_DEFAULT 0x00000048 2827 #define smnBIF_CFG_DEV0_EPF0_INTERRUPT_LINE_DEFAULT 0x000000ff 2828 #define smnBIF_CFG_DEV0_EPF0_INTERRUPT_PIN_DEFAULT 0x00000001 2829 #define smnBIF_CFG_DEV0_EPF0_MIN_GRANT_DEFAULT 0x00000000 2830 #define smnBIF_CFG_DEV0_EPF0_MAX_LATENCY_DEFAULT 0x00000000 2831 #define smnBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST_DEFAULT 0x00000000 2832 #define smnBIF_CFG_DEV0_EPF0_ADAPTER_ID_W_DEFAULT 0x73101002 2833 #define smnBIF_CFG_DEV0_EPF0_PMI_CAP_LIST_DEFAULT 0x00006400 2834 #define smnBIF_CFG_DEV0_EPF0_PMI_CAP_DEFAULT 0x0000f000 2835 #define smnBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL_DEFAULT 0x00000000 2836 #define smnBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST_DEFAULT 0x0000a000 2837 #define smnBIF_CFG_DEV0_EPF0_PCIE_CAP_DEFAULT 0x00000012 2838 #define smnBIF_CFG_DEV0_EPF0_DEVICE_CAP_DEFAULT 0x00000f81 2839 #define smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL_DEFAULT 0x00002810 2840 #define smnBIF_CFG_DEV0_EPF0_DEVICE_STATUS_DEFAULT 0x00000000 2841 #define smnBIF_CFG_DEV0_EPF0_LINK_CAP_DEFAULT 0x00000d04 2842 #define smnBIF_CFG_DEV0_EPF0_LINK_CNTL_DEFAULT 0x00000000 2843 #define smnBIF_CFG_DEV0_EPF0_LINK_STATUS_DEFAULT 0x00000001 2844 #define smnBIF_CFG_DEV0_EPF0_DEVICE_CAP2_DEFAULT 0x00010000 2845 #define smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2_DEFAULT 0x00000000 2846 #define smnBIF_CFG_DEV0_EPF0_DEVICE_STATUS2_DEFAULT 0x00000000 2847 #define smnBIF_CFG_DEV0_EPF0_LINK_CAP2_DEFAULT 0x0000001e 2848 #define smnBIF_CFG_DEV0_EPF0_LINK_CNTL2_DEFAULT 0x00000004 2849 #define smnBIF_CFG_DEV0_EPF0_LINK_STATUS2_DEFAULT 0x00000001 2850 #define smnBIF_CFG_DEV0_EPF0_MSI_CAP_LIST_DEFAULT 0x0000c000 2851 #define smnBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL_DEFAULT 0x00000084 2852 #define smnBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 2853 #define smnBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 2854 #define smnBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_DEFAULT 0x00000000 2855 #define smnBIF_CFG_DEV0_EPF0_MSI_MASK_DEFAULT 0x00000000 2856 #define smnBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64_DEFAULT 0x00000000 2857 #define smnBIF_CFG_DEV0_EPF0_MSI_MASK_64_DEFAULT 0x00000000 2858 #define smnBIF_CFG_DEV0_EPF0_MSI_PENDING_DEFAULT 0x00000000 2859 #define smnBIF_CFG_DEV0_EPF0_MSI_PENDING_64_DEFAULT 0x00000000 2860 #define smnBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST_DEFAULT 0x00000000 2861 #define smnBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL_DEFAULT 0x00000000 2862 #define smnBIF_CFG_DEV0_EPF0_MSIX_TABLE_DEFAULT 0x00000000 2863 #define smnBIF_CFG_DEV0_EPF0_MSIX_PBA_DEFAULT 0x00000000 2864 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 2865 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 2866 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 2867 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 2868 #define smnBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 2869 #define smnBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 2870 #define smnBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 2871 #define smnBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 2872 #define smnBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 2873 #define smnBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 2874 #define smnBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe 2875 #define smnBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 2876 #define smnBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 2877 #define smnBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 2878 #define smnBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 2879 #define smnBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 2880 #define smnBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 2881 #define smnBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 2882 #define smnBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 2883 #define smnBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 2884 #define smnBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 2885 #define smnBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 2886 #define smnBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 2887 #define smnBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 2888 #define smnBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 2889 #define smnBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0_DEFAULT 0x00000000 2890 #define smnBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1_DEFAULT 0x00000000 2891 #define smnBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2_DEFAULT 0x00000000 2892 #define smnBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3_DEFAULT 0x00000000 2893 #define smnBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 2894 #define smnBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 2895 #define smnBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 2896 #define smnBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 2897 #define smnBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 2898 #define smnBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP_DEFAULT 0x00000000 2899 #define smnBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL_DEFAULT 0x00000020 2900 #define smnBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP_DEFAULT 0x00000000 2901 #define smnBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL_DEFAULT 0x00000000 2902 #define smnBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP_DEFAULT 0x00000000 2903 #define smnBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL_DEFAULT 0x00000000 2904 #define smnBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP_DEFAULT 0x00000000 2905 #define smnBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL_DEFAULT 0x00000000 2906 #define smnBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP_DEFAULT 0x00000000 2907 #define smnBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL_DEFAULT 0x00000000 2908 #define smnBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP_DEFAULT 0x00000000 2909 #define smnBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL_DEFAULT 0x00000000 2910 #define smnBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 2911 #define smnBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 2912 #define smnBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 2913 #define smnBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 2914 #define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 2915 #define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP_DEFAULT 0x00000000 2916 #define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 2917 #define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS_DEFAULT 0x00000100 2918 #define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL_DEFAULT 0x00000000 2919 #define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 2920 #define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 2921 #define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 2922 #define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 2923 #define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 2924 #define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 2925 #define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 2926 #define smnBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 2927 #define smnBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 2928 #define smnBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 2929 #define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 2930 #define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 2931 #define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 2932 #define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 2933 #define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 2934 #define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 2935 #define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 2936 #define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 2937 #define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 2938 #define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 2939 #define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 2940 #define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 2941 #define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 2942 #define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 2943 #define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 2944 #define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 2945 #define smnBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 2946 #define smnBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 2947 #define smnBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP_DEFAULT 0x00000000 2948 #define smnBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL_DEFAULT 0x00000000 2949 #define smnBIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 2950 #define smnBIF_CFG_DEV0_EPF0_PCIE_ATS_CAP_DEFAULT 0x00000000 2951 #define smnBIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL_DEFAULT 0x00000000 2952 #define smnBIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000 2953 #define smnBIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 2954 #define smnBIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000100 2955 #define smnBIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000 2956 #define smnBIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 2957 #define smnBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000 2958 #define smnBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP_DEFAULT 0x00001000 2959 #define smnBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL_DEFAULT 0x00000000 2960 #define smnBIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 2961 #define smnBIF_CFG_DEV0_EPF0_PCIE_MC_CAP_DEFAULT 0x00000000 2962 #define smnBIF_CFG_DEV0_EPF0_PCIE_MC_CNTL_DEFAULT 0x00000000 2963 #define smnBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0_DEFAULT 0x00000000 2964 #define smnBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1_DEFAULT 0x00000000 2965 #define smnBIF_CFG_DEV0_EPF0_PCIE_MC_RCV0_DEFAULT 0x00000000 2966 #define smnBIF_CFG_DEV0_EPF0_PCIE_MC_RCV1_DEFAULT 0x00000000 2967 #define smnBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 2968 #define smnBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 2969 #define smnBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 2970 #define smnBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 2971 #define smnBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 2972 #define smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP_DEFAULT 0x00000000 2973 #define smnBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 2974 #define smnBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP_DEFAULT 0x00000000 2975 #define smnBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL_DEFAULT 0x00000000 2976 #define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x37000000 2977 #define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP_DEFAULT 0x00000000 2978 #define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000 2979 #define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS_DEFAULT 0x00000000 2980 #define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000 2981 #define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000 2982 #define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000 2983 #define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000 2984 #define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000 2985 #define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000 2986 #define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000 2987 #define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000553 2988 #define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001 2989 #define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000 2990 #define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000 2991 #define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000 2992 #define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000 2993 #define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000 2994 #define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000 2995 #define smnBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000 2996 #define smnBIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000 2997 #define smnBIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000 2998 #define smnBIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 2999 #define smnBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41010025 3000 #define smnBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP_DEFAULT 0x00000001 3001 #define smnBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000 3002 #define smnBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44010026 3003 #define smnBIF_CFG_DEV0_EPF0_LINK_CAP_16GT_DEFAULT 0x00000000 3004 #define smnBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT_DEFAULT 0x00000000 3005 #define smnBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT_DEFAULT 0x00000000 3006 #define smnBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 3007 #define smnBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 3008 #define smnBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 3009 #define smnBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3010 #define smnBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3011 #define smnBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3012 #define smnBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3013 #define smnBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3014 #define smnBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3015 #define smnBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3016 #define smnBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3017 #define smnBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3018 #define smnBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3019 #define smnBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3020 #define smnBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3021 #define smnBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3022 #define smnBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3023 #define smnBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3024 #define smnBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3025 #define smnBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x4c010027 3026 #define smnBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP_DEFAULT 0x00000000 3027 #define smnBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS_DEFAULT 0x00000000 3028 #define smnBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3029 #define smnBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3030 #define smnBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3031 #define smnBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3032 #define smnBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3033 #define smnBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3034 #define smnBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3035 #define smnBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3036 #define smnBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3037 #define smnBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3038 #define smnBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3039 #define smnBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3040 #define smnBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3041 #define smnBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3042 #define smnBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3043 #define smnBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3044 #define smnBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3045 #define smnBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3046 #define smnBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3047 #define smnBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3048 #define smnBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3049 #define smnBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3050 #define smnBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3051 #define smnBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3052 #define smnBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3053 #define smnBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3054 #define smnBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3055 #define smnBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3056 #define smnBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3057 #define smnBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3058 #define smnBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3059 #define smnBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3060 #define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_DEFAULT 0x00000000 3061 #define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP_DEFAULT 0x00000000 3062 #define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL_DEFAULT 0x00000020 3063 #define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP_DEFAULT 0x00000000 3064 #define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL_DEFAULT 0x00000000 3065 #define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP_DEFAULT 0x00000000 3066 #define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL_DEFAULT 0x00000000 3067 #define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP_DEFAULT 0x00000000 3068 #define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL_DEFAULT 0x00000000 3069 #define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP_DEFAULT 0x00000000 3070 #define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL_DEFAULT 0x00000000 3071 #define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP_DEFAULT 0x00000000 3072 #define smnBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL_DEFAULT 0x00000000 3073 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000 3074 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000 3075 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000 3076 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000 3077 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000 3078 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000 3079 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000 3080 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000 3081 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000 3082 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000 3083 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000 3084 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x0012000c 3085 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_DEFAULT 0x00000000 3086 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_DEFAULT 0x00000000 3087 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000 3088 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000 3089 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000 3090 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000 3091 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000 3092 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000 3093 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000 3094 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000 3095 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000 3096 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000 3097 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000 3098 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000 3099 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000 3100 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000 3101 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000 3102 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000 3103 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_DEFAULT 0x00000000 3104 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_DEFAULT 0x00000000 3105 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_DEFAULT 0x00000000 3106 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_DEFAULT 0x00000000 3107 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_DEFAULT 0x00000000 3108 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_DEFAULT 0x00000000 3109 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_DEFAULT 0x00000000 3110 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_DEFAULT 0x00000000 3111 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_DEFAULT 0x00000000 3112 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_DEFAULT 0x00000000 3113 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_DEFAULT 0x00000000 3114 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_DEFAULT 0x00000000 3115 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_DEFAULT 0x00000000 3116 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_DEFAULT 0x00000000 3117 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_DEFAULT 0x00000000 3118 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000 3119 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000 3120 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000 3121 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000 3122 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000 3123 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000 3124 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000 3125 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000 3126 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000 3127 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000 3128 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000 3129 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000 3130 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000 3131 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000 3132 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000 3133 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000 3134 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000 3135 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000 3136 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000 3137 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000 3138 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000 3139 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000 3140 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000 3141 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000 3142 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000 3143 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000 3144 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000 3145 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0_DEFAULT 0x00000000 3146 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1_DEFAULT 0x00000000 3147 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2_DEFAULT 0x00000000 3148 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3_DEFAULT 0x00000000 3149 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4_DEFAULT 0x00000000 3150 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5_DEFAULT 0x00000000 3151 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6_DEFAULT 0x00000000 3152 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7_DEFAULT 0x00000000 3153 #define smnBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8_DEFAULT 0x00000000 3154 3155 3156 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp 3157 #define smnBIF_CFG_DEV0_EPF1_VENDOR_ID_DEFAULT 0x00001002 3158 #define smnBIF_CFG_DEV0_EPF1_DEVICE_ID_DEFAULT 0x0000ab38 3159 #define smnBIF_CFG_DEV0_EPF1_COMMAND_DEFAULT 0x00000000 3160 #define smnBIF_CFG_DEV0_EPF1_STATUS_DEFAULT 0x00000000 3161 #define smnBIF_CFG_DEV0_EPF1_REVISION_ID_DEFAULT 0x00000000 3162 #define smnBIF_CFG_DEV0_EPF1_PROG_INTERFACE_DEFAULT 0x00000000 3163 #define smnBIF_CFG_DEV0_EPF1_SUB_CLASS_DEFAULT 0x00000000 3164 #define smnBIF_CFG_DEV0_EPF1_BASE_CLASS_DEFAULT 0x00000000 3165 #define smnBIF_CFG_DEV0_EPF1_CACHE_LINE_DEFAULT 0x00000000 3166 #define smnBIF_CFG_DEV0_EPF1_LATENCY_DEFAULT 0x00000000 3167 #define smnBIF_CFG_DEV0_EPF1_HEADER_DEFAULT 0x00000080 3168 #define smnBIF_CFG_DEV0_EPF1_BIST_DEFAULT 0x00000000 3169 #define smnBIF_CFG_DEV0_EPF1_BASE_ADDR_1_DEFAULT 0x00000000 3170 #define smnBIF_CFG_DEV0_EPF1_BASE_ADDR_2_DEFAULT 0x00000000 3171 #define smnBIF_CFG_DEV0_EPF1_BASE_ADDR_3_DEFAULT 0x00000000 3172 #define smnBIF_CFG_DEV0_EPF1_BASE_ADDR_4_DEFAULT 0x00000000 3173 #define smnBIF_CFG_DEV0_EPF1_BASE_ADDR_5_DEFAULT 0x00000000 3174 #define smnBIF_CFG_DEV0_EPF1_BASE_ADDR_6_DEFAULT 0x00000000 3175 #define smnBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 3176 #define smnBIF_CFG_DEV0_EPF1_ADAPTER_ID_DEFAULT 0xab381002 3177 #define smnBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR_DEFAULT 0x00000000 3178 #define smnBIF_CFG_DEV0_EPF1_CAP_PTR_DEFAULT 0x00000048 3179 #define smnBIF_CFG_DEV0_EPF1_INTERRUPT_LINE_DEFAULT 0x000000ff 3180 #define smnBIF_CFG_DEV0_EPF1_INTERRUPT_PIN_DEFAULT 0x00000002 3181 #define smnBIF_CFG_DEV0_EPF1_MIN_GRANT_DEFAULT 0x00000000 3182 #define smnBIF_CFG_DEV0_EPF1_MAX_LATENCY_DEFAULT 0x00000000 3183 #define smnBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST_DEFAULT 0x00000000 3184 #define smnBIF_CFG_DEV0_EPF1_ADAPTER_ID_W_DEFAULT 0xab381002 3185 #define smnBIF_CFG_DEV0_EPF1_PMI_CAP_LIST_DEFAULT 0x00006400 3186 #define smnBIF_CFG_DEV0_EPF1_PMI_CAP_DEFAULT 0x0000f000 3187 #define smnBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL_DEFAULT 0x00000000 3188 #define smnBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST_DEFAULT 0x0000a000 3189 #define smnBIF_CFG_DEV0_EPF1_PCIE_CAP_DEFAULT 0x00000012 3190 #define smnBIF_CFG_DEV0_EPF1_DEVICE_CAP_DEFAULT 0x00000f81 3191 #define smnBIF_CFG_DEV0_EPF1_DEVICE_CNTL_DEFAULT 0x00002810 3192 #define smnBIF_CFG_DEV0_EPF1_DEVICE_STATUS_DEFAULT 0x00000000 3193 #define smnBIF_CFG_DEV0_EPF1_LINK_CAP_DEFAULT 0x00000d04 3194 #define smnBIF_CFG_DEV0_EPF1_LINK_CNTL_DEFAULT 0x00000000 3195 #define smnBIF_CFG_DEV0_EPF1_LINK_STATUS_DEFAULT 0x00000001 3196 #define smnBIF_CFG_DEV0_EPF1_DEVICE_CAP2_DEFAULT 0x00010000 3197 #define smnBIF_CFG_DEV0_EPF1_DEVICE_CNTL2_DEFAULT 0x00000000 3198 #define smnBIF_CFG_DEV0_EPF1_DEVICE_STATUS2_DEFAULT 0x00000000 3199 #define smnBIF_CFG_DEV0_EPF1_LINK_CAP2_DEFAULT 0x0000001e 3200 #define smnBIF_CFG_DEV0_EPF1_LINK_CNTL2_DEFAULT 0x00000004 3201 #define smnBIF_CFG_DEV0_EPF1_LINK_STATUS2_DEFAULT 0x00000001 3202 #define smnBIF_CFG_DEV0_EPF1_MSI_CAP_LIST_DEFAULT 0x0000c000 3203 #define smnBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL_DEFAULT 0x00000080 3204 #define smnBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 3205 #define smnBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 3206 #define smnBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_DEFAULT 0x00000000 3207 #define smnBIF_CFG_DEV0_EPF1_MSI_MASK_DEFAULT 0x00000000 3208 #define smnBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64_DEFAULT 0x00000000 3209 #define smnBIF_CFG_DEV0_EPF1_MSI_MASK_64_DEFAULT 0x00000000 3210 #define smnBIF_CFG_DEV0_EPF1_MSI_PENDING_DEFAULT 0x00000000 3211 #define smnBIF_CFG_DEV0_EPF1_MSI_PENDING_64_DEFAULT 0x00000000 3212 #define smnBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST_DEFAULT 0x00000000 3213 #define smnBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL_DEFAULT 0x00000000 3214 #define smnBIF_CFG_DEV0_EPF1_MSIX_TABLE_DEFAULT 0x00000000 3215 #define smnBIF_CFG_DEV0_EPF1_MSIX_PBA_DEFAULT 0x00000000 3216 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 3217 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 3218 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 3219 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 3220 #define smnBIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 3221 #define smnBIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 3222 #define smnBIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 3223 #define smnBIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 3224 #define smnBIF_CFG_DEV0_EPF1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 3225 #define smnBIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 3226 #define smnBIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe 3227 #define smnBIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 3228 #define smnBIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 3229 #define smnBIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 3230 #define smnBIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 3231 #define smnBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 3232 #define smnBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 3233 #define smnBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 3234 #define smnBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 3235 #define smnBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 3236 #define smnBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 3237 #define smnBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 3238 #define smnBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 3239 #define smnBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 3240 #define smnBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 3241 #define smnBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0_DEFAULT 0x00000000 3242 #define smnBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1_DEFAULT 0x00000000 3243 #define smnBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2_DEFAULT 0x00000000 3244 #define smnBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3_DEFAULT 0x00000000 3245 #define smnBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 3246 #define smnBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 3247 #define smnBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 3248 #define smnBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 3249 #define smnBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 3250 #define smnBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP_DEFAULT 0x00000000 3251 #define smnBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL_DEFAULT 0x00000020 3252 #define smnBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP_DEFAULT 0x00000000 3253 #define smnBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL_DEFAULT 0x00000000 3254 #define smnBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP_DEFAULT 0x00000000 3255 #define smnBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL_DEFAULT 0x00000000 3256 #define smnBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP_DEFAULT 0x00000000 3257 #define smnBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL_DEFAULT 0x00000000 3258 #define smnBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP_DEFAULT 0x00000000 3259 #define smnBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 3260 #define smnBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP_DEFAULT 0x00000000 3261 #define smnBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL_DEFAULT 0x00000000 3262 #define smnBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 3263 #define smnBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 3264 #define smnBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 3265 #define smnBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 3266 #define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 3267 #define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP_DEFAULT 0x00000000 3268 #define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 3269 #define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS_DEFAULT 0x00000100 3270 #define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL_DEFAULT 0x00000000 3271 #define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 3272 #define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 3273 #define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 3274 #define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 3275 #define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 3276 #define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 3277 #define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 3278 #define smnBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 3279 #define smnBIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 3280 #define smnBIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 3281 #define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 3282 #define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 3283 #define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 3284 #define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 3285 #define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 3286 #define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 3287 #define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 3288 #define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 3289 #define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 3290 #define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 3291 #define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 3292 #define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 3293 #define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 3294 #define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 3295 #define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 3296 #define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 3297 #define smnBIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 3298 #define smnBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 3299 #define smnBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP_DEFAULT 0x00000000 3300 #define smnBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL_DEFAULT 0x00000000 3301 #define smnBIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 3302 #define smnBIF_CFG_DEV0_EPF1_PCIE_ATS_CAP_DEFAULT 0x00000000 3303 #define smnBIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL_DEFAULT 0x00000000 3304 #define smnBIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000 3305 #define smnBIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 3306 #define smnBIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000100 3307 #define smnBIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000 3308 #define smnBIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 3309 #define smnBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000 3310 #define smnBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP_DEFAULT 0x00001000 3311 #define smnBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL_DEFAULT 0x00000000 3312 #define smnBIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 3313 #define smnBIF_CFG_DEV0_EPF1_PCIE_MC_CAP_DEFAULT 0x00000000 3314 #define smnBIF_CFG_DEV0_EPF1_PCIE_MC_CNTL_DEFAULT 0x00000000 3315 #define smnBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0_DEFAULT 0x00000000 3316 #define smnBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1_DEFAULT 0x00000000 3317 #define smnBIF_CFG_DEV0_EPF1_PCIE_MC_RCV0_DEFAULT 0x00000000 3318 #define smnBIF_CFG_DEV0_EPF1_PCIE_MC_RCV1_DEFAULT 0x00000000 3319 #define smnBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 3320 #define smnBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 3321 #define smnBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 3322 #define smnBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 3323 #define smnBIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 3324 #define smnBIF_CFG_DEV0_EPF1_PCIE_LTR_CAP_DEFAULT 0x00000000 3325 #define smnBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 3326 #define smnBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP_DEFAULT 0x00000000 3327 #define smnBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL_DEFAULT 0x00000000 3328 #define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x37000000 3329 #define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP_DEFAULT 0x00000000 3330 #define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000 3331 #define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS_DEFAULT 0x00000000 3332 #define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000 3333 #define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000 3334 #define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000 3335 #define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000 3336 #define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000 3337 #define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000 3338 #define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000 3339 #define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000 3340 #define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001 3341 #define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000 3342 #define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000 3343 #define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000 3344 #define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000 3345 #define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000 3346 #define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000 3347 #define smnBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000 3348 #define smnBIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000 3349 #define smnBIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000 3350 #define smnBIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 3351 #define smnBIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41010025 3352 #define smnBIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP_DEFAULT 0x00000001 3353 #define smnBIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000 3354 #define smnBIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44010026 3355 #define smnBIF_CFG_DEV0_EPF1_LINK_CAP_16GT_DEFAULT 0x00000000 3356 #define smnBIF_CFG_DEV0_EPF1_LINK_CNTL_16GT_DEFAULT 0x00000000 3357 #define smnBIF_CFG_DEV0_EPF1_LINK_STATUS_16GT_DEFAULT 0x00000000 3358 #define smnBIF_CFG_DEV0_EPF1_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 3359 #define smnBIF_CFG_DEV0_EPF1_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 3360 #define smnBIF_CFG_DEV0_EPF1_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 3361 #define smnBIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3362 #define smnBIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3363 #define smnBIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3364 #define smnBIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3365 #define smnBIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3366 #define smnBIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3367 #define smnBIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3368 #define smnBIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3369 #define smnBIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3370 #define smnBIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3371 #define smnBIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3372 #define smnBIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3373 #define smnBIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3374 #define smnBIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3375 #define smnBIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3376 #define smnBIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 3377 #define smnBIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x4c010027 3378 #define smnBIF_CFG_DEV0_EPF1_MARGINING_PORT_CAP_DEFAULT 0x00000000 3379 #define smnBIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS_DEFAULT 0x00000000 3380 #define smnBIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3381 #define smnBIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3382 #define smnBIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3383 #define smnBIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3384 #define smnBIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3385 #define smnBIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3386 #define smnBIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3387 #define smnBIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3388 #define smnBIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3389 #define smnBIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3390 #define smnBIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3391 #define smnBIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3392 #define smnBIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3393 #define smnBIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3394 #define smnBIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3395 #define smnBIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3396 #define smnBIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3397 #define smnBIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3398 #define smnBIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3399 #define smnBIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3400 #define smnBIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3401 #define smnBIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3402 #define smnBIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3403 #define smnBIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3404 #define smnBIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3405 #define smnBIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3406 #define smnBIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3407 #define smnBIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3408 #define smnBIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3409 #define smnBIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3410 #define smnBIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 3411 #define smnBIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000 3412 #define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_DEFAULT 0x00000000 3413 #define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP_DEFAULT 0x00000000 3414 #define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL_DEFAULT 0x00000020 3415 #define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP_DEFAULT 0x00000000 3416 #define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL_DEFAULT 0x00000000 3417 #define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP_DEFAULT 0x00000000 3418 #define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL_DEFAULT 0x00000000 3419 #define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP_DEFAULT 0x00000000 3420 #define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL_DEFAULT 0x00000000 3421 #define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP_DEFAULT 0x00000000 3422 #define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL_DEFAULT 0x00000000 3423 #define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP_DEFAULT 0x00000000 3424 #define smnBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL_DEFAULT 0x00000000 3425 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000 3426 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000 3427 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000 3428 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000 3429 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000 3430 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000 3431 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000 3432 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000 3433 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000 3434 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000 3435 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000 3436 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x0012000c 3437 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_DEFAULT 0x00000000 3438 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_DEFAULT 0x00000000 3439 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000 3440 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000 3441 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000 3442 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000 3443 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000 3444 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000 3445 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000 3446 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000 3447 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000 3448 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000 3449 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000 3450 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000 3451 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000 3452 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000 3453 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000 3454 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000 3455 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_DEFAULT 0x00000000 3456 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_DEFAULT 0x00000000 3457 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_DEFAULT 0x00000000 3458 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_DEFAULT 0x00000000 3459 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_DEFAULT 0x00000000 3460 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_DEFAULT 0x00000000 3461 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_DEFAULT 0x00000000 3462 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_DEFAULT 0x00000000 3463 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_DEFAULT 0x00000000 3464 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_DEFAULT 0x00000000 3465 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_DEFAULT 0x00000000 3466 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_DEFAULT 0x00000000 3467 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_DEFAULT 0x00000000 3468 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_DEFAULT 0x00000000 3469 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_DEFAULT 0x00000000 3470 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000 3471 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000 3472 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000 3473 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000 3474 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000 3475 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000 3476 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000 3477 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000 3478 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000 3479 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000 3480 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000 3481 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000 3482 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000 3483 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000 3484 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000 3485 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000 3486 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000 3487 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000 3488 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000 3489 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000 3490 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000 3491 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000 3492 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000 3493 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000 3494 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000 3495 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000 3496 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000 3497 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0_DEFAULT 0x00000000 3498 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1_DEFAULT 0x00000000 3499 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2_DEFAULT 0x00000000 3500 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3_DEFAULT 0x00000000 3501 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4_DEFAULT 0x00000000 3502 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5_DEFAULT 0x00000000 3503 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6_DEFAULT 0x00000000 3504 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7_DEFAULT 0x00000000 3505 #define smnBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8_DEFAULT 0x00000000 3506 3507 3508 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp 3509 #define smnBIF_CFG_DEV0_EPF2_VENDOR_ID_DEFAULT 0x00001002 3510 #define smnBIF_CFG_DEV0_EPF2_DEVICE_ID_DEFAULT 0x00007316 3511 #define smnBIF_CFG_DEV0_EPF2_COMMAND_DEFAULT 0x00000000 3512 #define smnBIF_CFG_DEV0_EPF2_STATUS_DEFAULT 0x00000000 3513 #define smnBIF_CFG_DEV0_EPF2_REVISION_ID_DEFAULT 0x00000000 3514 #define smnBIF_CFG_DEV0_EPF2_PROG_INTERFACE_DEFAULT 0x00000030 3515 #define smnBIF_CFG_DEV0_EPF2_SUB_CLASS_DEFAULT 0x00000003 3516 #define smnBIF_CFG_DEV0_EPF2_BASE_CLASS_DEFAULT 0x0000000c 3517 #define smnBIF_CFG_DEV0_EPF2_CACHE_LINE_DEFAULT 0x00000000 3518 #define smnBIF_CFG_DEV0_EPF2_LATENCY_DEFAULT 0x00000000 3519 #define smnBIF_CFG_DEV0_EPF2_HEADER_DEFAULT 0x00000080 3520 #define smnBIF_CFG_DEV0_EPF2_BIST_DEFAULT 0x00000000 3521 #define smnBIF_CFG_DEV0_EPF2_BASE_ADDR_1_DEFAULT 0x00000000 3522 #define smnBIF_CFG_DEV0_EPF2_BASE_ADDR_2_DEFAULT 0x00000000 3523 #define smnBIF_CFG_DEV0_EPF2_BASE_ADDR_3_DEFAULT 0x00000000 3524 #define smnBIF_CFG_DEV0_EPF2_BASE_ADDR_4_DEFAULT 0x00000000 3525 #define smnBIF_CFG_DEV0_EPF2_BASE_ADDR_5_DEFAULT 0x00000000 3526 #define smnBIF_CFG_DEV0_EPF2_BASE_ADDR_6_DEFAULT 0x00000000 3527 #define smnBIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR_DEFAULT 0x00000000 3528 #define smnBIF_CFG_DEV0_EPF2_ADAPTER_ID_DEFAULT 0x73161002 3529 #define smnBIF_CFG_DEV0_EPF2_ROM_BASE_ADDR_DEFAULT 0x00000000 3530 #define smnBIF_CFG_DEV0_EPF2_CAP_PTR_DEFAULT 0x00000048 3531 #define smnBIF_CFG_DEV0_EPF2_INTERRUPT_LINE_DEFAULT 0x00000000 3532 #define smnBIF_CFG_DEV0_EPF2_INTERRUPT_PIN_DEFAULT 0x00000003 3533 #define smnBIF_CFG_DEV0_EPF2_MIN_GRANT_DEFAULT 0x00000000 3534 #define smnBIF_CFG_DEV0_EPF2_MAX_LATENCY_DEFAULT 0x00000000 3535 #define smnBIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST_DEFAULT 0x00000000 3536 #define smnBIF_CFG_DEV0_EPF2_ADAPTER_ID_W_DEFAULT 0x73161002 3537 #define smnBIF_CFG_DEV0_EPF2_PMI_CAP_LIST_DEFAULT 0x00006400 3538 #define smnBIF_CFG_DEV0_EPF2_PMI_CAP_DEFAULT 0x0000c800 3539 #define smnBIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL_DEFAULT 0x00000000 3540 #define smnBIF_CFG_DEV0_EPF2_SBRN_DEFAULT 0x00000000 3541 #define smnBIF_CFG_DEV0_EPF2_FLADJ_DEFAULT 0x00000020 3542 #define smnBIF_CFG_DEV0_EPF2_DBESL_DBESLD_DEFAULT 0x00000000 3543 #define smnBIF_CFG_DEV0_EPF2_PCIE_CAP_LIST_DEFAULT 0x0000a000 3544 #define smnBIF_CFG_DEV0_EPF2_PCIE_CAP_DEFAULT 0x00000002 3545 #define smnBIF_CFG_DEV0_EPF2_DEVICE_CAP_DEFAULT 0x00000f81 3546 #define smnBIF_CFG_DEV0_EPF2_DEVICE_CNTL_DEFAULT 0x00002810 3547 #define smnBIF_CFG_DEV0_EPF2_DEVICE_STATUS_DEFAULT 0x00000000 3548 #define smnBIF_CFG_DEV0_EPF2_LINK_CAP_DEFAULT 0x00000d04 3549 #define smnBIF_CFG_DEV0_EPF2_LINK_CNTL_DEFAULT 0x00000000 3550 #define smnBIF_CFG_DEV0_EPF2_LINK_STATUS_DEFAULT 0x00000001 3551 #define smnBIF_CFG_DEV0_EPF2_DEVICE_CAP2_DEFAULT 0x00010000 3552 #define smnBIF_CFG_DEV0_EPF2_DEVICE_CNTL2_DEFAULT 0x00000000 3553 #define smnBIF_CFG_DEV0_EPF2_DEVICE_STATUS2_DEFAULT 0x00000000 3554 #define smnBIF_CFG_DEV0_EPF2_LINK_CAP2_DEFAULT 0x0000001e 3555 #define smnBIF_CFG_DEV0_EPF2_LINK_CNTL2_DEFAULT 0x00000004 3556 #define smnBIF_CFG_DEV0_EPF2_LINK_STATUS2_DEFAULT 0x00000001 3557 #define smnBIF_CFG_DEV0_EPF2_MSI_CAP_LIST_DEFAULT 0x0000c000 3558 #define smnBIF_CFG_DEV0_EPF2_MSI_MSG_CNTL_DEFAULT 0x00000086 3559 #define smnBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 3560 #define smnBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 3561 #define smnBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_DEFAULT 0x00000000 3562 #define smnBIF_CFG_DEV0_EPF2_MSI_MASK_DEFAULT 0x00000000 3563 #define smnBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64_DEFAULT 0x00000000 3564 #define smnBIF_CFG_DEV0_EPF2_MSI_MASK_64_DEFAULT 0x00000000 3565 #define smnBIF_CFG_DEV0_EPF2_MSI_PENDING_DEFAULT 0x00000000 3566 #define smnBIF_CFG_DEV0_EPF2_MSI_PENDING_64_DEFAULT 0x00000000 3567 #define smnBIF_CFG_DEV0_EPF2_MSIX_CAP_LIST_DEFAULT 0x00000000 3568 #define smnBIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL_DEFAULT 0x00000000 3569 #define smnBIF_CFG_DEV0_EPF2_MSIX_TABLE_DEFAULT 0x00000000 3570 #define smnBIF_CFG_DEV0_EPF2_MSIX_PBA_DEFAULT 0x00000000 3571 #define smnBIF_CFG_DEV0_EPF2_SATA_CAP_0_DEFAULT 0x00000000 3572 #define smnBIF_CFG_DEV0_EPF2_SATA_CAP_1_DEFAULT 0x00000000 3573 #define smnBIF_CFG_DEV0_EPF2_SATA_IDP_INDEX_DEFAULT 0x00000000 3574 #define smnBIF_CFG_DEV0_EPF2_SATA_IDP_DATA_DEFAULT 0x00000000 3575 #define smnBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 3576 #define smnBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 3577 #define smnBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 3578 #define smnBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 3579 #define smnBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 3580 #define smnBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 3581 #define smnBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 3582 #define smnBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 3583 #define smnBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 3584 #define smnBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 3585 #define smnBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 3586 #define smnBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0_DEFAULT 0x00000000 3587 #define smnBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1_DEFAULT 0x00000000 3588 #define smnBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2_DEFAULT 0x00000000 3589 #define smnBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3_DEFAULT 0x00000000 3590 #define smnBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 3591 #define smnBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 3592 #define smnBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 3593 #define smnBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 3594 #define smnBIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 3595 #define smnBIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP_DEFAULT 0x00000000 3596 #define smnBIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL_DEFAULT 0x00000020 3597 #define smnBIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP_DEFAULT 0x00000000 3598 #define smnBIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL_DEFAULT 0x00000000 3599 #define smnBIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP_DEFAULT 0x00000000 3600 #define smnBIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL_DEFAULT 0x00000000 3601 #define smnBIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP_DEFAULT 0x00000000 3602 #define smnBIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL_DEFAULT 0x00000000 3603 #define smnBIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP_DEFAULT 0x00000000 3604 #define smnBIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL_DEFAULT 0x00000000 3605 #define smnBIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP_DEFAULT 0x00000000 3606 #define smnBIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL_DEFAULT 0x00000000 3607 #define smnBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 3608 #define smnBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 3609 #define smnBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 3610 #define smnBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 3611 #define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 3612 #define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_CAP_DEFAULT 0x00000000 3613 #define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 3614 #define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS_DEFAULT 0x00000100 3615 #define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL_DEFAULT 0x00000000 3616 #define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 3617 #define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 3618 #define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 3619 #define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 3620 #define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 3621 #define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 3622 #define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 3623 #define smnBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 3624 #define smnBIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 3625 #define smnBIF_CFG_DEV0_EPF2_PCIE_ACS_CAP_DEFAULT 0x00000000 3626 #define smnBIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL_DEFAULT 0x00000000 3627 #define smnBIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000 3628 #define smnBIF_CFG_DEV0_EPF2_PCIE_PASID_CAP_DEFAULT 0x00001000 3629 #define smnBIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL_DEFAULT 0x00000000 3630 #define smnBIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 3631 #define smnBIF_CFG_DEV0_EPF2_PCIE_ARI_CAP_DEFAULT 0x00000000 3632 #define smnBIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL_DEFAULT 0x00000000 3633 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000 3634 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000 3635 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 3636 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0_DEFAULT 0x00000000 3637 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1_DEFAULT 0x00000000 3638 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2_DEFAULT 0x00000000 3639 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3_DEFAULT 0x00000000 3640 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4_DEFAULT 0x00000000 3641 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5_DEFAULT 0x00000000 3642 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6_DEFAULT 0x00000000 3643 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7_DEFAULT 0x00000000 3644 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8_DEFAULT 0x00000000 3645 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9_DEFAULT 0x00000000 3646 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10_DEFAULT 0x00000000 3647 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11_DEFAULT 0x00000000 3648 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12_DEFAULT 0x00000000 3649 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13_DEFAULT 0x00000000 3650 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14_DEFAULT 0x00000000 3651 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15_DEFAULT 0x00000000 3652 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16_DEFAULT 0x00000000 3653 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17_DEFAULT 0x00000000 3654 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18_DEFAULT 0x00000000 3655 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19_DEFAULT 0x00000000 3656 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20_DEFAULT 0x00000000 3657 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21_DEFAULT 0x00000000 3658 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22_DEFAULT 0x00000000 3659 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23_DEFAULT 0x00000000 3660 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24_DEFAULT 0x00000000 3661 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25_DEFAULT 0x00000000 3662 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26_DEFAULT 0x00000000 3663 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27_DEFAULT 0x00000000 3664 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28_DEFAULT 0x00000000 3665 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29_DEFAULT 0x00000000 3666 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30_DEFAULT 0x00000000 3667 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31_DEFAULT 0x00000000 3668 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32_DEFAULT 0x00000000 3669 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33_DEFAULT 0x00000000 3670 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34_DEFAULT 0x00000000 3671 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35_DEFAULT 0x00000000 3672 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36_DEFAULT 0x00000000 3673 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37_DEFAULT 0x00000000 3674 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38_DEFAULT 0x00000000 3675 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39_DEFAULT 0x00000000 3676 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40_DEFAULT 0x00000000 3677 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41_DEFAULT 0x00000000 3678 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42_DEFAULT 0x00000000 3679 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43_DEFAULT 0x00000000 3680 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44_DEFAULT 0x00000000 3681 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45_DEFAULT 0x00000000 3682 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46_DEFAULT 0x00000000 3683 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47_DEFAULT 0x00000000 3684 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48_DEFAULT 0x00000000 3685 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49_DEFAULT 0x00000000 3686 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50_DEFAULT 0x00000000 3687 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51_DEFAULT 0x00000000 3688 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52_DEFAULT 0x00000000 3689 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53_DEFAULT 0x00000000 3690 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54_DEFAULT 0x00000000 3691 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55_DEFAULT 0x00000000 3692 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56_DEFAULT 0x00000000 3693 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57_DEFAULT 0x00000000 3694 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58_DEFAULT 0x00000000 3695 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59_DEFAULT 0x00000000 3696 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60_DEFAULT 0x00000000 3697 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61_DEFAULT 0x00000000 3698 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62_DEFAULT 0x00000000 3699 #define smnBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63_DEFAULT 0x00000000 3700 3701 3702 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp 3703 #define smnBIF_CFG_DEV0_EPF3_VENDOR_ID_DEFAULT 0x00001002 3704 #define smnBIF_CFG_DEV0_EPF3_DEVICE_ID_DEFAULT 0x00007314 3705 #define smnBIF_CFG_DEV0_EPF3_COMMAND_DEFAULT 0x00000000 3706 #define smnBIF_CFG_DEV0_EPF3_STATUS_DEFAULT 0x00000000 3707 #define smnBIF_CFG_DEV0_EPF3_REVISION_ID_DEFAULT 0x00000000 3708 #define smnBIF_CFG_DEV0_EPF3_PROG_INTERFACE_DEFAULT 0x00000000 3709 #define smnBIF_CFG_DEV0_EPF3_SUB_CLASS_DEFAULT 0x00000080 3710 #define smnBIF_CFG_DEV0_EPF3_BASE_CLASS_DEFAULT 0x0000000c 3711 #define smnBIF_CFG_DEV0_EPF3_CACHE_LINE_DEFAULT 0x00000000 3712 #define smnBIF_CFG_DEV0_EPF3_LATENCY_DEFAULT 0x00000000 3713 #define smnBIF_CFG_DEV0_EPF3_HEADER_DEFAULT 0x00000080 3714 #define smnBIF_CFG_DEV0_EPF3_BIST_DEFAULT 0x00000000 3715 #define smnBIF_CFG_DEV0_EPF3_BASE_ADDR_1_DEFAULT 0x00000000 3716 #define smnBIF_CFG_DEV0_EPF3_BASE_ADDR_2_DEFAULT 0x00000000 3717 #define smnBIF_CFG_DEV0_EPF3_BASE_ADDR_3_DEFAULT 0x00000000 3718 #define smnBIF_CFG_DEV0_EPF3_BASE_ADDR_4_DEFAULT 0x00000000 3719 #define smnBIF_CFG_DEV0_EPF3_BASE_ADDR_5_DEFAULT 0x00000000 3720 #define smnBIF_CFG_DEV0_EPF3_BASE_ADDR_6_DEFAULT 0x00000000 3721 #define smnBIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR_DEFAULT 0x00000000 3722 #define smnBIF_CFG_DEV0_EPF3_ADAPTER_ID_DEFAULT 0x73141002 3723 #define smnBIF_CFG_DEV0_EPF3_ROM_BASE_ADDR_DEFAULT 0x00000000 3724 #define smnBIF_CFG_DEV0_EPF3_CAP_PTR_DEFAULT 0x00000048 3725 #define smnBIF_CFG_DEV0_EPF3_INTERRUPT_LINE_DEFAULT 0x00000000 3726 #define smnBIF_CFG_DEV0_EPF3_INTERRUPT_PIN_DEFAULT 0x00000004 3727 #define smnBIF_CFG_DEV0_EPF3_MIN_GRANT_DEFAULT 0x00000000 3728 #define smnBIF_CFG_DEV0_EPF3_MAX_LATENCY_DEFAULT 0x00000000 3729 #define smnBIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST_DEFAULT 0x00000000 3730 #define smnBIF_CFG_DEV0_EPF3_ADAPTER_ID_W_DEFAULT 0x73141002 3731 #define smnBIF_CFG_DEV0_EPF3_PMI_CAP_LIST_DEFAULT 0x00006400 3732 #define smnBIF_CFG_DEV0_EPF3_PMI_CAP_DEFAULT 0x00000000 3733 #define smnBIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL_DEFAULT 0x00000000 3734 #define smnBIF_CFG_DEV0_EPF3_SBRN_DEFAULT 0x00000000 3735 #define smnBIF_CFG_DEV0_EPF3_FLADJ_DEFAULT 0x00000020 3736 #define smnBIF_CFG_DEV0_EPF3_DBESL_DBESLD_DEFAULT 0x00000000 3737 #define smnBIF_CFG_DEV0_EPF3_PCIE_CAP_LIST_DEFAULT 0x0000a000 3738 #define smnBIF_CFG_DEV0_EPF3_PCIE_CAP_DEFAULT 0x00000002 3739 #define smnBIF_CFG_DEV0_EPF3_DEVICE_CAP_DEFAULT 0x00000f81 3740 #define smnBIF_CFG_DEV0_EPF3_DEVICE_CNTL_DEFAULT 0x00002810 3741 #define smnBIF_CFG_DEV0_EPF3_DEVICE_STATUS_DEFAULT 0x00000000 3742 #define smnBIF_CFG_DEV0_EPF3_LINK_CAP_DEFAULT 0x00000d04 3743 #define smnBIF_CFG_DEV0_EPF3_LINK_CNTL_DEFAULT 0x00000000 3744 #define smnBIF_CFG_DEV0_EPF3_LINK_STATUS_DEFAULT 0x00000001 3745 #define smnBIF_CFG_DEV0_EPF3_DEVICE_CAP2_DEFAULT 0x00010000 3746 #define smnBIF_CFG_DEV0_EPF3_DEVICE_CNTL2_DEFAULT 0x00000000 3747 #define smnBIF_CFG_DEV0_EPF3_DEVICE_STATUS2_DEFAULT 0x00000000 3748 #define smnBIF_CFG_DEV0_EPF3_LINK_CAP2_DEFAULT 0x0000001e 3749 #define smnBIF_CFG_DEV0_EPF3_LINK_CNTL2_DEFAULT 0x00000004 3750 #define smnBIF_CFG_DEV0_EPF3_LINK_STATUS2_DEFAULT 0x00000001 3751 #define smnBIF_CFG_DEV0_EPF3_MSI_CAP_LIST_DEFAULT 0x0000c000 3752 #define smnBIF_CFG_DEV0_EPF3_MSI_MSG_CNTL_DEFAULT 0x00000082 3753 #define smnBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 3754 #define smnBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 3755 #define smnBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_DEFAULT 0x00000000 3756 #define smnBIF_CFG_DEV0_EPF3_MSI_MASK_DEFAULT 0x00000000 3757 #define smnBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64_DEFAULT 0x00000000 3758 #define smnBIF_CFG_DEV0_EPF3_MSI_MASK_64_DEFAULT 0x00000000 3759 #define smnBIF_CFG_DEV0_EPF3_MSI_PENDING_DEFAULT 0x00000000 3760 #define smnBIF_CFG_DEV0_EPF3_MSI_PENDING_64_DEFAULT 0x00000000 3761 #define smnBIF_CFG_DEV0_EPF3_MSIX_CAP_LIST_DEFAULT 0x00000000 3762 #define smnBIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL_DEFAULT 0x00000000 3763 #define smnBIF_CFG_DEV0_EPF3_MSIX_TABLE_DEFAULT 0x00000000 3764 #define smnBIF_CFG_DEV0_EPF3_MSIX_PBA_DEFAULT 0x00000000 3765 #define smnBIF_CFG_DEV0_EPF3_SATA_CAP_0_DEFAULT 0x00000000 3766 #define smnBIF_CFG_DEV0_EPF3_SATA_CAP_1_DEFAULT 0x00000000 3767 #define smnBIF_CFG_DEV0_EPF3_SATA_IDP_INDEX_DEFAULT 0x00000000 3768 #define smnBIF_CFG_DEV0_EPF3_SATA_IDP_DATA_DEFAULT 0x00000000 3769 #define smnBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 3770 #define smnBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 3771 #define smnBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 3772 #define smnBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 3773 #define smnBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 3774 #define smnBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 3775 #define smnBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 3776 #define smnBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 3777 #define smnBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 3778 #define smnBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 3779 #define smnBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 3780 #define smnBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0_DEFAULT 0x00000000 3781 #define smnBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1_DEFAULT 0x00000000 3782 #define smnBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2_DEFAULT 0x00000000 3783 #define smnBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3_DEFAULT 0x00000000 3784 #define smnBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 3785 #define smnBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 3786 #define smnBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 3787 #define smnBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 3788 #define smnBIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 3789 #define smnBIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP_DEFAULT 0x00000000 3790 #define smnBIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL_DEFAULT 0x00000020 3791 #define smnBIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP_DEFAULT 0x00000000 3792 #define smnBIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL_DEFAULT 0x00000000 3793 #define smnBIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP_DEFAULT 0x00000000 3794 #define smnBIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL_DEFAULT 0x00000000 3795 #define smnBIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP_DEFAULT 0x00000000 3796 #define smnBIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL_DEFAULT 0x00000000 3797 #define smnBIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP_DEFAULT 0x00000000 3798 #define smnBIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL_DEFAULT 0x00000000 3799 #define smnBIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP_DEFAULT 0x00000000 3800 #define smnBIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL_DEFAULT 0x00000000 3801 #define smnBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 3802 #define smnBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 3803 #define smnBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 3804 #define smnBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 3805 #define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 3806 #define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_CAP_DEFAULT 0x00000000 3807 #define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 3808 #define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS_DEFAULT 0x00000100 3809 #define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL_DEFAULT 0x00000000 3810 #define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 3811 #define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 3812 #define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 3813 #define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 3814 #define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 3815 #define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 3816 #define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 3817 #define smnBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 3818 #define smnBIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 3819 #define smnBIF_CFG_DEV0_EPF3_PCIE_ACS_CAP_DEFAULT 0x00000000 3820 #define smnBIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL_DEFAULT 0x00000000 3821 #define smnBIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000 3822 #define smnBIF_CFG_DEV0_EPF3_PCIE_PASID_CAP_DEFAULT 0x00001000 3823 #define smnBIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL_DEFAULT 0x00000000 3824 #define smnBIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 3825 #define smnBIF_CFG_DEV0_EPF3_PCIE_ARI_CAP_DEFAULT 0x00000000 3826 #define smnBIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL_DEFAULT 0x00000000 3827 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000 3828 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000 3829 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 3830 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0_DEFAULT 0x00000000 3831 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1_DEFAULT 0x00000000 3832 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2_DEFAULT 0x00000000 3833 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3_DEFAULT 0x00000000 3834 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4_DEFAULT 0x00000000 3835 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5_DEFAULT 0x00000000 3836 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6_DEFAULT 0x00000000 3837 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7_DEFAULT 0x00000000 3838 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8_DEFAULT 0x00000000 3839 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9_DEFAULT 0x00000000 3840 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10_DEFAULT 0x00000000 3841 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11_DEFAULT 0x00000000 3842 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12_DEFAULT 0x00000000 3843 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13_DEFAULT 0x00000000 3844 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14_DEFAULT 0x00000000 3845 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15_DEFAULT 0x00000000 3846 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16_DEFAULT 0x00000000 3847 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17_DEFAULT 0x00000000 3848 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18_DEFAULT 0x00000000 3849 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19_DEFAULT 0x00000000 3850 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20_DEFAULT 0x00000000 3851 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21_DEFAULT 0x00000000 3852 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22_DEFAULT 0x00000000 3853 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23_DEFAULT 0x00000000 3854 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24_DEFAULT 0x00000000 3855 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25_DEFAULT 0x00000000 3856 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26_DEFAULT 0x00000000 3857 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27_DEFAULT 0x00000000 3858 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28_DEFAULT 0x00000000 3859 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29_DEFAULT 0x00000000 3860 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30_DEFAULT 0x00000000 3861 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31_DEFAULT 0x00000000 3862 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32_DEFAULT 0x00000000 3863 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33_DEFAULT 0x00000000 3864 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34_DEFAULT 0x00000000 3865 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35_DEFAULT 0x00000000 3866 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36_DEFAULT 0x00000000 3867 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37_DEFAULT 0x00000000 3868 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38_DEFAULT 0x00000000 3869 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39_DEFAULT 0x00000000 3870 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40_DEFAULT 0x00000000 3871 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41_DEFAULT 0x00000000 3872 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42_DEFAULT 0x00000000 3873 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43_DEFAULT 0x00000000 3874 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44_DEFAULT 0x00000000 3875 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45_DEFAULT 0x00000000 3876 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46_DEFAULT 0x00000000 3877 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47_DEFAULT 0x00000000 3878 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48_DEFAULT 0x00000000 3879 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49_DEFAULT 0x00000000 3880 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50_DEFAULT 0x00000000 3881 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51_DEFAULT 0x00000000 3882 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52_DEFAULT 0x00000000 3883 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53_DEFAULT 0x00000000 3884 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54_DEFAULT 0x00000000 3885 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55_DEFAULT 0x00000000 3886 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56_DEFAULT 0x00000000 3887 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57_DEFAULT 0x00000000 3888 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58_DEFAULT 0x00000000 3889 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59_DEFAULT 0x00000000 3890 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60_DEFAULT 0x00000000 3891 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61_DEFAULT 0x00000000 3892 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62_DEFAULT 0x00000000 3893 #define smnBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63_DEFAULT 0x00000000 3894 3895 3896 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp 3897 #define smnBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID_DEFAULT 0x00000000 3898 #define smnBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID_DEFAULT 0x00000000 3899 #define smnBIF_CFG_DEV0_EPF0_VF0_COMMAND_DEFAULT 0x00000000 3900 #define smnBIF_CFG_DEV0_EPF0_VF0_STATUS_DEFAULT 0x00000000 3901 #define smnBIF_CFG_DEV0_EPF0_VF0_REVISION_ID_DEFAULT 0x00000000 3902 #define smnBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE_DEFAULT 0x00000000 3903 #define smnBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS_DEFAULT 0x00000000 3904 #define smnBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS_DEFAULT 0x00000000 3905 #define smnBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE_DEFAULT 0x00000000 3906 #define smnBIF_CFG_DEV0_EPF0_VF0_LATENCY_DEFAULT 0x00000000 3907 #define smnBIF_CFG_DEV0_EPF0_VF0_HEADER_DEFAULT 0x00000000 3908 #define smnBIF_CFG_DEV0_EPF0_VF0_BIST_DEFAULT 0x00000000 3909 #define smnBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1_DEFAULT 0x00000000 3910 #define smnBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2_DEFAULT 0x00000000 3911 #define smnBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3_DEFAULT 0x00000000 3912 #define smnBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4_DEFAULT 0x00000000 3913 #define smnBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5_DEFAULT 0x00000000 3914 #define smnBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6_DEFAULT 0x00000000 3915 #define smnBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 3916 #define smnBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID_DEFAULT 0x73101002 3917 #define smnBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR_DEFAULT 0x00000000 3918 #define smnBIF_CFG_DEV0_EPF0_VF0_CAP_PTR_DEFAULT 0x00000048 3919 #define smnBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE_DEFAULT 0x00000000 3920 #define smnBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN_DEFAULT 0x00000000 3921 #define smnBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT_DEFAULT 0x00000000 3922 #define smnBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY_DEFAULT 0x00000000 3923 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST_DEFAULT 0x0000a000 3924 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_DEFAULT 0x00000002 3925 #define smnBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP_DEFAULT 0x00000000 3926 #define smnBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL_DEFAULT 0x00000000 3927 #define smnBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS_DEFAULT 0x00000000 3928 #define smnBIF_CFG_DEV0_EPF0_VF0_LINK_CAP_DEFAULT 0x00000d04 3929 #define smnBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL_DEFAULT 0x00000000 3930 #define smnBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS_DEFAULT 0x00000000 3931 #define smnBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2_DEFAULT 0x00010000 3932 #define smnBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2_DEFAULT 0x00000000 3933 #define smnBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2_DEFAULT 0x00000000 3934 #define smnBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2_DEFAULT 0x0000001e 3935 #define smnBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2_DEFAULT 0x00000000 3936 #define smnBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2_DEFAULT 0x00000000 3937 #define smnBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST_DEFAULT 0x0000c000 3938 #define smnBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL_DEFAULT 0x00000082 3939 #define smnBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 3940 #define smnBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 3941 #define smnBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_DEFAULT 0x00000000 3942 #define smnBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_DEFAULT 0x00000000 3943 #define smnBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64_DEFAULT 0x00000000 3944 #define smnBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64_DEFAULT 0x00000000 3945 #define smnBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_DEFAULT 0x00000000 3946 #define smnBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64_DEFAULT 0x00000000 3947 #define smnBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST_DEFAULT 0x00000000 3948 #define smnBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL_DEFAULT 0x00000000 3949 #define smnBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE_DEFAULT 0x00000000 3950 #define smnBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA_DEFAULT 0x00000000 3951 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 3952 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 3953 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 3954 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 3955 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 3956 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 3957 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 3958 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 3959 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 3960 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 3961 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 3962 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0_DEFAULT 0x00000000 3963 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1_DEFAULT 0x00000000 3964 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2_DEFAULT 0x00000000 3965 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3_DEFAULT 0x00000000 3966 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 3967 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 3968 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 3969 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 3970 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 3971 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP_DEFAULT 0x00000000 3972 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL_DEFAULT 0x00000000 3973 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 3974 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP_DEFAULT 0x00000000 3975 #define smnBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL_DEFAULT 0x00000000 3976 3977 3978 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp 3979 #define smnBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID_DEFAULT 0x00000000 3980 #define smnBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID_DEFAULT 0x00000000 3981 #define smnBIF_CFG_DEV0_EPF0_VF1_COMMAND_DEFAULT 0x00000000 3982 #define smnBIF_CFG_DEV0_EPF0_VF1_STATUS_DEFAULT 0x00000000 3983 #define smnBIF_CFG_DEV0_EPF0_VF1_REVISION_ID_DEFAULT 0x00000000 3984 #define smnBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE_DEFAULT 0x00000000 3985 #define smnBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS_DEFAULT 0x00000000 3986 #define smnBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS_DEFAULT 0x00000000 3987 #define smnBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE_DEFAULT 0x00000000 3988 #define smnBIF_CFG_DEV0_EPF0_VF1_LATENCY_DEFAULT 0x00000000 3989 #define smnBIF_CFG_DEV0_EPF0_VF1_HEADER_DEFAULT 0x00000000 3990 #define smnBIF_CFG_DEV0_EPF0_VF1_BIST_DEFAULT 0x00000000 3991 #define smnBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1_DEFAULT 0x00000000 3992 #define smnBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2_DEFAULT 0x00000000 3993 #define smnBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3_DEFAULT 0x00000000 3994 #define smnBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4_DEFAULT 0x00000000 3995 #define smnBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5_DEFAULT 0x00000000 3996 #define smnBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6_DEFAULT 0x00000000 3997 #define smnBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 3998 #define smnBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID_DEFAULT 0x73101002 3999 #define smnBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR_DEFAULT 0x00000000 4000 #define smnBIF_CFG_DEV0_EPF0_VF1_CAP_PTR_DEFAULT 0x00000048 4001 #define smnBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE_DEFAULT 0x00000000 4002 #define smnBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN_DEFAULT 0x00000000 4003 #define smnBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT_DEFAULT 0x00000000 4004 #define smnBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY_DEFAULT 0x00000000 4005 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST_DEFAULT 0x0000a000 4006 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_DEFAULT 0x00000002 4007 #define smnBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP_DEFAULT 0x00000000 4008 #define smnBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL_DEFAULT 0x00000000 4009 #define smnBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS_DEFAULT 0x00000000 4010 #define smnBIF_CFG_DEV0_EPF0_VF1_LINK_CAP_DEFAULT 0x00000d04 4011 #define smnBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL_DEFAULT 0x00000000 4012 #define smnBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS_DEFAULT 0x00000000 4013 #define smnBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2_DEFAULT 0x00010000 4014 #define smnBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2_DEFAULT 0x00000000 4015 #define smnBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2_DEFAULT 0x00000000 4016 #define smnBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2_DEFAULT 0x0000001e 4017 #define smnBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2_DEFAULT 0x00000000 4018 #define smnBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2_DEFAULT 0x00000000 4019 #define smnBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST_DEFAULT 0x0000c000 4020 #define smnBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL_DEFAULT 0x00000082 4021 #define smnBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 4022 #define smnBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 4023 #define smnBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_DEFAULT 0x00000000 4024 #define smnBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_DEFAULT 0x00000000 4025 #define smnBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64_DEFAULT 0x00000000 4026 #define smnBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64_DEFAULT 0x00000000 4027 #define smnBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_DEFAULT 0x00000000 4028 #define smnBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64_DEFAULT 0x00000000 4029 #define smnBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST_DEFAULT 0x00000000 4030 #define smnBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL_DEFAULT 0x00000000 4031 #define smnBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE_DEFAULT 0x00000000 4032 #define smnBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA_DEFAULT 0x00000000 4033 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 4034 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 4035 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 4036 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 4037 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 4038 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 4039 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 4040 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 4041 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 4042 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 4043 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 4044 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0_DEFAULT 0x00000000 4045 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1_DEFAULT 0x00000000 4046 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2_DEFAULT 0x00000000 4047 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3_DEFAULT 0x00000000 4048 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 4049 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 4050 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 4051 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 4052 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 4053 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP_DEFAULT 0x00000000 4054 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL_DEFAULT 0x00000000 4055 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 4056 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP_DEFAULT 0x00000000 4057 #define smnBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL_DEFAULT 0x00000000 4058 4059 4060 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp 4061 #define smnBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID_DEFAULT 0x00000000 4062 #define smnBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID_DEFAULT 0x00000000 4063 #define smnBIF_CFG_DEV0_EPF0_VF2_COMMAND_DEFAULT 0x00000000 4064 #define smnBIF_CFG_DEV0_EPF0_VF2_STATUS_DEFAULT 0x00000000 4065 #define smnBIF_CFG_DEV0_EPF0_VF2_REVISION_ID_DEFAULT 0x00000000 4066 #define smnBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE_DEFAULT 0x00000000 4067 #define smnBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS_DEFAULT 0x00000000 4068 #define smnBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS_DEFAULT 0x00000000 4069 #define smnBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE_DEFAULT 0x00000000 4070 #define smnBIF_CFG_DEV0_EPF0_VF2_LATENCY_DEFAULT 0x00000000 4071 #define smnBIF_CFG_DEV0_EPF0_VF2_HEADER_DEFAULT 0x00000000 4072 #define smnBIF_CFG_DEV0_EPF0_VF2_BIST_DEFAULT 0x00000000 4073 #define smnBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1_DEFAULT 0x00000000 4074 #define smnBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2_DEFAULT 0x00000000 4075 #define smnBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3_DEFAULT 0x00000000 4076 #define smnBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4_DEFAULT 0x00000000 4077 #define smnBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5_DEFAULT 0x00000000 4078 #define smnBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6_DEFAULT 0x00000000 4079 #define smnBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR_DEFAULT 0x00000000 4080 #define smnBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID_DEFAULT 0x73101002 4081 #define smnBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR_DEFAULT 0x00000000 4082 #define smnBIF_CFG_DEV0_EPF0_VF2_CAP_PTR_DEFAULT 0x00000048 4083 #define smnBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE_DEFAULT 0x00000000 4084 #define smnBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN_DEFAULT 0x00000000 4085 #define smnBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT_DEFAULT 0x00000000 4086 #define smnBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY_DEFAULT 0x00000000 4087 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST_DEFAULT 0x0000a000 4088 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_DEFAULT 0x00000002 4089 #define smnBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP_DEFAULT 0x00000000 4090 #define smnBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL_DEFAULT 0x00000000 4091 #define smnBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS_DEFAULT 0x00000000 4092 #define smnBIF_CFG_DEV0_EPF0_VF2_LINK_CAP_DEFAULT 0x00000d04 4093 #define smnBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL_DEFAULT 0x00000000 4094 #define smnBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS_DEFAULT 0x00000000 4095 #define smnBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2_DEFAULT 0x00010000 4096 #define smnBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2_DEFAULT 0x00000000 4097 #define smnBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2_DEFAULT 0x00000000 4098 #define smnBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2_DEFAULT 0x0000001e 4099 #define smnBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2_DEFAULT 0x00000000 4100 #define smnBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2_DEFAULT 0x00000000 4101 #define smnBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST_DEFAULT 0x0000c000 4102 #define smnBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL_DEFAULT 0x00000082 4103 #define smnBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 4104 #define smnBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 4105 #define smnBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_DEFAULT 0x00000000 4106 #define smnBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_DEFAULT 0x00000000 4107 #define smnBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64_DEFAULT 0x00000000 4108 #define smnBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64_DEFAULT 0x00000000 4109 #define smnBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_DEFAULT 0x00000000 4110 #define smnBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64_DEFAULT 0x00000000 4111 #define smnBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST_DEFAULT 0x00000000 4112 #define smnBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL_DEFAULT 0x00000000 4113 #define smnBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE_DEFAULT 0x00000000 4114 #define smnBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA_DEFAULT 0x00000000 4115 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 4116 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 4117 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 4118 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 4119 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 4120 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 4121 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 4122 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 4123 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 4124 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 4125 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 4126 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0_DEFAULT 0x00000000 4127 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1_DEFAULT 0x00000000 4128 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2_DEFAULT 0x00000000 4129 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3_DEFAULT 0x00000000 4130 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 4131 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 4132 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 4133 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 4134 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 4135 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP_DEFAULT 0x00000000 4136 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL_DEFAULT 0x00000000 4137 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 4138 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP_DEFAULT 0x00000000 4139 #define smnBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL_DEFAULT 0x00000000 4140 4141 4142 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp 4143 #define smnBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID_DEFAULT 0x00000000 4144 #define smnBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID_DEFAULT 0x00000000 4145 #define smnBIF_CFG_DEV0_EPF0_VF3_COMMAND_DEFAULT 0x00000000 4146 #define smnBIF_CFG_DEV0_EPF0_VF3_STATUS_DEFAULT 0x00000000 4147 #define smnBIF_CFG_DEV0_EPF0_VF3_REVISION_ID_DEFAULT 0x00000000 4148 #define smnBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE_DEFAULT 0x00000000 4149 #define smnBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS_DEFAULT 0x00000000 4150 #define smnBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS_DEFAULT 0x00000000 4151 #define smnBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE_DEFAULT 0x00000000 4152 #define smnBIF_CFG_DEV0_EPF0_VF3_LATENCY_DEFAULT 0x00000000 4153 #define smnBIF_CFG_DEV0_EPF0_VF3_HEADER_DEFAULT 0x00000000 4154 #define smnBIF_CFG_DEV0_EPF0_VF3_BIST_DEFAULT 0x00000000 4155 #define smnBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1_DEFAULT 0x00000000 4156 #define smnBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2_DEFAULT 0x00000000 4157 #define smnBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3_DEFAULT 0x00000000 4158 #define smnBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4_DEFAULT 0x00000000 4159 #define smnBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5_DEFAULT 0x00000000 4160 #define smnBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6_DEFAULT 0x00000000 4161 #define smnBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR_DEFAULT 0x00000000 4162 #define smnBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID_DEFAULT 0x73101002 4163 #define smnBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR_DEFAULT 0x00000000 4164 #define smnBIF_CFG_DEV0_EPF0_VF3_CAP_PTR_DEFAULT 0x00000048 4165 #define smnBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE_DEFAULT 0x00000000 4166 #define smnBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN_DEFAULT 0x00000000 4167 #define smnBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT_DEFAULT 0x00000000 4168 #define smnBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY_DEFAULT 0x00000000 4169 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST_DEFAULT 0x0000a000 4170 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_DEFAULT 0x00000002 4171 #define smnBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP_DEFAULT 0x00000000 4172 #define smnBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL_DEFAULT 0x00000000 4173 #define smnBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS_DEFAULT 0x00000000 4174 #define smnBIF_CFG_DEV0_EPF0_VF3_LINK_CAP_DEFAULT 0x00000d04 4175 #define smnBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL_DEFAULT 0x00000000 4176 #define smnBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS_DEFAULT 0x00000000 4177 #define smnBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2_DEFAULT 0x00010000 4178 #define smnBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2_DEFAULT 0x00000000 4179 #define smnBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2_DEFAULT 0x00000000 4180 #define smnBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2_DEFAULT 0x0000001e 4181 #define smnBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2_DEFAULT 0x00000000 4182 #define smnBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2_DEFAULT 0x00000000 4183 #define smnBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST_DEFAULT 0x0000c000 4184 #define smnBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL_DEFAULT 0x00000082 4185 #define smnBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 4186 #define smnBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 4187 #define smnBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_DEFAULT 0x00000000 4188 #define smnBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_DEFAULT 0x00000000 4189 #define smnBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64_DEFAULT 0x00000000 4190 #define smnBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64_DEFAULT 0x00000000 4191 #define smnBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_DEFAULT 0x00000000 4192 #define smnBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64_DEFAULT 0x00000000 4193 #define smnBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST_DEFAULT 0x00000000 4194 #define smnBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL_DEFAULT 0x00000000 4195 #define smnBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE_DEFAULT 0x00000000 4196 #define smnBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA_DEFAULT 0x00000000 4197 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 4198 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 4199 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 4200 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 4201 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 4202 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 4203 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 4204 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 4205 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 4206 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 4207 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 4208 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0_DEFAULT 0x00000000 4209 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1_DEFAULT 0x00000000 4210 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2_DEFAULT 0x00000000 4211 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3_DEFAULT 0x00000000 4212 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 4213 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 4214 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 4215 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 4216 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 4217 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP_DEFAULT 0x00000000 4218 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL_DEFAULT 0x00000000 4219 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 4220 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP_DEFAULT 0x00000000 4221 #define smnBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL_DEFAULT 0x00000000 4222 4223 4224 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp 4225 #define smnBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID_DEFAULT 0x00000000 4226 #define smnBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID_DEFAULT 0x00000000 4227 #define smnBIF_CFG_DEV0_EPF0_VF4_COMMAND_DEFAULT 0x00000000 4228 #define smnBIF_CFG_DEV0_EPF0_VF4_STATUS_DEFAULT 0x00000000 4229 #define smnBIF_CFG_DEV0_EPF0_VF4_REVISION_ID_DEFAULT 0x00000000 4230 #define smnBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE_DEFAULT 0x00000000 4231 #define smnBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS_DEFAULT 0x00000000 4232 #define smnBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS_DEFAULT 0x00000000 4233 #define smnBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE_DEFAULT 0x00000000 4234 #define smnBIF_CFG_DEV0_EPF0_VF4_LATENCY_DEFAULT 0x00000000 4235 #define smnBIF_CFG_DEV0_EPF0_VF4_HEADER_DEFAULT 0x00000000 4236 #define smnBIF_CFG_DEV0_EPF0_VF4_BIST_DEFAULT 0x00000000 4237 #define smnBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1_DEFAULT 0x00000000 4238 #define smnBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2_DEFAULT 0x00000000 4239 #define smnBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3_DEFAULT 0x00000000 4240 #define smnBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4_DEFAULT 0x00000000 4241 #define smnBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5_DEFAULT 0x00000000 4242 #define smnBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6_DEFAULT 0x00000000 4243 #define smnBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR_DEFAULT 0x00000000 4244 #define smnBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID_DEFAULT 0x73101002 4245 #define smnBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR_DEFAULT 0x00000000 4246 #define smnBIF_CFG_DEV0_EPF0_VF4_CAP_PTR_DEFAULT 0x00000048 4247 #define smnBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE_DEFAULT 0x00000000 4248 #define smnBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN_DEFAULT 0x00000000 4249 #define smnBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT_DEFAULT 0x00000000 4250 #define smnBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY_DEFAULT 0x00000000 4251 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST_DEFAULT 0x0000a000 4252 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_DEFAULT 0x00000002 4253 #define smnBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP_DEFAULT 0x00000000 4254 #define smnBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL_DEFAULT 0x00000000 4255 #define smnBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS_DEFAULT 0x00000000 4256 #define smnBIF_CFG_DEV0_EPF0_VF4_LINK_CAP_DEFAULT 0x00000d04 4257 #define smnBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL_DEFAULT 0x00000000 4258 #define smnBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS_DEFAULT 0x00000000 4259 #define smnBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2_DEFAULT 0x00010000 4260 #define smnBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2_DEFAULT 0x00000000 4261 #define smnBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2_DEFAULT 0x00000000 4262 #define smnBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2_DEFAULT 0x0000001e 4263 #define smnBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2_DEFAULT 0x00000000 4264 #define smnBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2_DEFAULT 0x00000000 4265 #define smnBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST_DEFAULT 0x0000c000 4266 #define smnBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL_DEFAULT 0x00000082 4267 #define smnBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 4268 #define smnBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 4269 #define smnBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_DEFAULT 0x00000000 4270 #define smnBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_DEFAULT 0x00000000 4271 #define smnBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64_DEFAULT 0x00000000 4272 #define smnBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64_DEFAULT 0x00000000 4273 #define smnBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_DEFAULT 0x00000000 4274 #define smnBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64_DEFAULT 0x00000000 4275 #define smnBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST_DEFAULT 0x00000000 4276 #define smnBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL_DEFAULT 0x00000000 4277 #define smnBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE_DEFAULT 0x00000000 4278 #define smnBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA_DEFAULT 0x00000000 4279 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 4280 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 4281 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 4282 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 4283 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 4284 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 4285 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 4286 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 4287 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 4288 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 4289 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 4290 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0_DEFAULT 0x00000000 4291 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1_DEFAULT 0x00000000 4292 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2_DEFAULT 0x00000000 4293 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3_DEFAULT 0x00000000 4294 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 4295 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 4296 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 4297 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 4298 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 4299 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP_DEFAULT 0x00000000 4300 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL_DEFAULT 0x00000000 4301 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 4302 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP_DEFAULT 0x00000000 4303 #define smnBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL_DEFAULT 0x00000000 4304 4305 4306 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp 4307 #define smnBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID_DEFAULT 0x00000000 4308 #define smnBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID_DEFAULT 0x00000000 4309 #define smnBIF_CFG_DEV0_EPF0_VF5_COMMAND_DEFAULT 0x00000000 4310 #define smnBIF_CFG_DEV0_EPF0_VF5_STATUS_DEFAULT 0x00000000 4311 #define smnBIF_CFG_DEV0_EPF0_VF5_REVISION_ID_DEFAULT 0x00000000 4312 #define smnBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE_DEFAULT 0x00000000 4313 #define smnBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS_DEFAULT 0x00000000 4314 #define smnBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS_DEFAULT 0x00000000 4315 #define smnBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE_DEFAULT 0x00000000 4316 #define smnBIF_CFG_DEV0_EPF0_VF5_LATENCY_DEFAULT 0x00000000 4317 #define smnBIF_CFG_DEV0_EPF0_VF5_HEADER_DEFAULT 0x00000000 4318 #define smnBIF_CFG_DEV0_EPF0_VF5_BIST_DEFAULT 0x00000000 4319 #define smnBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1_DEFAULT 0x00000000 4320 #define smnBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2_DEFAULT 0x00000000 4321 #define smnBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3_DEFAULT 0x00000000 4322 #define smnBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4_DEFAULT 0x00000000 4323 #define smnBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5_DEFAULT 0x00000000 4324 #define smnBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6_DEFAULT 0x00000000 4325 #define smnBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR_DEFAULT 0x00000000 4326 #define smnBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID_DEFAULT 0x73101002 4327 #define smnBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR_DEFAULT 0x00000000 4328 #define smnBIF_CFG_DEV0_EPF0_VF5_CAP_PTR_DEFAULT 0x00000048 4329 #define smnBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE_DEFAULT 0x00000000 4330 #define smnBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN_DEFAULT 0x00000000 4331 #define smnBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT_DEFAULT 0x00000000 4332 #define smnBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY_DEFAULT 0x00000000 4333 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST_DEFAULT 0x0000a000 4334 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_DEFAULT 0x00000002 4335 #define smnBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP_DEFAULT 0x00000000 4336 #define smnBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL_DEFAULT 0x00000000 4337 #define smnBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS_DEFAULT 0x00000000 4338 #define smnBIF_CFG_DEV0_EPF0_VF5_LINK_CAP_DEFAULT 0x00000d04 4339 #define smnBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL_DEFAULT 0x00000000 4340 #define smnBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS_DEFAULT 0x00000000 4341 #define smnBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2_DEFAULT 0x00010000 4342 #define smnBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2_DEFAULT 0x00000000 4343 #define smnBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2_DEFAULT 0x00000000 4344 #define smnBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2_DEFAULT 0x0000001e 4345 #define smnBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2_DEFAULT 0x00000000 4346 #define smnBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2_DEFAULT 0x00000000 4347 #define smnBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST_DEFAULT 0x0000c000 4348 #define smnBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL_DEFAULT 0x00000082 4349 #define smnBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 4350 #define smnBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 4351 #define smnBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_DEFAULT 0x00000000 4352 #define smnBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_DEFAULT 0x00000000 4353 #define smnBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64_DEFAULT 0x00000000 4354 #define smnBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64_DEFAULT 0x00000000 4355 #define smnBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_DEFAULT 0x00000000 4356 #define smnBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64_DEFAULT 0x00000000 4357 #define smnBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST_DEFAULT 0x00000000 4358 #define smnBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL_DEFAULT 0x00000000 4359 #define smnBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE_DEFAULT 0x00000000 4360 #define smnBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA_DEFAULT 0x00000000 4361 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 4362 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 4363 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 4364 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 4365 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 4366 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 4367 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 4368 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 4369 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 4370 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 4371 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 4372 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0_DEFAULT 0x00000000 4373 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1_DEFAULT 0x00000000 4374 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2_DEFAULT 0x00000000 4375 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3_DEFAULT 0x00000000 4376 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 4377 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 4378 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 4379 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 4380 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 4381 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP_DEFAULT 0x00000000 4382 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL_DEFAULT 0x00000000 4383 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 4384 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP_DEFAULT 0x00000000 4385 #define smnBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL_DEFAULT 0x00000000 4386 4387 4388 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp 4389 #define smnBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID_DEFAULT 0x00000000 4390 #define smnBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID_DEFAULT 0x00000000 4391 #define smnBIF_CFG_DEV0_EPF0_VF6_COMMAND_DEFAULT 0x00000000 4392 #define smnBIF_CFG_DEV0_EPF0_VF6_STATUS_DEFAULT 0x00000000 4393 #define smnBIF_CFG_DEV0_EPF0_VF6_REVISION_ID_DEFAULT 0x00000000 4394 #define smnBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE_DEFAULT 0x00000000 4395 #define smnBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS_DEFAULT 0x00000000 4396 #define smnBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS_DEFAULT 0x00000000 4397 #define smnBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE_DEFAULT 0x00000000 4398 #define smnBIF_CFG_DEV0_EPF0_VF6_LATENCY_DEFAULT 0x00000000 4399 #define smnBIF_CFG_DEV0_EPF0_VF6_HEADER_DEFAULT 0x00000000 4400 #define smnBIF_CFG_DEV0_EPF0_VF6_BIST_DEFAULT 0x00000000 4401 #define smnBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1_DEFAULT 0x00000000 4402 #define smnBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2_DEFAULT 0x00000000 4403 #define smnBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3_DEFAULT 0x00000000 4404 #define smnBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4_DEFAULT 0x00000000 4405 #define smnBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5_DEFAULT 0x00000000 4406 #define smnBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6_DEFAULT 0x00000000 4407 #define smnBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR_DEFAULT 0x00000000 4408 #define smnBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID_DEFAULT 0x73101002 4409 #define smnBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR_DEFAULT 0x00000000 4410 #define smnBIF_CFG_DEV0_EPF0_VF6_CAP_PTR_DEFAULT 0x00000048 4411 #define smnBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE_DEFAULT 0x00000000 4412 #define smnBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN_DEFAULT 0x00000000 4413 #define smnBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT_DEFAULT 0x00000000 4414 #define smnBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY_DEFAULT 0x00000000 4415 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST_DEFAULT 0x0000a000 4416 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_DEFAULT 0x00000002 4417 #define smnBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP_DEFAULT 0x00000000 4418 #define smnBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL_DEFAULT 0x00000000 4419 #define smnBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS_DEFAULT 0x00000000 4420 #define smnBIF_CFG_DEV0_EPF0_VF6_LINK_CAP_DEFAULT 0x00000d04 4421 #define smnBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL_DEFAULT 0x00000000 4422 #define smnBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS_DEFAULT 0x00000000 4423 #define smnBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2_DEFAULT 0x00010000 4424 #define smnBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2_DEFAULT 0x00000000 4425 #define smnBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2_DEFAULT 0x00000000 4426 #define smnBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2_DEFAULT 0x0000001e 4427 #define smnBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2_DEFAULT 0x00000000 4428 #define smnBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2_DEFAULT 0x00000000 4429 #define smnBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST_DEFAULT 0x0000c000 4430 #define smnBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL_DEFAULT 0x00000082 4431 #define smnBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 4432 #define smnBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 4433 #define smnBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_DEFAULT 0x00000000 4434 #define smnBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_DEFAULT 0x00000000 4435 #define smnBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64_DEFAULT 0x00000000 4436 #define smnBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64_DEFAULT 0x00000000 4437 #define smnBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_DEFAULT 0x00000000 4438 #define smnBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64_DEFAULT 0x00000000 4439 #define smnBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST_DEFAULT 0x00000000 4440 #define smnBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL_DEFAULT 0x00000000 4441 #define smnBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE_DEFAULT 0x00000000 4442 #define smnBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA_DEFAULT 0x00000000 4443 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 4444 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 4445 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 4446 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 4447 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 4448 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 4449 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 4450 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 4451 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 4452 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 4453 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 4454 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0_DEFAULT 0x00000000 4455 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1_DEFAULT 0x00000000 4456 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2_DEFAULT 0x00000000 4457 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3_DEFAULT 0x00000000 4458 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 4459 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 4460 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 4461 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 4462 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 4463 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP_DEFAULT 0x00000000 4464 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL_DEFAULT 0x00000000 4465 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 4466 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP_DEFAULT 0x00000000 4467 #define smnBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL_DEFAULT 0x00000000 4468 4469 4470 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp 4471 #define smnBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID_DEFAULT 0x00000000 4472 #define smnBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID_DEFAULT 0x00000000 4473 #define smnBIF_CFG_DEV0_EPF0_VF7_COMMAND_DEFAULT 0x00000000 4474 #define smnBIF_CFG_DEV0_EPF0_VF7_STATUS_DEFAULT 0x00000000 4475 #define smnBIF_CFG_DEV0_EPF0_VF7_REVISION_ID_DEFAULT 0x00000000 4476 #define smnBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE_DEFAULT 0x00000000 4477 #define smnBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS_DEFAULT 0x00000000 4478 #define smnBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS_DEFAULT 0x00000000 4479 #define smnBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE_DEFAULT 0x00000000 4480 #define smnBIF_CFG_DEV0_EPF0_VF7_LATENCY_DEFAULT 0x00000000 4481 #define smnBIF_CFG_DEV0_EPF0_VF7_HEADER_DEFAULT 0x00000000 4482 #define smnBIF_CFG_DEV0_EPF0_VF7_BIST_DEFAULT 0x00000000 4483 #define smnBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1_DEFAULT 0x00000000 4484 #define smnBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2_DEFAULT 0x00000000 4485 #define smnBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3_DEFAULT 0x00000000 4486 #define smnBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4_DEFAULT 0x00000000 4487 #define smnBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5_DEFAULT 0x00000000 4488 #define smnBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6_DEFAULT 0x00000000 4489 #define smnBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR_DEFAULT 0x00000000 4490 #define smnBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID_DEFAULT 0x73101002 4491 #define smnBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR_DEFAULT 0x00000000 4492 #define smnBIF_CFG_DEV0_EPF0_VF7_CAP_PTR_DEFAULT 0x00000048 4493 #define smnBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE_DEFAULT 0x00000000 4494 #define smnBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN_DEFAULT 0x00000000 4495 #define smnBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT_DEFAULT 0x00000000 4496 #define smnBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY_DEFAULT 0x00000000 4497 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST_DEFAULT 0x0000a000 4498 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_DEFAULT 0x00000002 4499 #define smnBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP_DEFAULT 0x00000000 4500 #define smnBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL_DEFAULT 0x00000000 4501 #define smnBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS_DEFAULT 0x00000000 4502 #define smnBIF_CFG_DEV0_EPF0_VF7_LINK_CAP_DEFAULT 0x00000d04 4503 #define smnBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL_DEFAULT 0x00000000 4504 #define smnBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS_DEFAULT 0x00000000 4505 #define smnBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2_DEFAULT 0x00010000 4506 #define smnBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2_DEFAULT 0x00000000 4507 #define smnBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2_DEFAULT 0x00000000 4508 #define smnBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2_DEFAULT 0x0000001e 4509 #define smnBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2_DEFAULT 0x00000000 4510 #define smnBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2_DEFAULT 0x00000000 4511 #define smnBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST_DEFAULT 0x0000c000 4512 #define smnBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL_DEFAULT 0x00000082 4513 #define smnBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 4514 #define smnBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 4515 #define smnBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_DEFAULT 0x00000000 4516 #define smnBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_DEFAULT 0x00000000 4517 #define smnBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64_DEFAULT 0x00000000 4518 #define smnBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64_DEFAULT 0x00000000 4519 #define smnBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_DEFAULT 0x00000000 4520 #define smnBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64_DEFAULT 0x00000000 4521 #define smnBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST_DEFAULT 0x00000000 4522 #define smnBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL_DEFAULT 0x00000000 4523 #define smnBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE_DEFAULT 0x00000000 4524 #define smnBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA_DEFAULT 0x00000000 4525 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 4526 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 4527 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 4528 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 4529 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 4530 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 4531 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 4532 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 4533 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 4534 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 4535 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 4536 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0_DEFAULT 0x00000000 4537 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1_DEFAULT 0x00000000 4538 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2_DEFAULT 0x00000000 4539 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3_DEFAULT 0x00000000 4540 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 4541 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 4542 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 4543 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 4544 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 4545 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP_DEFAULT 0x00000000 4546 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL_DEFAULT 0x00000000 4547 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 4548 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP_DEFAULT 0x00000000 4549 #define smnBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL_DEFAULT 0x00000000 4550 4551 4552 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp 4553 #define smnBIF_CFG_DEV0_EPF0_VF8_VENDOR_ID_DEFAULT 0x00000000 4554 #define smnBIF_CFG_DEV0_EPF0_VF8_DEVICE_ID_DEFAULT 0x00000000 4555 #define smnBIF_CFG_DEV0_EPF0_VF8_COMMAND_DEFAULT 0x00000000 4556 #define smnBIF_CFG_DEV0_EPF0_VF8_STATUS_DEFAULT 0x00000000 4557 #define smnBIF_CFG_DEV0_EPF0_VF8_REVISION_ID_DEFAULT 0x00000000 4558 #define smnBIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE_DEFAULT 0x00000000 4559 #define smnBIF_CFG_DEV0_EPF0_VF8_SUB_CLASS_DEFAULT 0x00000000 4560 #define smnBIF_CFG_DEV0_EPF0_VF8_BASE_CLASS_DEFAULT 0x00000000 4561 #define smnBIF_CFG_DEV0_EPF0_VF8_CACHE_LINE_DEFAULT 0x00000000 4562 #define smnBIF_CFG_DEV0_EPF0_VF8_LATENCY_DEFAULT 0x00000000 4563 #define smnBIF_CFG_DEV0_EPF0_VF8_HEADER_DEFAULT 0x00000000 4564 #define smnBIF_CFG_DEV0_EPF0_VF8_BIST_DEFAULT 0x00000000 4565 #define smnBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1_DEFAULT 0x00000000 4566 #define smnBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2_DEFAULT 0x00000000 4567 #define smnBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3_DEFAULT 0x00000000 4568 #define smnBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4_DEFAULT 0x00000000 4569 #define smnBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5_DEFAULT 0x00000000 4570 #define smnBIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6_DEFAULT 0x00000000 4571 #define smnBIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR_DEFAULT 0x00000000 4572 #define smnBIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID_DEFAULT 0x73101002 4573 #define smnBIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR_DEFAULT 0x00000000 4574 #define smnBIF_CFG_DEV0_EPF0_VF8_CAP_PTR_DEFAULT 0x00000048 4575 #define smnBIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE_DEFAULT 0x00000000 4576 #define smnBIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN_DEFAULT 0x00000000 4577 #define smnBIF_CFG_DEV0_EPF0_VF8_MIN_GRANT_DEFAULT 0x00000000 4578 #define smnBIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY_DEFAULT 0x00000000 4579 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST_DEFAULT 0x0000a000 4580 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_DEFAULT 0x00000002 4581 #define smnBIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP_DEFAULT 0x00000000 4582 #define smnBIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL_DEFAULT 0x00000000 4583 #define smnBIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS_DEFAULT 0x00000000 4584 #define smnBIF_CFG_DEV0_EPF0_VF8_LINK_CAP_DEFAULT 0x00000d04 4585 #define smnBIF_CFG_DEV0_EPF0_VF8_LINK_CNTL_DEFAULT 0x00000000 4586 #define smnBIF_CFG_DEV0_EPF0_VF8_LINK_STATUS_DEFAULT 0x00000000 4587 #define smnBIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2_DEFAULT 0x00010000 4588 #define smnBIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2_DEFAULT 0x00000000 4589 #define smnBIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2_DEFAULT 0x00000000 4590 #define smnBIF_CFG_DEV0_EPF0_VF8_LINK_CAP2_DEFAULT 0x0000001e 4591 #define smnBIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2_DEFAULT 0x00000000 4592 #define smnBIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2_DEFAULT 0x00000000 4593 #define smnBIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST_DEFAULT 0x0000c000 4594 #define smnBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL_DEFAULT 0x00000082 4595 #define smnBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 4596 #define smnBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 4597 #define smnBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_DEFAULT 0x00000000 4598 #define smnBIF_CFG_DEV0_EPF0_VF8_MSI_MASK_DEFAULT 0x00000000 4599 #define smnBIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64_DEFAULT 0x00000000 4600 #define smnBIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64_DEFAULT 0x00000000 4601 #define smnBIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_DEFAULT 0x00000000 4602 #define smnBIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64_DEFAULT 0x00000000 4603 #define smnBIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST_DEFAULT 0x00000000 4604 #define smnBIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL_DEFAULT 0x00000000 4605 #define smnBIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE_DEFAULT 0x00000000 4606 #define smnBIF_CFG_DEV0_EPF0_VF8_MSIX_PBA_DEFAULT 0x00000000 4607 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 4608 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 4609 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 4610 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 4611 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 4612 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 4613 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 4614 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 4615 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 4616 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 4617 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 4618 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0_DEFAULT 0x00000000 4619 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1_DEFAULT 0x00000000 4620 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2_DEFAULT 0x00000000 4621 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3_DEFAULT 0x00000000 4622 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 4623 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 4624 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 4625 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 4626 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 4627 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CAP_DEFAULT 0x00000000 4628 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CNTL_DEFAULT 0x00000000 4629 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 4630 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP_DEFAULT 0x00000000 4631 #define smnBIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL_DEFAULT 0x00000000 4632 4633 4634 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp 4635 #define smnBIF_CFG_DEV0_EPF0_VF9_VENDOR_ID_DEFAULT 0x00000000 4636 #define smnBIF_CFG_DEV0_EPF0_VF9_DEVICE_ID_DEFAULT 0x00000000 4637 #define smnBIF_CFG_DEV0_EPF0_VF9_COMMAND_DEFAULT 0x00000000 4638 #define smnBIF_CFG_DEV0_EPF0_VF9_STATUS_DEFAULT 0x00000000 4639 #define smnBIF_CFG_DEV0_EPF0_VF9_REVISION_ID_DEFAULT 0x00000000 4640 #define smnBIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE_DEFAULT 0x00000000 4641 #define smnBIF_CFG_DEV0_EPF0_VF9_SUB_CLASS_DEFAULT 0x00000000 4642 #define smnBIF_CFG_DEV0_EPF0_VF9_BASE_CLASS_DEFAULT 0x00000000 4643 #define smnBIF_CFG_DEV0_EPF0_VF9_CACHE_LINE_DEFAULT 0x00000000 4644 #define smnBIF_CFG_DEV0_EPF0_VF9_LATENCY_DEFAULT 0x00000000 4645 #define smnBIF_CFG_DEV0_EPF0_VF9_HEADER_DEFAULT 0x00000000 4646 #define smnBIF_CFG_DEV0_EPF0_VF9_BIST_DEFAULT 0x00000000 4647 #define smnBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1_DEFAULT 0x00000000 4648 #define smnBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2_DEFAULT 0x00000000 4649 #define smnBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3_DEFAULT 0x00000000 4650 #define smnBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4_DEFAULT 0x00000000 4651 #define smnBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5_DEFAULT 0x00000000 4652 #define smnBIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6_DEFAULT 0x00000000 4653 #define smnBIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR_DEFAULT 0x00000000 4654 #define smnBIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID_DEFAULT 0x73101002 4655 #define smnBIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR_DEFAULT 0x00000000 4656 #define smnBIF_CFG_DEV0_EPF0_VF9_CAP_PTR_DEFAULT 0x00000048 4657 #define smnBIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE_DEFAULT 0x00000000 4658 #define smnBIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN_DEFAULT 0x00000000 4659 #define smnBIF_CFG_DEV0_EPF0_VF9_MIN_GRANT_DEFAULT 0x00000000 4660 #define smnBIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY_DEFAULT 0x00000000 4661 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST_DEFAULT 0x0000a000 4662 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_DEFAULT 0x00000002 4663 #define smnBIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP_DEFAULT 0x00000000 4664 #define smnBIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL_DEFAULT 0x00000000 4665 #define smnBIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS_DEFAULT 0x00000000 4666 #define smnBIF_CFG_DEV0_EPF0_VF9_LINK_CAP_DEFAULT 0x00000d04 4667 #define smnBIF_CFG_DEV0_EPF0_VF9_LINK_CNTL_DEFAULT 0x00000000 4668 #define smnBIF_CFG_DEV0_EPF0_VF9_LINK_STATUS_DEFAULT 0x00000000 4669 #define smnBIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2_DEFAULT 0x00010000 4670 #define smnBIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2_DEFAULT 0x00000000 4671 #define smnBIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2_DEFAULT 0x00000000 4672 #define smnBIF_CFG_DEV0_EPF0_VF9_LINK_CAP2_DEFAULT 0x0000001e 4673 #define smnBIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2_DEFAULT 0x00000000 4674 #define smnBIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2_DEFAULT 0x00000000 4675 #define smnBIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST_DEFAULT 0x0000c000 4676 #define smnBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL_DEFAULT 0x00000082 4677 #define smnBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 4678 #define smnBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 4679 #define smnBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_DEFAULT 0x00000000 4680 #define smnBIF_CFG_DEV0_EPF0_VF9_MSI_MASK_DEFAULT 0x00000000 4681 #define smnBIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64_DEFAULT 0x00000000 4682 #define smnBIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64_DEFAULT 0x00000000 4683 #define smnBIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_DEFAULT 0x00000000 4684 #define smnBIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64_DEFAULT 0x00000000 4685 #define smnBIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST_DEFAULT 0x00000000 4686 #define smnBIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL_DEFAULT 0x00000000 4687 #define smnBIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE_DEFAULT 0x00000000 4688 #define smnBIF_CFG_DEV0_EPF0_VF9_MSIX_PBA_DEFAULT 0x00000000 4689 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 4690 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 4691 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 4692 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 4693 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 4694 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 4695 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 4696 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 4697 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 4698 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 4699 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 4700 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0_DEFAULT 0x00000000 4701 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1_DEFAULT 0x00000000 4702 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2_DEFAULT 0x00000000 4703 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3_DEFAULT 0x00000000 4704 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 4705 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 4706 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 4707 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 4708 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 4709 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CAP_DEFAULT 0x00000000 4710 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CNTL_DEFAULT 0x00000000 4711 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 4712 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP_DEFAULT 0x00000000 4713 #define smnBIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL_DEFAULT 0x00000000 4714 4715 4716 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp 4717 #define smnBIF_CFG_DEV0_EPF0_VF10_VENDOR_ID_DEFAULT 0x00000000 4718 #define smnBIF_CFG_DEV0_EPF0_VF10_DEVICE_ID_DEFAULT 0x00000000 4719 #define smnBIF_CFG_DEV0_EPF0_VF10_COMMAND_DEFAULT 0x00000000 4720 #define smnBIF_CFG_DEV0_EPF0_VF10_STATUS_DEFAULT 0x00000000 4721 #define smnBIF_CFG_DEV0_EPF0_VF10_REVISION_ID_DEFAULT 0x00000000 4722 #define smnBIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE_DEFAULT 0x00000000 4723 #define smnBIF_CFG_DEV0_EPF0_VF10_SUB_CLASS_DEFAULT 0x00000000 4724 #define smnBIF_CFG_DEV0_EPF0_VF10_BASE_CLASS_DEFAULT 0x00000000 4725 #define smnBIF_CFG_DEV0_EPF0_VF10_CACHE_LINE_DEFAULT 0x00000000 4726 #define smnBIF_CFG_DEV0_EPF0_VF10_LATENCY_DEFAULT 0x00000000 4727 #define smnBIF_CFG_DEV0_EPF0_VF10_HEADER_DEFAULT 0x00000000 4728 #define smnBIF_CFG_DEV0_EPF0_VF10_BIST_DEFAULT 0x00000000 4729 #define smnBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1_DEFAULT 0x00000000 4730 #define smnBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2_DEFAULT 0x00000000 4731 #define smnBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3_DEFAULT 0x00000000 4732 #define smnBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4_DEFAULT 0x00000000 4733 #define smnBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5_DEFAULT 0x00000000 4734 #define smnBIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6_DEFAULT 0x00000000 4735 #define smnBIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR_DEFAULT 0x00000000 4736 #define smnBIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID_DEFAULT 0x73101002 4737 #define smnBIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR_DEFAULT 0x00000000 4738 #define smnBIF_CFG_DEV0_EPF0_VF10_CAP_PTR_DEFAULT 0x00000048 4739 #define smnBIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE_DEFAULT 0x00000000 4740 #define smnBIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN_DEFAULT 0x00000000 4741 #define smnBIF_CFG_DEV0_EPF0_VF10_MIN_GRANT_DEFAULT 0x00000000 4742 #define smnBIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY_DEFAULT 0x00000000 4743 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST_DEFAULT 0x0000a000 4744 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_DEFAULT 0x00000002 4745 #define smnBIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP_DEFAULT 0x00000000 4746 #define smnBIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL_DEFAULT 0x00000000 4747 #define smnBIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS_DEFAULT 0x00000000 4748 #define smnBIF_CFG_DEV0_EPF0_VF10_LINK_CAP_DEFAULT 0x00000d04 4749 #define smnBIF_CFG_DEV0_EPF0_VF10_LINK_CNTL_DEFAULT 0x00000000 4750 #define smnBIF_CFG_DEV0_EPF0_VF10_LINK_STATUS_DEFAULT 0x00000000 4751 #define smnBIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2_DEFAULT 0x00010000 4752 #define smnBIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2_DEFAULT 0x00000000 4753 #define smnBIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2_DEFAULT 0x00000000 4754 #define smnBIF_CFG_DEV0_EPF0_VF10_LINK_CAP2_DEFAULT 0x0000001e 4755 #define smnBIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2_DEFAULT 0x00000000 4756 #define smnBIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2_DEFAULT 0x00000000 4757 #define smnBIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST_DEFAULT 0x0000c000 4758 #define smnBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL_DEFAULT 0x00000082 4759 #define smnBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 4760 #define smnBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 4761 #define smnBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_DEFAULT 0x00000000 4762 #define smnBIF_CFG_DEV0_EPF0_VF10_MSI_MASK_DEFAULT 0x00000000 4763 #define smnBIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64_DEFAULT 0x00000000 4764 #define smnBIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64_DEFAULT 0x00000000 4765 #define smnBIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_DEFAULT 0x00000000 4766 #define smnBIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64_DEFAULT 0x00000000 4767 #define smnBIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST_DEFAULT 0x00000000 4768 #define smnBIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL_DEFAULT 0x00000000 4769 #define smnBIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE_DEFAULT 0x00000000 4770 #define smnBIF_CFG_DEV0_EPF0_VF10_MSIX_PBA_DEFAULT 0x00000000 4771 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 4772 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 4773 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 4774 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 4775 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 4776 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 4777 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 4778 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 4779 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 4780 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 4781 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 4782 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0_DEFAULT 0x00000000 4783 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1_DEFAULT 0x00000000 4784 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2_DEFAULT 0x00000000 4785 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3_DEFAULT 0x00000000 4786 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 4787 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 4788 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 4789 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 4790 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 4791 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CAP_DEFAULT 0x00000000 4792 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CNTL_DEFAULT 0x00000000 4793 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 4794 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP_DEFAULT 0x00000000 4795 #define smnBIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL_DEFAULT 0x00000000 4796 4797 4798 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp 4799 #define smnBIF_CFG_DEV0_EPF0_VF11_VENDOR_ID_DEFAULT 0x00000000 4800 #define smnBIF_CFG_DEV0_EPF0_VF11_DEVICE_ID_DEFAULT 0x00000000 4801 #define smnBIF_CFG_DEV0_EPF0_VF11_COMMAND_DEFAULT 0x00000000 4802 #define smnBIF_CFG_DEV0_EPF0_VF11_STATUS_DEFAULT 0x00000000 4803 #define smnBIF_CFG_DEV0_EPF0_VF11_REVISION_ID_DEFAULT 0x00000000 4804 #define smnBIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE_DEFAULT 0x00000000 4805 #define smnBIF_CFG_DEV0_EPF0_VF11_SUB_CLASS_DEFAULT 0x00000000 4806 #define smnBIF_CFG_DEV0_EPF0_VF11_BASE_CLASS_DEFAULT 0x00000000 4807 #define smnBIF_CFG_DEV0_EPF0_VF11_CACHE_LINE_DEFAULT 0x00000000 4808 #define smnBIF_CFG_DEV0_EPF0_VF11_LATENCY_DEFAULT 0x00000000 4809 #define smnBIF_CFG_DEV0_EPF0_VF11_HEADER_DEFAULT 0x00000000 4810 #define smnBIF_CFG_DEV0_EPF0_VF11_BIST_DEFAULT 0x00000000 4811 #define smnBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1_DEFAULT 0x00000000 4812 #define smnBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2_DEFAULT 0x00000000 4813 #define smnBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3_DEFAULT 0x00000000 4814 #define smnBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4_DEFAULT 0x00000000 4815 #define smnBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5_DEFAULT 0x00000000 4816 #define smnBIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6_DEFAULT 0x00000000 4817 #define smnBIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR_DEFAULT 0x00000000 4818 #define smnBIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID_DEFAULT 0x73101002 4819 #define smnBIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR_DEFAULT 0x00000000 4820 #define smnBIF_CFG_DEV0_EPF0_VF11_CAP_PTR_DEFAULT 0x00000048 4821 #define smnBIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE_DEFAULT 0x00000000 4822 #define smnBIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN_DEFAULT 0x00000000 4823 #define smnBIF_CFG_DEV0_EPF0_VF11_MIN_GRANT_DEFAULT 0x00000000 4824 #define smnBIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY_DEFAULT 0x00000000 4825 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST_DEFAULT 0x0000a000 4826 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_DEFAULT 0x00000002 4827 #define smnBIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP_DEFAULT 0x00000000 4828 #define smnBIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL_DEFAULT 0x00000000 4829 #define smnBIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS_DEFAULT 0x00000000 4830 #define smnBIF_CFG_DEV0_EPF0_VF11_LINK_CAP_DEFAULT 0x00000d04 4831 #define smnBIF_CFG_DEV0_EPF0_VF11_LINK_CNTL_DEFAULT 0x00000000 4832 #define smnBIF_CFG_DEV0_EPF0_VF11_LINK_STATUS_DEFAULT 0x00000000 4833 #define smnBIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2_DEFAULT 0x00010000 4834 #define smnBIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2_DEFAULT 0x00000000 4835 #define smnBIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2_DEFAULT 0x00000000 4836 #define smnBIF_CFG_DEV0_EPF0_VF11_LINK_CAP2_DEFAULT 0x0000001e 4837 #define smnBIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2_DEFAULT 0x00000000 4838 #define smnBIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2_DEFAULT 0x00000000 4839 #define smnBIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST_DEFAULT 0x0000c000 4840 #define smnBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL_DEFAULT 0x00000082 4841 #define smnBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 4842 #define smnBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 4843 #define smnBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_DEFAULT 0x00000000 4844 #define smnBIF_CFG_DEV0_EPF0_VF11_MSI_MASK_DEFAULT 0x00000000 4845 #define smnBIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64_DEFAULT 0x00000000 4846 #define smnBIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64_DEFAULT 0x00000000 4847 #define smnBIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_DEFAULT 0x00000000 4848 #define smnBIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64_DEFAULT 0x00000000 4849 #define smnBIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST_DEFAULT 0x00000000 4850 #define smnBIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL_DEFAULT 0x00000000 4851 #define smnBIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE_DEFAULT 0x00000000 4852 #define smnBIF_CFG_DEV0_EPF0_VF11_MSIX_PBA_DEFAULT 0x00000000 4853 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 4854 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 4855 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 4856 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 4857 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 4858 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 4859 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 4860 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 4861 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 4862 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 4863 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 4864 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0_DEFAULT 0x00000000 4865 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1_DEFAULT 0x00000000 4866 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2_DEFAULT 0x00000000 4867 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3_DEFAULT 0x00000000 4868 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 4869 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 4870 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 4871 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 4872 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 4873 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CAP_DEFAULT 0x00000000 4874 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CNTL_DEFAULT 0x00000000 4875 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 4876 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP_DEFAULT 0x00000000 4877 #define smnBIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL_DEFAULT 0x00000000 4878 4879 4880 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp 4881 #define smnBIF_CFG_DEV0_EPF0_VF12_VENDOR_ID_DEFAULT 0x00000000 4882 #define smnBIF_CFG_DEV0_EPF0_VF12_DEVICE_ID_DEFAULT 0x00000000 4883 #define smnBIF_CFG_DEV0_EPF0_VF12_COMMAND_DEFAULT 0x00000000 4884 #define smnBIF_CFG_DEV0_EPF0_VF12_STATUS_DEFAULT 0x00000000 4885 #define smnBIF_CFG_DEV0_EPF0_VF12_REVISION_ID_DEFAULT 0x00000000 4886 #define smnBIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE_DEFAULT 0x00000000 4887 #define smnBIF_CFG_DEV0_EPF0_VF12_SUB_CLASS_DEFAULT 0x00000000 4888 #define smnBIF_CFG_DEV0_EPF0_VF12_BASE_CLASS_DEFAULT 0x00000000 4889 #define smnBIF_CFG_DEV0_EPF0_VF12_CACHE_LINE_DEFAULT 0x00000000 4890 #define smnBIF_CFG_DEV0_EPF0_VF12_LATENCY_DEFAULT 0x00000000 4891 #define smnBIF_CFG_DEV0_EPF0_VF12_HEADER_DEFAULT 0x00000000 4892 #define smnBIF_CFG_DEV0_EPF0_VF12_BIST_DEFAULT 0x00000000 4893 #define smnBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1_DEFAULT 0x00000000 4894 #define smnBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2_DEFAULT 0x00000000 4895 #define smnBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3_DEFAULT 0x00000000 4896 #define smnBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4_DEFAULT 0x00000000 4897 #define smnBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5_DEFAULT 0x00000000 4898 #define smnBIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6_DEFAULT 0x00000000 4899 #define smnBIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR_DEFAULT 0x00000000 4900 #define smnBIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID_DEFAULT 0x73101002 4901 #define smnBIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR_DEFAULT 0x00000000 4902 #define smnBIF_CFG_DEV0_EPF0_VF12_CAP_PTR_DEFAULT 0x00000048 4903 #define smnBIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE_DEFAULT 0x00000000 4904 #define smnBIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN_DEFAULT 0x00000000 4905 #define smnBIF_CFG_DEV0_EPF0_VF12_MIN_GRANT_DEFAULT 0x00000000 4906 #define smnBIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY_DEFAULT 0x00000000 4907 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST_DEFAULT 0x0000a000 4908 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_DEFAULT 0x00000002 4909 #define smnBIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP_DEFAULT 0x00000000 4910 #define smnBIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL_DEFAULT 0x00000000 4911 #define smnBIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS_DEFAULT 0x00000000 4912 #define smnBIF_CFG_DEV0_EPF0_VF12_LINK_CAP_DEFAULT 0x00000d04 4913 #define smnBIF_CFG_DEV0_EPF0_VF12_LINK_CNTL_DEFAULT 0x00000000 4914 #define smnBIF_CFG_DEV0_EPF0_VF12_LINK_STATUS_DEFAULT 0x00000000 4915 #define smnBIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2_DEFAULT 0x00010000 4916 #define smnBIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2_DEFAULT 0x00000000 4917 #define smnBIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2_DEFAULT 0x00000000 4918 #define smnBIF_CFG_DEV0_EPF0_VF12_LINK_CAP2_DEFAULT 0x0000001e 4919 #define smnBIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2_DEFAULT 0x00000000 4920 #define smnBIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2_DEFAULT 0x00000000 4921 #define smnBIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST_DEFAULT 0x0000c000 4922 #define smnBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL_DEFAULT 0x00000082 4923 #define smnBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 4924 #define smnBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 4925 #define smnBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_DEFAULT 0x00000000 4926 #define smnBIF_CFG_DEV0_EPF0_VF12_MSI_MASK_DEFAULT 0x00000000 4927 #define smnBIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64_DEFAULT 0x00000000 4928 #define smnBIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64_DEFAULT 0x00000000 4929 #define smnBIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_DEFAULT 0x00000000 4930 #define smnBIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64_DEFAULT 0x00000000 4931 #define smnBIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST_DEFAULT 0x00000000 4932 #define smnBIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL_DEFAULT 0x00000000 4933 #define smnBIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE_DEFAULT 0x00000000 4934 #define smnBIF_CFG_DEV0_EPF0_VF12_MSIX_PBA_DEFAULT 0x00000000 4935 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 4936 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 4937 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 4938 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 4939 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 4940 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 4941 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 4942 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 4943 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 4944 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 4945 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 4946 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0_DEFAULT 0x00000000 4947 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1_DEFAULT 0x00000000 4948 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2_DEFAULT 0x00000000 4949 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3_DEFAULT 0x00000000 4950 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 4951 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 4952 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 4953 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 4954 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 4955 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CAP_DEFAULT 0x00000000 4956 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CNTL_DEFAULT 0x00000000 4957 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 4958 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP_DEFAULT 0x00000000 4959 #define smnBIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL_DEFAULT 0x00000000 4960 4961 4962 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp 4963 #define smnBIF_CFG_DEV0_EPF0_VF13_VENDOR_ID_DEFAULT 0x00000000 4964 #define smnBIF_CFG_DEV0_EPF0_VF13_DEVICE_ID_DEFAULT 0x00000000 4965 #define smnBIF_CFG_DEV0_EPF0_VF13_COMMAND_DEFAULT 0x00000000 4966 #define smnBIF_CFG_DEV0_EPF0_VF13_STATUS_DEFAULT 0x00000000 4967 #define smnBIF_CFG_DEV0_EPF0_VF13_REVISION_ID_DEFAULT 0x00000000 4968 #define smnBIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE_DEFAULT 0x00000000 4969 #define smnBIF_CFG_DEV0_EPF0_VF13_SUB_CLASS_DEFAULT 0x00000000 4970 #define smnBIF_CFG_DEV0_EPF0_VF13_BASE_CLASS_DEFAULT 0x00000000 4971 #define smnBIF_CFG_DEV0_EPF0_VF13_CACHE_LINE_DEFAULT 0x00000000 4972 #define smnBIF_CFG_DEV0_EPF0_VF13_LATENCY_DEFAULT 0x00000000 4973 #define smnBIF_CFG_DEV0_EPF0_VF13_HEADER_DEFAULT 0x00000000 4974 #define smnBIF_CFG_DEV0_EPF0_VF13_BIST_DEFAULT 0x00000000 4975 #define smnBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1_DEFAULT 0x00000000 4976 #define smnBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2_DEFAULT 0x00000000 4977 #define smnBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3_DEFAULT 0x00000000 4978 #define smnBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4_DEFAULT 0x00000000 4979 #define smnBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5_DEFAULT 0x00000000 4980 #define smnBIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6_DEFAULT 0x00000000 4981 #define smnBIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR_DEFAULT 0x00000000 4982 #define smnBIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID_DEFAULT 0x73101002 4983 #define smnBIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR_DEFAULT 0x00000000 4984 #define smnBIF_CFG_DEV0_EPF0_VF13_CAP_PTR_DEFAULT 0x00000048 4985 #define smnBIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE_DEFAULT 0x00000000 4986 #define smnBIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN_DEFAULT 0x00000000 4987 #define smnBIF_CFG_DEV0_EPF0_VF13_MIN_GRANT_DEFAULT 0x00000000 4988 #define smnBIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY_DEFAULT 0x00000000 4989 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST_DEFAULT 0x0000a000 4990 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_DEFAULT 0x00000002 4991 #define smnBIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP_DEFAULT 0x00000000 4992 #define smnBIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL_DEFAULT 0x00000000 4993 #define smnBIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS_DEFAULT 0x00000000 4994 #define smnBIF_CFG_DEV0_EPF0_VF13_LINK_CAP_DEFAULT 0x00000d04 4995 #define smnBIF_CFG_DEV0_EPF0_VF13_LINK_CNTL_DEFAULT 0x00000000 4996 #define smnBIF_CFG_DEV0_EPF0_VF13_LINK_STATUS_DEFAULT 0x00000000 4997 #define smnBIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2_DEFAULT 0x00010000 4998 #define smnBIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2_DEFAULT 0x00000000 4999 #define smnBIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2_DEFAULT 0x00000000 5000 #define smnBIF_CFG_DEV0_EPF0_VF13_LINK_CAP2_DEFAULT 0x0000001e 5001 #define smnBIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2_DEFAULT 0x00000000 5002 #define smnBIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2_DEFAULT 0x00000000 5003 #define smnBIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST_DEFAULT 0x0000c000 5004 #define smnBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL_DEFAULT 0x00000082 5005 #define smnBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 5006 #define smnBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 5007 #define smnBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_DEFAULT 0x00000000 5008 #define smnBIF_CFG_DEV0_EPF0_VF13_MSI_MASK_DEFAULT 0x00000000 5009 #define smnBIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64_DEFAULT 0x00000000 5010 #define smnBIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64_DEFAULT 0x00000000 5011 #define smnBIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_DEFAULT 0x00000000 5012 #define smnBIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64_DEFAULT 0x00000000 5013 #define smnBIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST_DEFAULT 0x00000000 5014 #define smnBIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL_DEFAULT 0x00000000 5015 #define smnBIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE_DEFAULT 0x00000000 5016 #define smnBIF_CFG_DEV0_EPF0_VF13_MSIX_PBA_DEFAULT 0x00000000 5017 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 5018 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 5019 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 5020 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 5021 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 5022 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 5023 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 5024 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 5025 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 5026 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 5027 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 5028 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0_DEFAULT 0x00000000 5029 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1_DEFAULT 0x00000000 5030 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2_DEFAULT 0x00000000 5031 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3_DEFAULT 0x00000000 5032 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 5033 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 5034 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 5035 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 5036 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 5037 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CAP_DEFAULT 0x00000000 5038 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CNTL_DEFAULT 0x00000000 5039 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 5040 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP_DEFAULT 0x00000000 5041 #define smnBIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL_DEFAULT 0x00000000 5042 5043 5044 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp 5045 #define smnBIF_CFG_DEV0_EPF0_VF14_VENDOR_ID_DEFAULT 0x00000000 5046 #define smnBIF_CFG_DEV0_EPF0_VF14_DEVICE_ID_DEFAULT 0x00000000 5047 #define smnBIF_CFG_DEV0_EPF0_VF14_COMMAND_DEFAULT 0x00000000 5048 #define smnBIF_CFG_DEV0_EPF0_VF14_STATUS_DEFAULT 0x00000000 5049 #define smnBIF_CFG_DEV0_EPF0_VF14_REVISION_ID_DEFAULT 0x00000000 5050 #define smnBIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE_DEFAULT 0x00000000 5051 #define smnBIF_CFG_DEV0_EPF0_VF14_SUB_CLASS_DEFAULT 0x00000000 5052 #define smnBIF_CFG_DEV0_EPF0_VF14_BASE_CLASS_DEFAULT 0x00000000 5053 #define smnBIF_CFG_DEV0_EPF0_VF14_CACHE_LINE_DEFAULT 0x00000000 5054 #define smnBIF_CFG_DEV0_EPF0_VF14_LATENCY_DEFAULT 0x00000000 5055 #define smnBIF_CFG_DEV0_EPF0_VF14_HEADER_DEFAULT 0x00000000 5056 #define smnBIF_CFG_DEV0_EPF0_VF14_BIST_DEFAULT 0x00000000 5057 #define smnBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1_DEFAULT 0x00000000 5058 #define smnBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2_DEFAULT 0x00000000 5059 #define smnBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3_DEFAULT 0x00000000 5060 #define smnBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4_DEFAULT 0x00000000 5061 #define smnBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5_DEFAULT 0x00000000 5062 #define smnBIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6_DEFAULT 0x00000000 5063 #define smnBIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR_DEFAULT 0x00000000 5064 #define smnBIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID_DEFAULT 0x73101002 5065 #define smnBIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR_DEFAULT 0x00000000 5066 #define smnBIF_CFG_DEV0_EPF0_VF14_CAP_PTR_DEFAULT 0x00000048 5067 #define smnBIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE_DEFAULT 0x00000000 5068 #define smnBIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN_DEFAULT 0x00000000 5069 #define smnBIF_CFG_DEV0_EPF0_VF14_MIN_GRANT_DEFAULT 0x00000000 5070 #define smnBIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY_DEFAULT 0x00000000 5071 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST_DEFAULT 0x0000a000 5072 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_DEFAULT 0x00000002 5073 #define smnBIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP_DEFAULT 0x00000000 5074 #define smnBIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL_DEFAULT 0x00000000 5075 #define smnBIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS_DEFAULT 0x00000000 5076 #define smnBIF_CFG_DEV0_EPF0_VF14_LINK_CAP_DEFAULT 0x00000d04 5077 #define smnBIF_CFG_DEV0_EPF0_VF14_LINK_CNTL_DEFAULT 0x00000000 5078 #define smnBIF_CFG_DEV0_EPF0_VF14_LINK_STATUS_DEFAULT 0x00000000 5079 #define smnBIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2_DEFAULT 0x00010000 5080 #define smnBIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2_DEFAULT 0x00000000 5081 #define smnBIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2_DEFAULT 0x00000000 5082 #define smnBIF_CFG_DEV0_EPF0_VF14_LINK_CAP2_DEFAULT 0x0000001e 5083 #define smnBIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2_DEFAULT 0x00000000 5084 #define smnBIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2_DEFAULT 0x00000000 5085 #define smnBIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST_DEFAULT 0x0000c000 5086 #define smnBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL_DEFAULT 0x00000082 5087 #define smnBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 5088 #define smnBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 5089 #define smnBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_DEFAULT 0x00000000 5090 #define smnBIF_CFG_DEV0_EPF0_VF14_MSI_MASK_DEFAULT 0x00000000 5091 #define smnBIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64_DEFAULT 0x00000000 5092 #define smnBIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64_DEFAULT 0x00000000 5093 #define smnBIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_DEFAULT 0x00000000 5094 #define smnBIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64_DEFAULT 0x00000000 5095 #define smnBIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST_DEFAULT 0x00000000 5096 #define smnBIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL_DEFAULT 0x00000000 5097 #define smnBIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE_DEFAULT 0x00000000 5098 #define smnBIF_CFG_DEV0_EPF0_VF14_MSIX_PBA_DEFAULT 0x00000000 5099 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 5100 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 5101 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 5102 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 5103 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 5104 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 5105 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 5106 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 5107 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 5108 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 5109 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 5110 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0_DEFAULT 0x00000000 5111 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1_DEFAULT 0x00000000 5112 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2_DEFAULT 0x00000000 5113 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3_DEFAULT 0x00000000 5114 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 5115 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 5116 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 5117 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 5118 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 5119 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CAP_DEFAULT 0x00000000 5120 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CNTL_DEFAULT 0x00000000 5121 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 5122 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP_DEFAULT 0x00000000 5123 #define smnBIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL_DEFAULT 0x00000000 5124 5125 5126 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp 5127 #define smnBIF_CFG_DEV0_EPF0_VF15_VENDOR_ID_DEFAULT 0x00000000 5128 #define smnBIF_CFG_DEV0_EPF0_VF15_DEVICE_ID_DEFAULT 0x00000000 5129 #define smnBIF_CFG_DEV0_EPF0_VF15_COMMAND_DEFAULT 0x00000000 5130 #define smnBIF_CFG_DEV0_EPF0_VF15_STATUS_DEFAULT 0x00000000 5131 #define smnBIF_CFG_DEV0_EPF0_VF15_REVISION_ID_DEFAULT 0x00000000 5132 #define smnBIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE_DEFAULT 0x00000000 5133 #define smnBIF_CFG_DEV0_EPF0_VF15_SUB_CLASS_DEFAULT 0x00000000 5134 #define smnBIF_CFG_DEV0_EPF0_VF15_BASE_CLASS_DEFAULT 0x00000000 5135 #define smnBIF_CFG_DEV0_EPF0_VF15_CACHE_LINE_DEFAULT 0x00000000 5136 #define smnBIF_CFG_DEV0_EPF0_VF15_LATENCY_DEFAULT 0x00000000 5137 #define smnBIF_CFG_DEV0_EPF0_VF15_HEADER_DEFAULT 0x00000000 5138 #define smnBIF_CFG_DEV0_EPF0_VF15_BIST_DEFAULT 0x00000000 5139 #define smnBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1_DEFAULT 0x00000000 5140 #define smnBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2_DEFAULT 0x00000000 5141 #define smnBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3_DEFAULT 0x00000000 5142 #define smnBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4_DEFAULT 0x00000000 5143 #define smnBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5_DEFAULT 0x00000000 5144 #define smnBIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6_DEFAULT 0x00000000 5145 #define smnBIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR_DEFAULT 0x00000000 5146 #define smnBIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID_DEFAULT 0x73101002 5147 #define smnBIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR_DEFAULT 0x00000000 5148 #define smnBIF_CFG_DEV0_EPF0_VF15_CAP_PTR_DEFAULT 0x00000048 5149 #define smnBIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE_DEFAULT 0x00000000 5150 #define smnBIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN_DEFAULT 0x00000000 5151 #define smnBIF_CFG_DEV0_EPF0_VF15_MIN_GRANT_DEFAULT 0x00000000 5152 #define smnBIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY_DEFAULT 0x00000000 5153 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST_DEFAULT 0x0000a000 5154 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_DEFAULT 0x00000002 5155 #define smnBIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP_DEFAULT 0x00000000 5156 #define smnBIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL_DEFAULT 0x00000000 5157 #define smnBIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS_DEFAULT 0x00000000 5158 #define smnBIF_CFG_DEV0_EPF0_VF15_LINK_CAP_DEFAULT 0x00000d04 5159 #define smnBIF_CFG_DEV0_EPF0_VF15_LINK_CNTL_DEFAULT 0x00000000 5160 #define smnBIF_CFG_DEV0_EPF0_VF15_LINK_STATUS_DEFAULT 0x00000000 5161 #define smnBIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2_DEFAULT 0x00010000 5162 #define smnBIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2_DEFAULT 0x00000000 5163 #define smnBIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2_DEFAULT 0x00000000 5164 #define smnBIF_CFG_DEV0_EPF0_VF15_LINK_CAP2_DEFAULT 0x0000001e 5165 #define smnBIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2_DEFAULT 0x00000000 5166 #define smnBIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2_DEFAULT 0x00000000 5167 #define smnBIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST_DEFAULT 0x0000c000 5168 #define smnBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL_DEFAULT 0x00000082 5169 #define smnBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 5170 #define smnBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 5171 #define smnBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_DEFAULT 0x00000000 5172 #define smnBIF_CFG_DEV0_EPF0_VF15_MSI_MASK_DEFAULT 0x00000000 5173 #define smnBIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64_DEFAULT 0x00000000 5174 #define smnBIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64_DEFAULT 0x00000000 5175 #define smnBIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_DEFAULT 0x00000000 5176 #define smnBIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64_DEFAULT 0x00000000 5177 #define smnBIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST_DEFAULT 0x00000000 5178 #define smnBIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL_DEFAULT 0x00000000 5179 #define smnBIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE_DEFAULT 0x00000000 5180 #define smnBIF_CFG_DEV0_EPF0_VF15_MSIX_PBA_DEFAULT 0x00000000 5181 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 5182 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 5183 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 5184 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 5185 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 5186 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 5187 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 5188 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 5189 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 5190 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 5191 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 5192 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0_DEFAULT 0x00000000 5193 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1_DEFAULT 0x00000000 5194 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2_DEFAULT 0x00000000 5195 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3_DEFAULT 0x00000000 5196 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 5197 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 5198 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 5199 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 5200 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 5201 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CAP_DEFAULT 0x00000000 5202 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CNTL_DEFAULT 0x00000000 5203 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 5204 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP_DEFAULT 0x00000000 5205 #define smnBIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL_DEFAULT 0x00000000 5206 5207 5208 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf16_bifcfgdecp 5209 #define smnBIF_CFG_DEV0_EPF0_VF16_VENDOR_ID_DEFAULT 0x00000000 5210 #define smnBIF_CFG_DEV0_EPF0_VF16_DEVICE_ID_DEFAULT 0x00000000 5211 #define smnBIF_CFG_DEV0_EPF0_VF16_COMMAND_DEFAULT 0x00000000 5212 #define smnBIF_CFG_DEV0_EPF0_VF16_STATUS_DEFAULT 0x00000000 5213 #define smnBIF_CFG_DEV0_EPF0_VF16_REVISION_ID_DEFAULT 0x00000000 5214 #define smnBIF_CFG_DEV0_EPF0_VF16_PROG_INTERFACE_DEFAULT 0x00000000 5215 #define smnBIF_CFG_DEV0_EPF0_VF16_SUB_CLASS_DEFAULT 0x00000000 5216 #define smnBIF_CFG_DEV0_EPF0_VF16_BASE_CLASS_DEFAULT 0x00000000 5217 #define smnBIF_CFG_DEV0_EPF0_VF16_CACHE_LINE_DEFAULT 0x00000000 5218 #define smnBIF_CFG_DEV0_EPF0_VF16_LATENCY_DEFAULT 0x00000000 5219 #define smnBIF_CFG_DEV0_EPF0_VF16_HEADER_DEFAULT 0x00000000 5220 #define smnBIF_CFG_DEV0_EPF0_VF16_BIST_DEFAULT 0x00000000 5221 #define smnBIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_1_DEFAULT 0x00000000 5222 #define smnBIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_2_DEFAULT 0x00000000 5223 #define smnBIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_3_DEFAULT 0x00000000 5224 #define smnBIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_4_DEFAULT 0x00000000 5225 #define smnBIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_5_DEFAULT 0x00000000 5226 #define smnBIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_6_DEFAULT 0x00000000 5227 #define smnBIF_CFG_DEV0_EPF0_VF16_CARDBUS_CIS_PTR_DEFAULT 0x00000000 5228 #define smnBIF_CFG_DEV0_EPF0_VF16_ADAPTER_ID_DEFAULT 0x73101002 5229 #define smnBIF_CFG_DEV0_EPF0_VF16_ROM_BASE_ADDR_DEFAULT 0x00000000 5230 #define smnBIF_CFG_DEV0_EPF0_VF16_CAP_PTR_DEFAULT 0x00000048 5231 #define smnBIF_CFG_DEV0_EPF0_VF16_INTERRUPT_LINE_DEFAULT 0x00000000 5232 #define smnBIF_CFG_DEV0_EPF0_VF16_INTERRUPT_PIN_DEFAULT 0x00000000 5233 #define smnBIF_CFG_DEV0_EPF0_VF16_MIN_GRANT_DEFAULT 0x00000000 5234 #define smnBIF_CFG_DEV0_EPF0_VF16_MAX_LATENCY_DEFAULT 0x00000000 5235 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_CAP_LIST_DEFAULT 0x0000a000 5236 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_CAP_DEFAULT 0x00000002 5237 #define smnBIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP_DEFAULT 0x00000000 5238 #define smnBIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL_DEFAULT 0x00000000 5239 #define smnBIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS_DEFAULT 0x00000000 5240 #define smnBIF_CFG_DEV0_EPF0_VF16_LINK_CAP_DEFAULT 0x00000d04 5241 #define smnBIF_CFG_DEV0_EPF0_VF16_LINK_CNTL_DEFAULT 0x00000000 5242 #define smnBIF_CFG_DEV0_EPF0_VF16_LINK_STATUS_DEFAULT 0x00000000 5243 #define smnBIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2_DEFAULT 0x00010000 5244 #define smnBIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2_DEFAULT 0x00000000 5245 #define smnBIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS2_DEFAULT 0x00000000 5246 #define smnBIF_CFG_DEV0_EPF0_VF16_LINK_CAP2_DEFAULT 0x0000001e 5247 #define smnBIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2_DEFAULT 0x00000000 5248 #define smnBIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2_DEFAULT 0x00000000 5249 #define smnBIF_CFG_DEV0_EPF0_VF16_MSI_CAP_LIST_DEFAULT 0x0000c000 5250 #define smnBIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL_DEFAULT 0x00000082 5251 #define smnBIF_CFG_DEV0_EPF0_VF16_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 5252 #define smnBIF_CFG_DEV0_EPF0_VF16_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 5253 #define smnBIF_CFG_DEV0_EPF0_VF16_MSI_MSG_DATA_DEFAULT 0x00000000 5254 #define smnBIF_CFG_DEV0_EPF0_VF16_MSI_MASK_DEFAULT 0x00000000 5255 #define smnBIF_CFG_DEV0_EPF0_VF16_MSI_MSG_DATA_64_DEFAULT 0x00000000 5256 #define smnBIF_CFG_DEV0_EPF0_VF16_MSI_MASK_64_DEFAULT 0x00000000 5257 #define smnBIF_CFG_DEV0_EPF0_VF16_MSI_PENDING_DEFAULT 0x00000000 5258 #define smnBIF_CFG_DEV0_EPF0_VF16_MSI_PENDING_64_DEFAULT 0x00000000 5259 #define smnBIF_CFG_DEV0_EPF0_VF16_MSIX_CAP_LIST_DEFAULT 0x00000000 5260 #define smnBIF_CFG_DEV0_EPF0_VF16_MSIX_MSG_CNTL_DEFAULT 0x00000000 5261 #define smnBIF_CFG_DEV0_EPF0_VF16_MSIX_TABLE_DEFAULT 0x00000000 5262 #define smnBIF_CFG_DEV0_EPF0_VF16_MSIX_PBA_DEFAULT 0x00000000 5263 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 5264 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 5265 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 5266 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 5267 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 5268 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 5269 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 5270 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 5271 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 5272 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 5273 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 5274 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG0_DEFAULT 0x00000000 5275 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG1_DEFAULT 0x00000000 5276 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG2_DEFAULT 0x00000000 5277 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG3_DEFAULT 0x00000000 5278 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 5279 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 5280 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 5281 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 5282 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 5283 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CAP_DEFAULT 0x00000000 5284 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CNTL_DEFAULT 0x00000000 5285 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 5286 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CAP_DEFAULT 0x00000000 5287 #define smnBIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CNTL_DEFAULT 0x00000000 5288 5289 5290 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf17_bifcfgdecp 5291 #define smnBIF_CFG_DEV0_EPF0_VF17_VENDOR_ID_DEFAULT 0x00000000 5292 #define smnBIF_CFG_DEV0_EPF0_VF17_DEVICE_ID_DEFAULT 0x00000000 5293 #define smnBIF_CFG_DEV0_EPF0_VF17_COMMAND_DEFAULT 0x00000000 5294 #define smnBIF_CFG_DEV0_EPF0_VF17_STATUS_DEFAULT 0x00000000 5295 #define smnBIF_CFG_DEV0_EPF0_VF17_REVISION_ID_DEFAULT 0x00000000 5296 #define smnBIF_CFG_DEV0_EPF0_VF17_PROG_INTERFACE_DEFAULT 0x00000000 5297 #define smnBIF_CFG_DEV0_EPF0_VF17_SUB_CLASS_DEFAULT 0x00000000 5298 #define smnBIF_CFG_DEV0_EPF0_VF17_BASE_CLASS_DEFAULT 0x00000000 5299 #define smnBIF_CFG_DEV0_EPF0_VF17_CACHE_LINE_DEFAULT 0x00000000 5300 #define smnBIF_CFG_DEV0_EPF0_VF17_LATENCY_DEFAULT 0x00000000 5301 #define smnBIF_CFG_DEV0_EPF0_VF17_HEADER_DEFAULT 0x00000000 5302 #define smnBIF_CFG_DEV0_EPF0_VF17_BIST_DEFAULT 0x00000000 5303 #define smnBIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_1_DEFAULT 0x00000000 5304 #define smnBIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_2_DEFAULT 0x00000000 5305 #define smnBIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_3_DEFAULT 0x00000000 5306 #define smnBIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_4_DEFAULT 0x00000000 5307 #define smnBIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_5_DEFAULT 0x00000000 5308 #define smnBIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_6_DEFAULT 0x00000000 5309 #define smnBIF_CFG_DEV0_EPF0_VF17_CARDBUS_CIS_PTR_DEFAULT 0x00000000 5310 #define smnBIF_CFG_DEV0_EPF0_VF17_ADAPTER_ID_DEFAULT 0x73101002 5311 #define smnBIF_CFG_DEV0_EPF0_VF17_ROM_BASE_ADDR_DEFAULT 0x00000000 5312 #define smnBIF_CFG_DEV0_EPF0_VF17_CAP_PTR_DEFAULT 0x00000048 5313 #define smnBIF_CFG_DEV0_EPF0_VF17_INTERRUPT_LINE_DEFAULT 0x00000000 5314 #define smnBIF_CFG_DEV0_EPF0_VF17_INTERRUPT_PIN_DEFAULT 0x00000000 5315 #define smnBIF_CFG_DEV0_EPF0_VF17_MIN_GRANT_DEFAULT 0x00000000 5316 #define smnBIF_CFG_DEV0_EPF0_VF17_MAX_LATENCY_DEFAULT 0x00000000 5317 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_CAP_LIST_DEFAULT 0x0000a000 5318 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_CAP_DEFAULT 0x00000002 5319 #define smnBIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP_DEFAULT 0x00000000 5320 #define smnBIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL_DEFAULT 0x00000000 5321 #define smnBIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS_DEFAULT 0x00000000 5322 #define smnBIF_CFG_DEV0_EPF0_VF17_LINK_CAP_DEFAULT 0x00000d04 5323 #define smnBIF_CFG_DEV0_EPF0_VF17_LINK_CNTL_DEFAULT 0x00000000 5324 #define smnBIF_CFG_DEV0_EPF0_VF17_LINK_STATUS_DEFAULT 0x00000000 5325 #define smnBIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2_DEFAULT 0x00010000 5326 #define smnBIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2_DEFAULT 0x00000000 5327 #define smnBIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS2_DEFAULT 0x00000000 5328 #define smnBIF_CFG_DEV0_EPF0_VF17_LINK_CAP2_DEFAULT 0x0000001e 5329 #define smnBIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2_DEFAULT 0x00000000 5330 #define smnBIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2_DEFAULT 0x00000000 5331 #define smnBIF_CFG_DEV0_EPF0_VF17_MSI_CAP_LIST_DEFAULT 0x0000c000 5332 #define smnBIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL_DEFAULT 0x00000082 5333 #define smnBIF_CFG_DEV0_EPF0_VF17_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 5334 #define smnBIF_CFG_DEV0_EPF0_VF17_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 5335 #define smnBIF_CFG_DEV0_EPF0_VF17_MSI_MSG_DATA_DEFAULT 0x00000000 5336 #define smnBIF_CFG_DEV0_EPF0_VF17_MSI_MASK_DEFAULT 0x00000000 5337 #define smnBIF_CFG_DEV0_EPF0_VF17_MSI_MSG_DATA_64_DEFAULT 0x00000000 5338 #define smnBIF_CFG_DEV0_EPF0_VF17_MSI_MASK_64_DEFAULT 0x00000000 5339 #define smnBIF_CFG_DEV0_EPF0_VF17_MSI_PENDING_DEFAULT 0x00000000 5340 #define smnBIF_CFG_DEV0_EPF0_VF17_MSI_PENDING_64_DEFAULT 0x00000000 5341 #define smnBIF_CFG_DEV0_EPF0_VF17_MSIX_CAP_LIST_DEFAULT 0x00000000 5342 #define smnBIF_CFG_DEV0_EPF0_VF17_MSIX_MSG_CNTL_DEFAULT 0x00000000 5343 #define smnBIF_CFG_DEV0_EPF0_VF17_MSIX_TABLE_DEFAULT 0x00000000 5344 #define smnBIF_CFG_DEV0_EPF0_VF17_MSIX_PBA_DEFAULT 0x00000000 5345 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 5346 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 5347 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 5348 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 5349 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 5350 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 5351 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 5352 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 5353 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 5354 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 5355 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 5356 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG0_DEFAULT 0x00000000 5357 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG1_DEFAULT 0x00000000 5358 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG2_DEFAULT 0x00000000 5359 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG3_DEFAULT 0x00000000 5360 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 5361 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 5362 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 5363 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 5364 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 5365 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CAP_DEFAULT 0x00000000 5366 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CNTL_DEFAULT 0x00000000 5367 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 5368 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CAP_DEFAULT 0x00000000 5369 #define smnBIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CNTL_DEFAULT 0x00000000 5370 5371 5372 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf18_bifcfgdecp 5373 #define smnBIF_CFG_DEV0_EPF0_VF18_VENDOR_ID_DEFAULT 0x00000000 5374 #define smnBIF_CFG_DEV0_EPF0_VF18_DEVICE_ID_DEFAULT 0x00000000 5375 #define smnBIF_CFG_DEV0_EPF0_VF18_COMMAND_DEFAULT 0x00000000 5376 #define smnBIF_CFG_DEV0_EPF0_VF18_STATUS_DEFAULT 0x00000000 5377 #define smnBIF_CFG_DEV0_EPF0_VF18_REVISION_ID_DEFAULT 0x00000000 5378 #define smnBIF_CFG_DEV0_EPF0_VF18_PROG_INTERFACE_DEFAULT 0x00000000 5379 #define smnBIF_CFG_DEV0_EPF0_VF18_SUB_CLASS_DEFAULT 0x00000000 5380 #define smnBIF_CFG_DEV0_EPF0_VF18_BASE_CLASS_DEFAULT 0x00000000 5381 #define smnBIF_CFG_DEV0_EPF0_VF18_CACHE_LINE_DEFAULT 0x00000000 5382 #define smnBIF_CFG_DEV0_EPF0_VF18_LATENCY_DEFAULT 0x00000000 5383 #define smnBIF_CFG_DEV0_EPF0_VF18_HEADER_DEFAULT 0x00000000 5384 #define smnBIF_CFG_DEV0_EPF0_VF18_BIST_DEFAULT 0x00000000 5385 #define smnBIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_1_DEFAULT 0x00000000 5386 #define smnBIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_2_DEFAULT 0x00000000 5387 #define smnBIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_3_DEFAULT 0x00000000 5388 #define smnBIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_4_DEFAULT 0x00000000 5389 #define smnBIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_5_DEFAULT 0x00000000 5390 #define smnBIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_6_DEFAULT 0x00000000 5391 #define smnBIF_CFG_DEV0_EPF0_VF18_CARDBUS_CIS_PTR_DEFAULT 0x00000000 5392 #define smnBIF_CFG_DEV0_EPF0_VF18_ADAPTER_ID_DEFAULT 0x73101002 5393 #define smnBIF_CFG_DEV0_EPF0_VF18_ROM_BASE_ADDR_DEFAULT 0x00000000 5394 #define smnBIF_CFG_DEV0_EPF0_VF18_CAP_PTR_DEFAULT 0x00000048 5395 #define smnBIF_CFG_DEV0_EPF0_VF18_INTERRUPT_LINE_DEFAULT 0x00000000 5396 #define smnBIF_CFG_DEV0_EPF0_VF18_INTERRUPT_PIN_DEFAULT 0x00000000 5397 #define smnBIF_CFG_DEV0_EPF0_VF18_MIN_GRANT_DEFAULT 0x00000000 5398 #define smnBIF_CFG_DEV0_EPF0_VF18_MAX_LATENCY_DEFAULT 0x00000000 5399 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_CAP_LIST_DEFAULT 0x0000a000 5400 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_CAP_DEFAULT 0x00000002 5401 #define smnBIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP_DEFAULT 0x00000000 5402 #define smnBIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL_DEFAULT 0x00000000 5403 #define smnBIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS_DEFAULT 0x00000000 5404 #define smnBIF_CFG_DEV0_EPF0_VF18_LINK_CAP_DEFAULT 0x00000d04 5405 #define smnBIF_CFG_DEV0_EPF0_VF18_LINK_CNTL_DEFAULT 0x00000000 5406 #define smnBIF_CFG_DEV0_EPF0_VF18_LINK_STATUS_DEFAULT 0x00000000 5407 #define smnBIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2_DEFAULT 0x00010000 5408 #define smnBIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2_DEFAULT 0x00000000 5409 #define smnBIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS2_DEFAULT 0x00000000 5410 #define smnBIF_CFG_DEV0_EPF0_VF18_LINK_CAP2_DEFAULT 0x0000001e 5411 #define smnBIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2_DEFAULT 0x00000000 5412 #define smnBIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2_DEFAULT 0x00000000 5413 #define smnBIF_CFG_DEV0_EPF0_VF18_MSI_CAP_LIST_DEFAULT 0x0000c000 5414 #define smnBIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL_DEFAULT 0x00000082 5415 #define smnBIF_CFG_DEV0_EPF0_VF18_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 5416 #define smnBIF_CFG_DEV0_EPF0_VF18_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 5417 #define smnBIF_CFG_DEV0_EPF0_VF18_MSI_MSG_DATA_DEFAULT 0x00000000 5418 #define smnBIF_CFG_DEV0_EPF0_VF18_MSI_MASK_DEFAULT 0x00000000 5419 #define smnBIF_CFG_DEV0_EPF0_VF18_MSI_MSG_DATA_64_DEFAULT 0x00000000 5420 #define smnBIF_CFG_DEV0_EPF0_VF18_MSI_MASK_64_DEFAULT 0x00000000 5421 #define smnBIF_CFG_DEV0_EPF0_VF18_MSI_PENDING_DEFAULT 0x00000000 5422 #define smnBIF_CFG_DEV0_EPF0_VF18_MSI_PENDING_64_DEFAULT 0x00000000 5423 #define smnBIF_CFG_DEV0_EPF0_VF18_MSIX_CAP_LIST_DEFAULT 0x00000000 5424 #define smnBIF_CFG_DEV0_EPF0_VF18_MSIX_MSG_CNTL_DEFAULT 0x00000000 5425 #define smnBIF_CFG_DEV0_EPF0_VF18_MSIX_TABLE_DEFAULT 0x00000000 5426 #define smnBIF_CFG_DEV0_EPF0_VF18_MSIX_PBA_DEFAULT 0x00000000 5427 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 5428 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 5429 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 5430 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 5431 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 5432 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 5433 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 5434 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 5435 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 5436 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 5437 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 5438 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG0_DEFAULT 0x00000000 5439 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG1_DEFAULT 0x00000000 5440 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG2_DEFAULT 0x00000000 5441 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG3_DEFAULT 0x00000000 5442 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 5443 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 5444 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 5445 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 5446 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 5447 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CAP_DEFAULT 0x00000000 5448 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CNTL_DEFAULT 0x00000000 5449 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 5450 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CAP_DEFAULT 0x00000000 5451 #define smnBIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CNTL_DEFAULT 0x00000000 5452 5453 5454 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf19_bifcfgdecp 5455 #define smnBIF_CFG_DEV0_EPF0_VF19_VENDOR_ID_DEFAULT 0x00000000 5456 #define smnBIF_CFG_DEV0_EPF0_VF19_DEVICE_ID_DEFAULT 0x00000000 5457 #define smnBIF_CFG_DEV0_EPF0_VF19_COMMAND_DEFAULT 0x00000000 5458 #define smnBIF_CFG_DEV0_EPF0_VF19_STATUS_DEFAULT 0x00000000 5459 #define smnBIF_CFG_DEV0_EPF0_VF19_REVISION_ID_DEFAULT 0x00000000 5460 #define smnBIF_CFG_DEV0_EPF0_VF19_PROG_INTERFACE_DEFAULT 0x00000000 5461 #define smnBIF_CFG_DEV0_EPF0_VF19_SUB_CLASS_DEFAULT 0x00000000 5462 #define smnBIF_CFG_DEV0_EPF0_VF19_BASE_CLASS_DEFAULT 0x00000000 5463 #define smnBIF_CFG_DEV0_EPF0_VF19_CACHE_LINE_DEFAULT 0x00000000 5464 #define smnBIF_CFG_DEV0_EPF0_VF19_LATENCY_DEFAULT 0x00000000 5465 #define smnBIF_CFG_DEV0_EPF0_VF19_HEADER_DEFAULT 0x00000000 5466 #define smnBIF_CFG_DEV0_EPF0_VF19_BIST_DEFAULT 0x00000000 5467 #define smnBIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_1_DEFAULT 0x00000000 5468 #define smnBIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_2_DEFAULT 0x00000000 5469 #define smnBIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_3_DEFAULT 0x00000000 5470 #define smnBIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_4_DEFAULT 0x00000000 5471 #define smnBIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_5_DEFAULT 0x00000000 5472 #define smnBIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_6_DEFAULT 0x00000000 5473 #define smnBIF_CFG_DEV0_EPF0_VF19_CARDBUS_CIS_PTR_DEFAULT 0x00000000 5474 #define smnBIF_CFG_DEV0_EPF0_VF19_ADAPTER_ID_DEFAULT 0x73101002 5475 #define smnBIF_CFG_DEV0_EPF0_VF19_ROM_BASE_ADDR_DEFAULT 0x00000000 5476 #define smnBIF_CFG_DEV0_EPF0_VF19_CAP_PTR_DEFAULT 0x00000048 5477 #define smnBIF_CFG_DEV0_EPF0_VF19_INTERRUPT_LINE_DEFAULT 0x00000000 5478 #define smnBIF_CFG_DEV0_EPF0_VF19_INTERRUPT_PIN_DEFAULT 0x00000000 5479 #define smnBIF_CFG_DEV0_EPF0_VF19_MIN_GRANT_DEFAULT 0x00000000 5480 #define smnBIF_CFG_DEV0_EPF0_VF19_MAX_LATENCY_DEFAULT 0x00000000 5481 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_CAP_LIST_DEFAULT 0x0000a000 5482 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_CAP_DEFAULT 0x00000002 5483 #define smnBIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP_DEFAULT 0x00000000 5484 #define smnBIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL_DEFAULT 0x00000000 5485 #define smnBIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS_DEFAULT 0x00000000 5486 #define smnBIF_CFG_DEV0_EPF0_VF19_LINK_CAP_DEFAULT 0x00000d04 5487 #define smnBIF_CFG_DEV0_EPF0_VF19_LINK_CNTL_DEFAULT 0x00000000 5488 #define smnBIF_CFG_DEV0_EPF0_VF19_LINK_STATUS_DEFAULT 0x00000000 5489 #define smnBIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2_DEFAULT 0x00010000 5490 #define smnBIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2_DEFAULT 0x00000000 5491 #define smnBIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS2_DEFAULT 0x00000000 5492 #define smnBIF_CFG_DEV0_EPF0_VF19_LINK_CAP2_DEFAULT 0x0000001e 5493 #define smnBIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2_DEFAULT 0x00000000 5494 #define smnBIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2_DEFAULT 0x00000000 5495 #define smnBIF_CFG_DEV0_EPF0_VF19_MSI_CAP_LIST_DEFAULT 0x0000c000 5496 #define smnBIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL_DEFAULT 0x00000082 5497 #define smnBIF_CFG_DEV0_EPF0_VF19_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 5498 #define smnBIF_CFG_DEV0_EPF0_VF19_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 5499 #define smnBIF_CFG_DEV0_EPF0_VF19_MSI_MSG_DATA_DEFAULT 0x00000000 5500 #define smnBIF_CFG_DEV0_EPF0_VF19_MSI_MASK_DEFAULT 0x00000000 5501 #define smnBIF_CFG_DEV0_EPF0_VF19_MSI_MSG_DATA_64_DEFAULT 0x00000000 5502 #define smnBIF_CFG_DEV0_EPF0_VF19_MSI_MASK_64_DEFAULT 0x00000000 5503 #define smnBIF_CFG_DEV0_EPF0_VF19_MSI_PENDING_DEFAULT 0x00000000 5504 #define smnBIF_CFG_DEV0_EPF0_VF19_MSI_PENDING_64_DEFAULT 0x00000000 5505 #define smnBIF_CFG_DEV0_EPF0_VF19_MSIX_CAP_LIST_DEFAULT 0x00000000 5506 #define smnBIF_CFG_DEV0_EPF0_VF19_MSIX_MSG_CNTL_DEFAULT 0x00000000 5507 #define smnBIF_CFG_DEV0_EPF0_VF19_MSIX_TABLE_DEFAULT 0x00000000 5508 #define smnBIF_CFG_DEV0_EPF0_VF19_MSIX_PBA_DEFAULT 0x00000000 5509 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 5510 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 5511 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 5512 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 5513 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 5514 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 5515 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 5516 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 5517 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 5518 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 5519 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 5520 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG0_DEFAULT 0x00000000 5521 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG1_DEFAULT 0x00000000 5522 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG2_DEFAULT 0x00000000 5523 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG3_DEFAULT 0x00000000 5524 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 5525 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 5526 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 5527 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 5528 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 5529 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CAP_DEFAULT 0x00000000 5530 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CNTL_DEFAULT 0x00000000 5531 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 5532 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CAP_DEFAULT 0x00000000 5533 #define smnBIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CNTL_DEFAULT 0x00000000 5534 5535 5536 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf20_bifcfgdecp 5537 #define smnBIF_CFG_DEV0_EPF0_VF20_VENDOR_ID_DEFAULT 0x00000000 5538 #define smnBIF_CFG_DEV0_EPF0_VF20_DEVICE_ID_DEFAULT 0x00000000 5539 #define smnBIF_CFG_DEV0_EPF0_VF20_COMMAND_DEFAULT 0x00000000 5540 #define smnBIF_CFG_DEV0_EPF0_VF20_STATUS_DEFAULT 0x00000000 5541 #define smnBIF_CFG_DEV0_EPF0_VF20_REVISION_ID_DEFAULT 0x00000000 5542 #define smnBIF_CFG_DEV0_EPF0_VF20_PROG_INTERFACE_DEFAULT 0x00000000 5543 #define smnBIF_CFG_DEV0_EPF0_VF20_SUB_CLASS_DEFAULT 0x00000000 5544 #define smnBIF_CFG_DEV0_EPF0_VF20_BASE_CLASS_DEFAULT 0x00000000 5545 #define smnBIF_CFG_DEV0_EPF0_VF20_CACHE_LINE_DEFAULT 0x00000000 5546 #define smnBIF_CFG_DEV0_EPF0_VF20_LATENCY_DEFAULT 0x00000000 5547 #define smnBIF_CFG_DEV0_EPF0_VF20_HEADER_DEFAULT 0x00000000 5548 #define smnBIF_CFG_DEV0_EPF0_VF20_BIST_DEFAULT 0x00000000 5549 #define smnBIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_1_DEFAULT 0x00000000 5550 #define smnBIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_2_DEFAULT 0x00000000 5551 #define smnBIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_3_DEFAULT 0x00000000 5552 #define smnBIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_4_DEFAULT 0x00000000 5553 #define smnBIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_5_DEFAULT 0x00000000 5554 #define smnBIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_6_DEFAULT 0x00000000 5555 #define smnBIF_CFG_DEV0_EPF0_VF20_CARDBUS_CIS_PTR_DEFAULT 0x00000000 5556 #define smnBIF_CFG_DEV0_EPF0_VF20_ADAPTER_ID_DEFAULT 0x73101002 5557 #define smnBIF_CFG_DEV0_EPF0_VF20_ROM_BASE_ADDR_DEFAULT 0x00000000 5558 #define smnBIF_CFG_DEV0_EPF0_VF20_CAP_PTR_DEFAULT 0x00000048 5559 #define smnBIF_CFG_DEV0_EPF0_VF20_INTERRUPT_LINE_DEFAULT 0x00000000 5560 #define smnBIF_CFG_DEV0_EPF0_VF20_INTERRUPT_PIN_DEFAULT 0x00000000 5561 #define smnBIF_CFG_DEV0_EPF0_VF20_MIN_GRANT_DEFAULT 0x00000000 5562 #define smnBIF_CFG_DEV0_EPF0_VF20_MAX_LATENCY_DEFAULT 0x00000000 5563 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_CAP_LIST_DEFAULT 0x0000a000 5564 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_CAP_DEFAULT 0x00000002 5565 #define smnBIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP_DEFAULT 0x00000000 5566 #define smnBIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL_DEFAULT 0x00000000 5567 #define smnBIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS_DEFAULT 0x00000000 5568 #define smnBIF_CFG_DEV0_EPF0_VF20_LINK_CAP_DEFAULT 0x00000d04 5569 #define smnBIF_CFG_DEV0_EPF0_VF20_LINK_CNTL_DEFAULT 0x00000000 5570 #define smnBIF_CFG_DEV0_EPF0_VF20_LINK_STATUS_DEFAULT 0x00000000 5571 #define smnBIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2_DEFAULT 0x00010000 5572 #define smnBIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2_DEFAULT 0x00000000 5573 #define smnBIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS2_DEFAULT 0x00000000 5574 #define smnBIF_CFG_DEV0_EPF0_VF20_LINK_CAP2_DEFAULT 0x0000001e 5575 #define smnBIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2_DEFAULT 0x00000000 5576 #define smnBIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2_DEFAULT 0x00000000 5577 #define smnBIF_CFG_DEV0_EPF0_VF20_MSI_CAP_LIST_DEFAULT 0x0000c000 5578 #define smnBIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL_DEFAULT 0x00000082 5579 #define smnBIF_CFG_DEV0_EPF0_VF20_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 5580 #define smnBIF_CFG_DEV0_EPF0_VF20_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 5581 #define smnBIF_CFG_DEV0_EPF0_VF20_MSI_MSG_DATA_DEFAULT 0x00000000 5582 #define smnBIF_CFG_DEV0_EPF0_VF20_MSI_MASK_DEFAULT 0x00000000 5583 #define smnBIF_CFG_DEV0_EPF0_VF20_MSI_MSG_DATA_64_DEFAULT 0x00000000 5584 #define smnBIF_CFG_DEV0_EPF0_VF20_MSI_MASK_64_DEFAULT 0x00000000 5585 #define smnBIF_CFG_DEV0_EPF0_VF20_MSI_PENDING_DEFAULT 0x00000000 5586 #define smnBIF_CFG_DEV0_EPF0_VF20_MSI_PENDING_64_DEFAULT 0x00000000 5587 #define smnBIF_CFG_DEV0_EPF0_VF20_MSIX_CAP_LIST_DEFAULT 0x00000000 5588 #define smnBIF_CFG_DEV0_EPF0_VF20_MSIX_MSG_CNTL_DEFAULT 0x00000000 5589 #define smnBIF_CFG_DEV0_EPF0_VF20_MSIX_TABLE_DEFAULT 0x00000000 5590 #define smnBIF_CFG_DEV0_EPF0_VF20_MSIX_PBA_DEFAULT 0x00000000 5591 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 5592 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 5593 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 5594 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 5595 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 5596 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 5597 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 5598 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 5599 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 5600 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 5601 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 5602 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG0_DEFAULT 0x00000000 5603 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG1_DEFAULT 0x00000000 5604 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG2_DEFAULT 0x00000000 5605 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG3_DEFAULT 0x00000000 5606 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 5607 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 5608 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 5609 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 5610 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 5611 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CAP_DEFAULT 0x00000000 5612 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CNTL_DEFAULT 0x00000000 5613 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 5614 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CAP_DEFAULT 0x00000000 5615 #define smnBIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CNTL_DEFAULT 0x00000000 5616 5617 5618 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf21_bifcfgdecp 5619 #define smnBIF_CFG_DEV0_EPF0_VF21_VENDOR_ID_DEFAULT 0x00000000 5620 #define smnBIF_CFG_DEV0_EPF0_VF21_DEVICE_ID_DEFAULT 0x00000000 5621 #define smnBIF_CFG_DEV0_EPF0_VF21_COMMAND_DEFAULT 0x00000000 5622 #define smnBIF_CFG_DEV0_EPF0_VF21_STATUS_DEFAULT 0x00000000 5623 #define smnBIF_CFG_DEV0_EPF0_VF21_REVISION_ID_DEFAULT 0x00000000 5624 #define smnBIF_CFG_DEV0_EPF0_VF21_PROG_INTERFACE_DEFAULT 0x00000000 5625 #define smnBIF_CFG_DEV0_EPF0_VF21_SUB_CLASS_DEFAULT 0x00000000 5626 #define smnBIF_CFG_DEV0_EPF0_VF21_BASE_CLASS_DEFAULT 0x00000000 5627 #define smnBIF_CFG_DEV0_EPF0_VF21_CACHE_LINE_DEFAULT 0x00000000 5628 #define smnBIF_CFG_DEV0_EPF0_VF21_LATENCY_DEFAULT 0x00000000 5629 #define smnBIF_CFG_DEV0_EPF0_VF21_HEADER_DEFAULT 0x00000000 5630 #define smnBIF_CFG_DEV0_EPF0_VF21_BIST_DEFAULT 0x00000000 5631 #define smnBIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_1_DEFAULT 0x00000000 5632 #define smnBIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_2_DEFAULT 0x00000000 5633 #define smnBIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_3_DEFAULT 0x00000000 5634 #define smnBIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_4_DEFAULT 0x00000000 5635 #define smnBIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_5_DEFAULT 0x00000000 5636 #define smnBIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_6_DEFAULT 0x00000000 5637 #define smnBIF_CFG_DEV0_EPF0_VF21_CARDBUS_CIS_PTR_DEFAULT 0x00000000 5638 #define smnBIF_CFG_DEV0_EPF0_VF21_ADAPTER_ID_DEFAULT 0x73101002 5639 #define smnBIF_CFG_DEV0_EPF0_VF21_ROM_BASE_ADDR_DEFAULT 0x00000000 5640 #define smnBIF_CFG_DEV0_EPF0_VF21_CAP_PTR_DEFAULT 0x00000048 5641 #define smnBIF_CFG_DEV0_EPF0_VF21_INTERRUPT_LINE_DEFAULT 0x00000000 5642 #define smnBIF_CFG_DEV0_EPF0_VF21_INTERRUPT_PIN_DEFAULT 0x00000000 5643 #define smnBIF_CFG_DEV0_EPF0_VF21_MIN_GRANT_DEFAULT 0x00000000 5644 #define smnBIF_CFG_DEV0_EPF0_VF21_MAX_LATENCY_DEFAULT 0x00000000 5645 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_CAP_LIST_DEFAULT 0x0000a000 5646 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_CAP_DEFAULT 0x00000002 5647 #define smnBIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP_DEFAULT 0x00000000 5648 #define smnBIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL_DEFAULT 0x00000000 5649 #define smnBIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS_DEFAULT 0x00000000 5650 #define smnBIF_CFG_DEV0_EPF0_VF21_LINK_CAP_DEFAULT 0x00000d04 5651 #define smnBIF_CFG_DEV0_EPF0_VF21_LINK_CNTL_DEFAULT 0x00000000 5652 #define smnBIF_CFG_DEV0_EPF0_VF21_LINK_STATUS_DEFAULT 0x00000000 5653 #define smnBIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2_DEFAULT 0x00010000 5654 #define smnBIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2_DEFAULT 0x00000000 5655 #define smnBIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS2_DEFAULT 0x00000000 5656 #define smnBIF_CFG_DEV0_EPF0_VF21_LINK_CAP2_DEFAULT 0x0000001e 5657 #define smnBIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2_DEFAULT 0x00000000 5658 #define smnBIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2_DEFAULT 0x00000000 5659 #define smnBIF_CFG_DEV0_EPF0_VF21_MSI_CAP_LIST_DEFAULT 0x0000c000 5660 #define smnBIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL_DEFAULT 0x00000082 5661 #define smnBIF_CFG_DEV0_EPF0_VF21_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 5662 #define smnBIF_CFG_DEV0_EPF0_VF21_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 5663 #define smnBIF_CFG_DEV0_EPF0_VF21_MSI_MSG_DATA_DEFAULT 0x00000000 5664 #define smnBIF_CFG_DEV0_EPF0_VF21_MSI_MASK_DEFAULT 0x00000000 5665 #define smnBIF_CFG_DEV0_EPF0_VF21_MSI_MSG_DATA_64_DEFAULT 0x00000000 5666 #define smnBIF_CFG_DEV0_EPF0_VF21_MSI_MASK_64_DEFAULT 0x00000000 5667 #define smnBIF_CFG_DEV0_EPF0_VF21_MSI_PENDING_DEFAULT 0x00000000 5668 #define smnBIF_CFG_DEV0_EPF0_VF21_MSI_PENDING_64_DEFAULT 0x00000000 5669 #define smnBIF_CFG_DEV0_EPF0_VF21_MSIX_CAP_LIST_DEFAULT 0x00000000 5670 #define smnBIF_CFG_DEV0_EPF0_VF21_MSIX_MSG_CNTL_DEFAULT 0x00000000 5671 #define smnBIF_CFG_DEV0_EPF0_VF21_MSIX_TABLE_DEFAULT 0x00000000 5672 #define smnBIF_CFG_DEV0_EPF0_VF21_MSIX_PBA_DEFAULT 0x00000000 5673 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 5674 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 5675 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 5676 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 5677 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 5678 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 5679 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 5680 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 5681 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 5682 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 5683 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 5684 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG0_DEFAULT 0x00000000 5685 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG1_DEFAULT 0x00000000 5686 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG2_DEFAULT 0x00000000 5687 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG3_DEFAULT 0x00000000 5688 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 5689 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 5690 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 5691 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 5692 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 5693 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CAP_DEFAULT 0x00000000 5694 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CNTL_DEFAULT 0x00000000 5695 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 5696 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CAP_DEFAULT 0x00000000 5697 #define smnBIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CNTL_DEFAULT 0x00000000 5698 5699 5700 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf22_bifcfgdecp 5701 #define smnBIF_CFG_DEV0_EPF0_VF22_VENDOR_ID_DEFAULT 0x00000000 5702 #define smnBIF_CFG_DEV0_EPF0_VF22_DEVICE_ID_DEFAULT 0x00000000 5703 #define smnBIF_CFG_DEV0_EPF0_VF22_COMMAND_DEFAULT 0x00000000 5704 #define smnBIF_CFG_DEV0_EPF0_VF22_STATUS_DEFAULT 0x00000000 5705 #define smnBIF_CFG_DEV0_EPF0_VF22_REVISION_ID_DEFAULT 0x00000000 5706 #define smnBIF_CFG_DEV0_EPF0_VF22_PROG_INTERFACE_DEFAULT 0x00000000 5707 #define smnBIF_CFG_DEV0_EPF0_VF22_SUB_CLASS_DEFAULT 0x00000000 5708 #define smnBIF_CFG_DEV0_EPF0_VF22_BASE_CLASS_DEFAULT 0x00000000 5709 #define smnBIF_CFG_DEV0_EPF0_VF22_CACHE_LINE_DEFAULT 0x00000000 5710 #define smnBIF_CFG_DEV0_EPF0_VF22_LATENCY_DEFAULT 0x00000000 5711 #define smnBIF_CFG_DEV0_EPF0_VF22_HEADER_DEFAULT 0x00000000 5712 #define smnBIF_CFG_DEV0_EPF0_VF22_BIST_DEFAULT 0x00000000 5713 #define smnBIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_1_DEFAULT 0x00000000 5714 #define smnBIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_2_DEFAULT 0x00000000 5715 #define smnBIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_3_DEFAULT 0x00000000 5716 #define smnBIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_4_DEFAULT 0x00000000 5717 #define smnBIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_5_DEFAULT 0x00000000 5718 #define smnBIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_6_DEFAULT 0x00000000 5719 #define smnBIF_CFG_DEV0_EPF0_VF22_CARDBUS_CIS_PTR_DEFAULT 0x00000000 5720 #define smnBIF_CFG_DEV0_EPF0_VF22_ADAPTER_ID_DEFAULT 0x73101002 5721 #define smnBIF_CFG_DEV0_EPF0_VF22_ROM_BASE_ADDR_DEFAULT 0x00000000 5722 #define smnBIF_CFG_DEV0_EPF0_VF22_CAP_PTR_DEFAULT 0x00000048 5723 #define smnBIF_CFG_DEV0_EPF0_VF22_INTERRUPT_LINE_DEFAULT 0x00000000 5724 #define smnBIF_CFG_DEV0_EPF0_VF22_INTERRUPT_PIN_DEFAULT 0x00000000 5725 #define smnBIF_CFG_DEV0_EPF0_VF22_MIN_GRANT_DEFAULT 0x00000000 5726 #define smnBIF_CFG_DEV0_EPF0_VF22_MAX_LATENCY_DEFAULT 0x00000000 5727 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_CAP_LIST_DEFAULT 0x0000a000 5728 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_CAP_DEFAULT 0x00000002 5729 #define smnBIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP_DEFAULT 0x00000000 5730 #define smnBIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL_DEFAULT 0x00000000 5731 #define smnBIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS_DEFAULT 0x00000000 5732 #define smnBIF_CFG_DEV0_EPF0_VF22_LINK_CAP_DEFAULT 0x00000d04 5733 #define smnBIF_CFG_DEV0_EPF0_VF22_LINK_CNTL_DEFAULT 0x00000000 5734 #define smnBIF_CFG_DEV0_EPF0_VF22_LINK_STATUS_DEFAULT 0x00000000 5735 #define smnBIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2_DEFAULT 0x00010000 5736 #define smnBIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2_DEFAULT 0x00000000 5737 #define smnBIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS2_DEFAULT 0x00000000 5738 #define smnBIF_CFG_DEV0_EPF0_VF22_LINK_CAP2_DEFAULT 0x0000001e 5739 #define smnBIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2_DEFAULT 0x00000000 5740 #define smnBIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2_DEFAULT 0x00000000 5741 #define smnBIF_CFG_DEV0_EPF0_VF22_MSI_CAP_LIST_DEFAULT 0x0000c000 5742 #define smnBIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL_DEFAULT 0x00000082 5743 #define smnBIF_CFG_DEV0_EPF0_VF22_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 5744 #define smnBIF_CFG_DEV0_EPF0_VF22_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 5745 #define smnBIF_CFG_DEV0_EPF0_VF22_MSI_MSG_DATA_DEFAULT 0x00000000 5746 #define smnBIF_CFG_DEV0_EPF0_VF22_MSI_MASK_DEFAULT 0x00000000 5747 #define smnBIF_CFG_DEV0_EPF0_VF22_MSI_MSG_DATA_64_DEFAULT 0x00000000 5748 #define smnBIF_CFG_DEV0_EPF0_VF22_MSI_MASK_64_DEFAULT 0x00000000 5749 #define smnBIF_CFG_DEV0_EPF0_VF22_MSI_PENDING_DEFAULT 0x00000000 5750 #define smnBIF_CFG_DEV0_EPF0_VF22_MSI_PENDING_64_DEFAULT 0x00000000 5751 #define smnBIF_CFG_DEV0_EPF0_VF22_MSIX_CAP_LIST_DEFAULT 0x00000000 5752 #define smnBIF_CFG_DEV0_EPF0_VF22_MSIX_MSG_CNTL_DEFAULT 0x00000000 5753 #define smnBIF_CFG_DEV0_EPF0_VF22_MSIX_TABLE_DEFAULT 0x00000000 5754 #define smnBIF_CFG_DEV0_EPF0_VF22_MSIX_PBA_DEFAULT 0x00000000 5755 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 5756 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 5757 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 5758 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 5759 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 5760 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 5761 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 5762 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 5763 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 5764 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 5765 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 5766 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG0_DEFAULT 0x00000000 5767 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG1_DEFAULT 0x00000000 5768 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG2_DEFAULT 0x00000000 5769 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG3_DEFAULT 0x00000000 5770 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 5771 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 5772 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 5773 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 5774 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 5775 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CAP_DEFAULT 0x00000000 5776 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CNTL_DEFAULT 0x00000000 5777 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 5778 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CAP_DEFAULT 0x00000000 5779 #define smnBIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CNTL_DEFAULT 0x00000000 5780 5781 5782 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf23_bifcfgdecp 5783 #define smnBIF_CFG_DEV0_EPF0_VF23_VENDOR_ID_DEFAULT 0x00000000 5784 #define smnBIF_CFG_DEV0_EPF0_VF23_DEVICE_ID_DEFAULT 0x00000000 5785 #define smnBIF_CFG_DEV0_EPF0_VF23_COMMAND_DEFAULT 0x00000000 5786 #define smnBIF_CFG_DEV0_EPF0_VF23_STATUS_DEFAULT 0x00000000 5787 #define smnBIF_CFG_DEV0_EPF0_VF23_REVISION_ID_DEFAULT 0x00000000 5788 #define smnBIF_CFG_DEV0_EPF0_VF23_PROG_INTERFACE_DEFAULT 0x00000000 5789 #define smnBIF_CFG_DEV0_EPF0_VF23_SUB_CLASS_DEFAULT 0x00000000 5790 #define smnBIF_CFG_DEV0_EPF0_VF23_BASE_CLASS_DEFAULT 0x00000000 5791 #define smnBIF_CFG_DEV0_EPF0_VF23_CACHE_LINE_DEFAULT 0x00000000 5792 #define smnBIF_CFG_DEV0_EPF0_VF23_LATENCY_DEFAULT 0x00000000 5793 #define smnBIF_CFG_DEV0_EPF0_VF23_HEADER_DEFAULT 0x00000000 5794 #define smnBIF_CFG_DEV0_EPF0_VF23_BIST_DEFAULT 0x00000000 5795 #define smnBIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_1_DEFAULT 0x00000000 5796 #define smnBIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_2_DEFAULT 0x00000000 5797 #define smnBIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_3_DEFAULT 0x00000000 5798 #define smnBIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_4_DEFAULT 0x00000000 5799 #define smnBIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_5_DEFAULT 0x00000000 5800 #define smnBIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_6_DEFAULT 0x00000000 5801 #define smnBIF_CFG_DEV0_EPF0_VF23_CARDBUS_CIS_PTR_DEFAULT 0x00000000 5802 #define smnBIF_CFG_DEV0_EPF0_VF23_ADAPTER_ID_DEFAULT 0x73101002 5803 #define smnBIF_CFG_DEV0_EPF0_VF23_ROM_BASE_ADDR_DEFAULT 0x00000000 5804 #define smnBIF_CFG_DEV0_EPF0_VF23_CAP_PTR_DEFAULT 0x00000048 5805 #define smnBIF_CFG_DEV0_EPF0_VF23_INTERRUPT_LINE_DEFAULT 0x00000000 5806 #define smnBIF_CFG_DEV0_EPF0_VF23_INTERRUPT_PIN_DEFAULT 0x00000000 5807 #define smnBIF_CFG_DEV0_EPF0_VF23_MIN_GRANT_DEFAULT 0x00000000 5808 #define smnBIF_CFG_DEV0_EPF0_VF23_MAX_LATENCY_DEFAULT 0x00000000 5809 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_CAP_LIST_DEFAULT 0x0000a000 5810 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_CAP_DEFAULT 0x00000002 5811 #define smnBIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP_DEFAULT 0x00000000 5812 #define smnBIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL_DEFAULT 0x00000000 5813 #define smnBIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS_DEFAULT 0x00000000 5814 #define smnBIF_CFG_DEV0_EPF0_VF23_LINK_CAP_DEFAULT 0x00000d04 5815 #define smnBIF_CFG_DEV0_EPF0_VF23_LINK_CNTL_DEFAULT 0x00000000 5816 #define smnBIF_CFG_DEV0_EPF0_VF23_LINK_STATUS_DEFAULT 0x00000000 5817 #define smnBIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2_DEFAULT 0x00010000 5818 #define smnBIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2_DEFAULT 0x00000000 5819 #define smnBIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS2_DEFAULT 0x00000000 5820 #define smnBIF_CFG_DEV0_EPF0_VF23_LINK_CAP2_DEFAULT 0x0000001e 5821 #define smnBIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2_DEFAULT 0x00000000 5822 #define smnBIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2_DEFAULT 0x00000000 5823 #define smnBIF_CFG_DEV0_EPF0_VF23_MSI_CAP_LIST_DEFAULT 0x0000c000 5824 #define smnBIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL_DEFAULT 0x00000082 5825 #define smnBIF_CFG_DEV0_EPF0_VF23_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 5826 #define smnBIF_CFG_DEV0_EPF0_VF23_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 5827 #define smnBIF_CFG_DEV0_EPF0_VF23_MSI_MSG_DATA_DEFAULT 0x00000000 5828 #define smnBIF_CFG_DEV0_EPF0_VF23_MSI_MASK_DEFAULT 0x00000000 5829 #define smnBIF_CFG_DEV0_EPF0_VF23_MSI_MSG_DATA_64_DEFAULT 0x00000000 5830 #define smnBIF_CFG_DEV0_EPF0_VF23_MSI_MASK_64_DEFAULT 0x00000000 5831 #define smnBIF_CFG_DEV0_EPF0_VF23_MSI_PENDING_DEFAULT 0x00000000 5832 #define smnBIF_CFG_DEV0_EPF0_VF23_MSI_PENDING_64_DEFAULT 0x00000000 5833 #define smnBIF_CFG_DEV0_EPF0_VF23_MSIX_CAP_LIST_DEFAULT 0x00000000 5834 #define smnBIF_CFG_DEV0_EPF0_VF23_MSIX_MSG_CNTL_DEFAULT 0x00000000 5835 #define smnBIF_CFG_DEV0_EPF0_VF23_MSIX_TABLE_DEFAULT 0x00000000 5836 #define smnBIF_CFG_DEV0_EPF0_VF23_MSIX_PBA_DEFAULT 0x00000000 5837 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 5838 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 5839 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 5840 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 5841 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 5842 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 5843 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 5844 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 5845 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 5846 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 5847 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 5848 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG0_DEFAULT 0x00000000 5849 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG1_DEFAULT 0x00000000 5850 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG2_DEFAULT 0x00000000 5851 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG3_DEFAULT 0x00000000 5852 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 5853 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 5854 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 5855 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 5856 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 5857 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CAP_DEFAULT 0x00000000 5858 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CNTL_DEFAULT 0x00000000 5859 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 5860 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CAP_DEFAULT 0x00000000 5861 #define smnBIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CNTL_DEFAULT 0x00000000 5862 5863 5864 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf24_bifcfgdecp 5865 #define smnBIF_CFG_DEV0_EPF0_VF24_VENDOR_ID_DEFAULT 0x00000000 5866 #define smnBIF_CFG_DEV0_EPF0_VF24_DEVICE_ID_DEFAULT 0x00000000 5867 #define smnBIF_CFG_DEV0_EPF0_VF24_COMMAND_DEFAULT 0x00000000 5868 #define smnBIF_CFG_DEV0_EPF0_VF24_STATUS_DEFAULT 0x00000000 5869 #define smnBIF_CFG_DEV0_EPF0_VF24_REVISION_ID_DEFAULT 0x00000000 5870 #define smnBIF_CFG_DEV0_EPF0_VF24_PROG_INTERFACE_DEFAULT 0x00000000 5871 #define smnBIF_CFG_DEV0_EPF0_VF24_SUB_CLASS_DEFAULT 0x00000000 5872 #define smnBIF_CFG_DEV0_EPF0_VF24_BASE_CLASS_DEFAULT 0x00000000 5873 #define smnBIF_CFG_DEV0_EPF0_VF24_CACHE_LINE_DEFAULT 0x00000000 5874 #define smnBIF_CFG_DEV0_EPF0_VF24_LATENCY_DEFAULT 0x00000000 5875 #define smnBIF_CFG_DEV0_EPF0_VF24_HEADER_DEFAULT 0x00000000 5876 #define smnBIF_CFG_DEV0_EPF0_VF24_BIST_DEFAULT 0x00000000 5877 #define smnBIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_1_DEFAULT 0x00000000 5878 #define smnBIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_2_DEFAULT 0x00000000 5879 #define smnBIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_3_DEFAULT 0x00000000 5880 #define smnBIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_4_DEFAULT 0x00000000 5881 #define smnBIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_5_DEFAULT 0x00000000 5882 #define smnBIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_6_DEFAULT 0x00000000 5883 #define smnBIF_CFG_DEV0_EPF0_VF24_CARDBUS_CIS_PTR_DEFAULT 0x00000000 5884 #define smnBIF_CFG_DEV0_EPF0_VF24_ADAPTER_ID_DEFAULT 0x73101002 5885 #define smnBIF_CFG_DEV0_EPF0_VF24_ROM_BASE_ADDR_DEFAULT 0x00000000 5886 #define smnBIF_CFG_DEV0_EPF0_VF24_CAP_PTR_DEFAULT 0x00000048 5887 #define smnBIF_CFG_DEV0_EPF0_VF24_INTERRUPT_LINE_DEFAULT 0x00000000 5888 #define smnBIF_CFG_DEV0_EPF0_VF24_INTERRUPT_PIN_DEFAULT 0x00000000 5889 #define smnBIF_CFG_DEV0_EPF0_VF24_MIN_GRANT_DEFAULT 0x00000000 5890 #define smnBIF_CFG_DEV0_EPF0_VF24_MAX_LATENCY_DEFAULT 0x00000000 5891 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_CAP_LIST_DEFAULT 0x0000a000 5892 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_CAP_DEFAULT 0x00000002 5893 #define smnBIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP_DEFAULT 0x00000000 5894 #define smnBIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL_DEFAULT 0x00000000 5895 #define smnBIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS_DEFAULT 0x00000000 5896 #define smnBIF_CFG_DEV0_EPF0_VF24_LINK_CAP_DEFAULT 0x00000d04 5897 #define smnBIF_CFG_DEV0_EPF0_VF24_LINK_CNTL_DEFAULT 0x00000000 5898 #define smnBIF_CFG_DEV0_EPF0_VF24_LINK_STATUS_DEFAULT 0x00000000 5899 #define smnBIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2_DEFAULT 0x00010000 5900 #define smnBIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2_DEFAULT 0x00000000 5901 #define smnBIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS2_DEFAULT 0x00000000 5902 #define smnBIF_CFG_DEV0_EPF0_VF24_LINK_CAP2_DEFAULT 0x0000001e 5903 #define smnBIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2_DEFAULT 0x00000000 5904 #define smnBIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2_DEFAULT 0x00000000 5905 #define smnBIF_CFG_DEV0_EPF0_VF24_MSI_CAP_LIST_DEFAULT 0x0000c000 5906 #define smnBIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL_DEFAULT 0x00000082 5907 #define smnBIF_CFG_DEV0_EPF0_VF24_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 5908 #define smnBIF_CFG_DEV0_EPF0_VF24_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 5909 #define smnBIF_CFG_DEV0_EPF0_VF24_MSI_MSG_DATA_DEFAULT 0x00000000 5910 #define smnBIF_CFG_DEV0_EPF0_VF24_MSI_MASK_DEFAULT 0x00000000 5911 #define smnBIF_CFG_DEV0_EPF0_VF24_MSI_MSG_DATA_64_DEFAULT 0x00000000 5912 #define smnBIF_CFG_DEV0_EPF0_VF24_MSI_MASK_64_DEFAULT 0x00000000 5913 #define smnBIF_CFG_DEV0_EPF0_VF24_MSI_PENDING_DEFAULT 0x00000000 5914 #define smnBIF_CFG_DEV0_EPF0_VF24_MSI_PENDING_64_DEFAULT 0x00000000 5915 #define smnBIF_CFG_DEV0_EPF0_VF24_MSIX_CAP_LIST_DEFAULT 0x00000000 5916 #define smnBIF_CFG_DEV0_EPF0_VF24_MSIX_MSG_CNTL_DEFAULT 0x00000000 5917 #define smnBIF_CFG_DEV0_EPF0_VF24_MSIX_TABLE_DEFAULT 0x00000000 5918 #define smnBIF_CFG_DEV0_EPF0_VF24_MSIX_PBA_DEFAULT 0x00000000 5919 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 5920 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 5921 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 5922 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 5923 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 5924 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 5925 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 5926 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 5927 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 5928 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 5929 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 5930 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG0_DEFAULT 0x00000000 5931 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG1_DEFAULT 0x00000000 5932 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG2_DEFAULT 0x00000000 5933 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG3_DEFAULT 0x00000000 5934 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 5935 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 5936 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 5937 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 5938 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 5939 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CAP_DEFAULT 0x00000000 5940 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CNTL_DEFAULT 0x00000000 5941 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 5942 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CAP_DEFAULT 0x00000000 5943 #define smnBIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CNTL_DEFAULT 0x00000000 5944 5945 5946 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf25_bifcfgdecp 5947 #define smnBIF_CFG_DEV0_EPF0_VF25_VENDOR_ID_DEFAULT 0x00000000 5948 #define smnBIF_CFG_DEV0_EPF0_VF25_DEVICE_ID_DEFAULT 0x00000000 5949 #define smnBIF_CFG_DEV0_EPF0_VF25_COMMAND_DEFAULT 0x00000000 5950 #define smnBIF_CFG_DEV0_EPF0_VF25_STATUS_DEFAULT 0x00000000 5951 #define smnBIF_CFG_DEV0_EPF0_VF25_REVISION_ID_DEFAULT 0x00000000 5952 #define smnBIF_CFG_DEV0_EPF0_VF25_PROG_INTERFACE_DEFAULT 0x00000000 5953 #define smnBIF_CFG_DEV0_EPF0_VF25_SUB_CLASS_DEFAULT 0x00000000 5954 #define smnBIF_CFG_DEV0_EPF0_VF25_BASE_CLASS_DEFAULT 0x00000000 5955 #define smnBIF_CFG_DEV0_EPF0_VF25_CACHE_LINE_DEFAULT 0x00000000 5956 #define smnBIF_CFG_DEV0_EPF0_VF25_LATENCY_DEFAULT 0x00000000 5957 #define smnBIF_CFG_DEV0_EPF0_VF25_HEADER_DEFAULT 0x00000000 5958 #define smnBIF_CFG_DEV0_EPF0_VF25_BIST_DEFAULT 0x00000000 5959 #define smnBIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_1_DEFAULT 0x00000000 5960 #define smnBIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_2_DEFAULT 0x00000000 5961 #define smnBIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_3_DEFAULT 0x00000000 5962 #define smnBIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_4_DEFAULT 0x00000000 5963 #define smnBIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_5_DEFAULT 0x00000000 5964 #define smnBIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_6_DEFAULT 0x00000000 5965 #define smnBIF_CFG_DEV0_EPF0_VF25_CARDBUS_CIS_PTR_DEFAULT 0x00000000 5966 #define smnBIF_CFG_DEV0_EPF0_VF25_ADAPTER_ID_DEFAULT 0x73101002 5967 #define smnBIF_CFG_DEV0_EPF0_VF25_ROM_BASE_ADDR_DEFAULT 0x00000000 5968 #define smnBIF_CFG_DEV0_EPF0_VF25_CAP_PTR_DEFAULT 0x00000048 5969 #define smnBIF_CFG_DEV0_EPF0_VF25_INTERRUPT_LINE_DEFAULT 0x00000000 5970 #define smnBIF_CFG_DEV0_EPF0_VF25_INTERRUPT_PIN_DEFAULT 0x00000000 5971 #define smnBIF_CFG_DEV0_EPF0_VF25_MIN_GRANT_DEFAULT 0x00000000 5972 #define smnBIF_CFG_DEV0_EPF0_VF25_MAX_LATENCY_DEFAULT 0x00000000 5973 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_CAP_LIST_DEFAULT 0x0000a000 5974 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_CAP_DEFAULT 0x00000002 5975 #define smnBIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP_DEFAULT 0x00000000 5976 #define smnBIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL_DEFAULT 0x00000000 5977 #define smnBIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS_DEFAULT 0x00000000 5978 #define smnBIF_CFG_DEV0_EPF0_VF25_LINK_CAP_DEFAULT 0x00000d04 5979 #define smnBIF_CFG_DEV0_EPF0_VF25_LINK_CNTL_DEFAULT 0x00000000 5980 #define smnBIF_CFG_DEV0_EPF0_VF25_LINK_STATUS_DEFAULT 0x00000000 5981 #define smnBIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2_DEFAULT 0x00010000 5982 #define smnBIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2_DEFAULT 0x00000000 5983 #define smnBIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS2_DEFAULT 0x00000000 5984 #define smnBIF_CFG_DEV0_EPF0_VF25_LINK_CAP2_DEFAULT 0x0000001e 5985 #define smnBIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2_DEFAULT 0x00000000 5986 #define smnBIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2_DEFAULT 0x00000000 5987 #define smnBIF_CFG_DEV0_EPF0_VF25_MSI_CAP_LIST_DEFAULT 0x0000c000 5988 #define smnBIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL_DEFAULT 0x00000082 5989 #define smnBIF_CFG_DEV0_EPF0_VF25_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 5990 #define smnBIF_CFG_DEV0_EPF0_VF25_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 5991 #define smnBIF_CFG_DEV0_EPF0_VF25_MSI_MSG_DATA_DEFAULT 0x00000000 5992 #define smnBIF_CFG_DEV0_EPF0_VF25_MSI_MASK_DEFAULT 0x00000000 5993 #define smnBIF_CFG_DEV0_EPF0_VF25_MSI_MSG_DATA_64_DEFAULT 0x00000000 5994 #define smnBIF_CFG_DEV0_EPF0_VF25_MSI_MASK_64_DEFAULT 0x00000000 5995 #define smnBIF_CFG_DEV0_EPF0_VF25_MSI_PENDING_DEFAULT 0x00000000 5996 #define smnBIF_CFG_DEV0_EPF0_VF25_MSI_PENDING_64_DEFAULT 0x00000000 5997 #define smnBIF_CFG_DEV0_EPF0_VF25_MSIX_CAP_LIST_DEFAULT 0x00000000 5998 #define smnBIF_CFG_DEV0_EPF0_VF25_MSIX_MSG_CNTL_DEFAULT 0x00000000 5999 #define smnBIF_CFG_DEV0_EPF0_VF25_MSIX_TABLE_DEFAULT 0x00000000 6000 #define smnBIF_CFG_DEV0_EPF0_VF25_MSIX_PBA_DEFAULT 0x00000000 6001 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 6002 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 6003 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 6004 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 6005 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 6006 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 6007 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 6008 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 6009 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 6010 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 6011 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 6012 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG0_DEFAULT 0x00000000 6013 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG1_DEFAULT 0x00000000 6014 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG2_DEFAULT 0x00000000 6015 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG3_DEFAULT 0x00000000 6016 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 6017 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 6018 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 6019 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 6020 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 6021 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CAP_DEFAULT 0x00000000 6022 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CNTL_DEFAULT 0x00000000 6023 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 6024 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CAP_DEFAULT 0x00000000 6025 #define smnBIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CNTL_DEFAULT 0x00000000 6026 6027 6028 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf26_bifcfgdecp 6029 #define smnBIF_CFG_DEV0_EPF0_VF26_VENDOR_ID_DEFAULT 0x00000000 6030 #define smnBIF_CFG_DEV0_EPF0_VF26_DEVICE_ID_DEFAULT 0x00000000 6031 #define smnBIF_CFG_DEV0_EPF0_VF26_COMMAND_DEFAULT 0x00000000 6032 #define smnBIF_CFG_DEV0_EPF0_VF26_STATUS_DEFAULT 0x00000000 6033 #define smnBIF_CFG_DEV0_EPF0_VF26_REVISION_ID_DEFAULT 0x00000000 6034 #define smnBIF_CFG_DEV0_EPF0_VF26_PROG_INTERFACE_DEFAULT 0x00000000 6035 #define smnBIF_CFG_DEV0_EPF0_VF26_SUB_CLASS_DEFAULT 0x00000000 6036 #define smnBIF_CFG_DEV0_EPF0_VF26_BASE_CLASS_DEFAULT 0x00000000 6037 #define smnBIF_CFG_DEV0_EPF0_VF26_CACHE_LINE_DEFAULT 0x00000000 6038 #define smnBIF_CFG_DEV0_EPF0_VF26_LATENCY_DEFAULT 0x00000000 6039 #define smnBIF_CFG_DEV0_EPF0_VF26_HEADER_DEFAULT 0x00000000 6040 #define smnBIF_CFG_DEV0_EPF0_VF26_BIST_DEFAULT 0x00000000 6041 #define smnBIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_1_DEFAULT 0x00000000 6042 #define smnBIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_2_DEFAULT 0x00000000 6043 #define smnBIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_3_DEFAULT 0x00000000 6044 #define smnBIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_4_DEFAULT 0x00000000 6045 #define smnBIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_5_DEFAULT 0x00000000 6046 #define smnBIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_6_DEFAULT 0x00000000 6047 #define smnBIF_CFG_DEV0_EPF0_VF26_CARDBUS_CIS_PTR_DEFAULT 0x00000000 6048 #define smnBIF_CFG_DEV0_EPF0_VF26_ADAPTER_ID_DEFAULT 0x73101002 6049 #define smnBIF_CFG_DEV0_EPF0_VF26_ROM_BASE_ADDR_DEFAULT 0x00000000 6050 #define smnBIF_CFG_DEV0_EPF0_VF26_CAP_PTR_DEFAULT 0x00000048 6051 #define smnBIF_CFG_DEV0_EPF0_VF26_INTERRUPT_LINE_DEFAULT 0x00000000 6052 #define smnBIF_CFG_DEV0_EPF0_VF26_INTERRUPT_PIN_DEFAULT 0x00000000 6053 #define smnBIF_CFG_DEV0_EPF0_VF26_MIN_GRANT_DEFAULT 0x00000000 6054 #define smnBIF_CFG_DEV0_EPF0_VF26_MAX_LATENCY_DEFAULT 0x00000000 6055 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_CAP_LIST_DEFAULT 0x0000a000 6056 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_CAP_DEFAULT 0x00000002 6057 #define smnBIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP_DEFAULT 0x00000000 6058 #define smnBIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL_DEFAULT 0x00000000 6059 #define smnBIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS_DEFAULT 0x00000000 6060 #define smnBIF_CFG_DEV0_EPF0_VF26_LINK_CAP_DEFAULT 0x00000d04 6061 #define smnBIF_CFG_DEV0_EPF0_VF26_LINK_CNTL_DEFAULT 0x00000000 6062 #define smnBIF_CFG_DEV0_EPF0_VF26_LINK_STATUS_DEFAULT 0x00000000 6063 #define smnBIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2_DEFAULT 0x00010000 6064 #define smnBIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2_DEFAULT 0x00000000 6065 #define smnBIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS2_DEFAULT 0x00000000 6066 #define smnBIF_CFG_DEV0_EPF0_VF26_LINK_CAP2_DEFAULT 0x0000001e 6067 #define smnBIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2_DEFAULT 0x00000000 6068 #define smnBIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2_DEFAULT 0x00000000 6069 #define smnBIF_CFG_DEV0_EPF0_VF26_MSI_CAP_LIST_DEFAULT 0x0000c000 6070 #define smnBIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL_DEFAULT 0x00000082 6071 #define smnBIF_CFG_DEV0_EPF0_VF26_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 6072 #define smnBIF_CFG_DEV0_EPF0_VF26_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 6073 #define smnBIF_CFG_DEV0_EPF0_VF26_MSI_MSG_DATA_DEFAULT 0x00000000 6074 #define smnBIF_CFG_DEV0_EPF0_VF26_MSI_MASK_DEFAULT 0x00000000 6075 #define smnBIF_CFG_DEV0_EPF0_VF26_MSI_MSG_DATA_64_DEFAULT 0x00000000 6076 #define smnBIF_CFG_DEV0_EPF0_VF26_MSI_MASK_64_DEFAULT 0x00000000 6077 #define smnBIF_CFG_DEV0_EPF0_VF26_MSI_PENDING_DEFAULT 0x00000000 6078 #define smnBIF_CFG_DEV0_EPF0_VF26_MSI_PENDING_64_DEFAULT 0x00000000 6079 #define smnBIF_CFG_DEV0_EPF0_VF26_MSIX_CAP_LIST_DEFAULT 0x00000000 6080 #define smnBIF_CFG_DEV0_EPF0_VF26_MSIX_MSG_CNTL_DEFAULT 0x00000000 6081 #define smnBIF_CFG_DEV0_EPF0_VF26_MSIX_TABLE_DEFAULT 0x00000000 6082 #define smnBIF_CFG_DEV0_EPF0_VF26_MSIX_PBA_DEFAULT 0x00000000 6083 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 6084 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 6085 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 6086 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 6087 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 6088 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 6089 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 6090 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 6091 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 6092 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 6093 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 6094 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG0_DEFAULT 0x00000000 6095 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG1_DEFAULT 0x00000000 6096 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG2_DEFAULT 0x00000000 6097 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG3_DEFAULT 0x00000000 6098 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 6099 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 6100 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 6101 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 6102 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 6103 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CAP_DEFAULT 0x00000000 6104 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CNTL_DEFAULT 0x00000000 6105 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 6106 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CAP_DEFAULT 0x00000000 6107 #define smnBIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CNTL_DEFAULT 0x00000000 6108 6109 6110 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf27_bifcfgdecp 6111 #define smnBIF_CFG_DEV0_EPF0_VF27_VENDOR_ID_DEFAULT 0x00000000 6112 #define smnBIF_CFG_DEV0_EPF0_VF27_DEVICE_ID_DEFAULT 0x00000000 6113 #define smnBIF_CFG_DEV0_EPF0_VF27_COMMAND_DEFAULT 0x00000000 6114 #define smnBIF_CFG_DEV0_EPF0_VF27_STATUS_DEFAULT 0x00000000 6115 #define smnBIF_CFG_DEV0_EPF0_VF27_REVISION_ID_DEFAULT 0x00000000 6116 #define smnBIF_CFG_DEV0_EPF0_VF27_PROG_INTERFACE_DEFAULT 0x00000000 6117 #define smnBIF_CFG_DEV0_EPF0_VF27_SUB_CLASS_DEFAULT 0x00000000 6118 #define smnBIF_CFG_DEV0_EPF0_VF27_BASE_CLASS_DEFAULT 0x00000000 6119 #define smnBIF_CFG_DEV0_EPF0_VF27_CACHE_LINE_DEFAULT 0x00000000 6120 #define smnBIF_CFG_DEV0_EPF0_VF27_LATENCY_DEFAULT 0x00000000 6121 #define smnBIF_CFG_DEV0_EPF0_VF27_HEADER_DEFAULT 0x00000000 6122 #define smnBIF_CFG_DEV0_EPF0_VF27_BIST_DEFAULT 0x00000000 6123 #define smnBIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_1_DEFAULT 0x00000000 6124 #define smnBIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_2_DEFAULT 0x00000000 6125 #define smnBIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_3_DEFAULT 0x00000000 6126 #define smnBIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_4_DEFAULT 0x00000000 6127 #define smnBIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_5_DEFAULT 0x00000000 6128 #define smnBIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_6_DEFAULT 0x00000000 6129 #define smnBIF_CFG_DEV0_EPF0_VF27_CARDBUS_CIS_PTR_DEFAULT 0x00000000 6130 #define smnBIF_CFG_DEV0_EPF0_VF27_ADAPTER_ID_DEFAULT 0x73101002 6131 #define smnBIF_CFG_DEV0_EPF0_VF27_ROM_BASE_ADDR_DEFAULT 0x00000000 6132 #define smnBIF_CFG_DEV0_EPF0_VF27_CAP_PTR_DEFAULT 0x00000048 6133 #define smnBIF_CFG_DEV0_EPF0_VF27_INTERRUPT_LINE_DEFAULT 0x00000000 6134 #define smnBIF_CFG_DEV0_EPF0_VF27_INTERRUPT_PIN_DEFAULT 0x00000000 6135 #define smnBIF_CFG_DEV0_EPF0_VF27_MIN_GRANT_DEFAULT 0x00000000 6136 #define smnBIF_CFG_DEV0_EPF0_VF27_MAX_LATENCY_DEFAULT 0x00000000 6137 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_CAP_LIST_DEFAULT 0x0000a000 6138 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_CAP_DEFAULT 0x00000002 6139 #define smnBIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP_DEFAULT 0x00000000 6140 #define smnBIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL_DEFAULT 0x00000000 6141 #define smnBIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS_DEFAULT 0x00000000 6142 #define smnBIF_CFG_DEV0_EPF0_VF27_LINK_CAP_DEFAULT 0x00000d04 6143 #define smnBIF_CFG_DEV0_EPF0_VF27_LINK_CNTL_DEFAULT 0x00000000 6144 #define smnBIF_CFG_DEV0_EPF0_VF27_LINK_STATUS_DEFAULT 0x00000000 6145 #define smnBIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2_DEFAULT 0x00010000 6146 #define smnBIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2_DEFAULT 0x00000000 6147 #define smnBIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS2_DEFAULT 0x00000000 6148 #define smnBIF_CFG_DEV0_EPF0_VF27_LINK_CAP2_DEFAULT 0x0000001e 6149 #define smnBIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2_DEFAULT 0x00000000 6150 #define smnBIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2_DEFAULT 0x00000000 6151 #define smnBIF_CFG_DEV0_EPF0_VF27_MSI_CAP_LIST_DEFAULT 0x0000c000 6152 #define smnBIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL_DEFAULT 0x00000082 6153 #define smnBIF_CFG_DEV0_EPF0_VF27_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 6154 #define smnBIF_CFG_DEV0_EPF0_VF27_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 6155 #define smnBIF_CFG_DEV0_EPF0_VF27_MSI_MSG_DATA_DEFAULT 0x00000000 6156 #define smnBIF_CFG_DEV0_EPF0_VF27_MSI_MASK_DEFAULT 0x00000000 6157 #define smnBIF_CFG_DEV0_EPF0_VF27_MSI_MSG_DATA_64_DEFAULT 0x00000000 6158 #define smnBIF_CFG_DEV0_EPF0_VF27_MSI_MASK_64_DEFAULT 0x00000000 6159 #define smnBIF_CFG_DEV0_EPF0_VF27_MSI_PENDING_DEFAULT 0x00000000 6160 #define smnBIF_CFG_DEV0_EPF0_VF27_MSI_PENDING_64_DEFAULT 0x00000000 6161 #define smnBIF_CFG_DEV0_EPF0_VF27_MSIX_CAP_LIST_DEFAULT 0x00000000 6162 #define smnBIF_CFG_DEV0_EPF0_VF27_MSIX_MSG_CNTL_DEFAULT 0x00000000 6163 #define smnBIF_CFG_DEV0_EPF0_VF27_MSIX_TABLE_DEFAULT 0x00000000 6164 #define smnBIF_CFG_DEV0_EPF0_VF27_MSIX_PBA_DEFAULT 0x00000000 6165 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 6166 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 6167 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 6168 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 6169 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 6170 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 6171 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 6172 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 6173 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 6174 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 6175 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 6176 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG0_DEFAULT 0x00000000 6177 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG1_DEFAULT 0x00000000 6178 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG2_DEFAULT 0x00000000 6179 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG3_DEFAULT 0x00000000 6180 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 6181 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 6182 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 6183 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 6184 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 6185 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CAP_DEFAULT 0x00000000 6186 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CNTL_DEFAULT 0x00000000 6187 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 6188 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CAP_DEFAULT 0x00000000 6189 #define smnBIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CNTL_DEFAULT 0x00000000 6190 6191 6192 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf28_bifcfgdecp 6193 #define smnBIF_CFG_DEV0_EPF0_VF28_VENDOR_ID_DEFAULT 0x00000000 6194 #define smnBIF_CFG_DEV0_EPF0_VF28_DEVICE_ID_DEFAULT 0x00000000 6195 #define smnBIF_CFG_DEV0_EPF0_VF28_COMMAND_DEFAULT 0x00000000 6196 #define smnBIF_CFG_DEV0_EPF0_VF28_STATUS_DEFAULT 0x00000000 6197 #define smnBIF_CFG_DEV0_EPF0_VF28_REVISION_ID_DEFAULT 0x00000000 6198 #define smnBIF_CFG_DEV0_EPF0_VF28_PROG_INTERFACE_DEFAULT 0x00000000 6199 #define smnBIF_CFG_DEV0_EPF0_VF28_SUB_CLASS_DEFAULT 0x00000000 6200 #define smnBIF_CFG_DEV0_EPF0_VF28_BASE_CLASS_DEFAULT 0x00000000 6201 #define smnBIF_CFG_DEV0_EPF0_VF28_CACHE_LINE_DEFAULT 0x00000000 6202 #define smnBIF_CFG_DEV0_EPF0_VF28_LATENCY_DEFAULT 0x00000000 6203 #define smnBIF_CFG_DEV0_EPF0_VF28_HEADER_DEFAULT 0x00000000 6204 #define smnBIF_CFG_DEV0_EPF0_VF28_BIST_DEFAULT 0x00000000 6205 #define smnBIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_1_DEFAULT 0x00000000 6206 #define smnBIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_2_DEFAULT 0x00000000 6207 #define smnBIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_3_DEFAULT 0x00000000 6208 #define smnBIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_4_DEFAULT 0x00000000 6209 #define smnBIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_5_DEFAULT 0x00000000 6210 #define smnBIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_6_DEFAULT 0x00000000 6211 #define smnBIF_CFG_DEV0_EPF0_VF28_CARDBUS_CIS_PTR_DEFAULT 0x00000000 6212 #define smnBIF_CFG_DEV0_EPF0_VF28_ADAPTER_ID_DEFAULT 0x73101002 6213 #define smnBIF_CFG_DEV0_EPF0_VF28_ROM_BASE_ADDR_DEFAULT 0x00000000 6214 #define smnBIF_CFG_DEV0_EPF0_VF28_CAP_PTR_DEFAULT 0x00000048 6215 #define smnBIF_CFG_DEV0_EPF0_VF28_INTERRUPT_LINE_DEFAULT 0x00000000 6216 #define smnBIF_CFG_DEV0_EPF0_VF28_INTERRUPT_PIN_DEFAULT 0x00000000 6217 #define smnBIF_CFG_DEV0_EPF0_VF28_MIN_GRANT_DEFAULT 0x00000000 6218 #define smnBIF_CFG_DEV0_EPF0_VF28_MAX_LATENCY_DEFAULT 0x00000000 6219 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_CAP_LIST_DEFAULT 0x0000a000 6220 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_CAP_DEFAULT 0x00000002 6221 #define smnBIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP_DEFAULT 0x00000000 6222 #define smnBIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL_DEFAULT 0x00000000 6223 #define smnBIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS_DEFAULT 0x00000000 6224 #define smnBIF_CFG_DEV0_EPF0_VF28_LINK_CAP_DEFAULT 0x00000d04 6225 #define smnBIF_CFG_DEV0_EPF0_VF28_LINK_CNTL_DEFAULT 0x00000000 6226 #define smnBIF_CFG_DEV0_EPF0_VF28_LINK_STATUS_DEFAULT 0x00000000 6227 #define smnBIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2_DEFAULT 0x00010000 6228 #define smnBIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2_DEFAULT 0x00000000 6229 #define smnBIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS2_DEFAULT 0x00000000 6230 #define smnBIF_CFG_DEV0_EPF0_VF28_LINK_CAP2_DEFAULT 0x0000001e 6231 #define smnBIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2_DEFAULT 0x00000000 6232 #define smnBIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2_DEFAULT 0x00000000 6233 #define smnBIF_CFG_DEV0_EPF0_VF28_MSI_CAP_LIST_DEFAULT 0x0000c000 6234 #define smnBIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL_DEFAULT 0x00000082 6235 #define smnBIF_CFG_DEV0_EPF0_VF28_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 6236 #define smnBIF_CFG_DEV0_EPF0_VF28_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 6237 #define smnBIF_CFG_DEV0_EPF0_VF28_MSI_MSG_DATA_DEFAULT 0x00000000 6238 #define smnBIF_CFG_DEV0_EPF0_VF28_MSI_MASK_DEFAULT 0x00000000 6239 #define smnBIF_CFG_DEV0_EPF0_VF28_MSI_MSG_DATA_64_DEFAULT 0x00000000 6240 #define smnBIF_CFG_DEV0_EPF0_VF28_MSI_MASK_64_DEFAULT 0x00000000 6241 #define smnBIF_CFG_DEV0_EPF0_VF28_MSI_PENDING_DEFAULT 0x00000000 6242 #define smnBIF_CFG_DEV0_EPF0_VF28_MSI_PENDING_64_DEFAULT 0x00000000 6243 #define smnBIF_CFG_DEV0_EPF0_VF28_MSIX_CAP_LIST_DEFAULT 0x00000000 6244 #define smnBIF_CFG_DEV0_EPF0_VF28_MSIX_MSG_CNTL_DEFAULT 0x00000000 6245 #define smnBIF_CFG_DEV0_EPF0_VF28_MSIX_TABLE_DEFAULT 0x00000000 6246 #define smnBIF_CFG_DEV0_EPF0_VF28_MSIX_PBA_DEFAULT 0x00000000 6247 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 6248 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 6249 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 6250 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 6251 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 6252 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 6253 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 6254 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 6255 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 6256 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 6257 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 6258 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG0_DEFAULT 0x00000000 6259 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG1_DEFAULT 0x00000000 6260 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG2_DEFAULT 0x00000000 6261 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG3_DEFAULT 0x00000000 6262 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 6263 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 6264 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 6265 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 6266 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 6267 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CAP_DEFAULT 0x00000000 6268 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CNTL_DEFAULT 0x00000000 6269 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 6270 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CAP_DEFAULT 0x00000000 6271 #define smnBIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CNTL_DEFAULT 0x00000000 6272 6273 6274 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf29_bifcfgdecp 6275 #define smnBIF_CFG_DEV0_EPF0_VF29_VENDOR_ID_DEFAULT 0x00000000 6276 #define smnBIF_CFG_DEV0_EPF0_VF29_DEVICE_ID_DEFAULT 0x00000000 6277 #define smnBIF_CFG_DEV0_EPF0_VF29_COMMAND_DEFAULT 0x00000000 6278 #define smnBIF_CFG_DEV0_EPF0_VF29_STATUS_DEFAULT 0x00000000 6279 #define smnBIF_CFG_DEV0_EPF0_VF29_REVISION_ID_DEFAULT 0x00000000 6280 #define smnBIF_CFG_DEV0_EPF0_VF29_PROG_INTERFACE_DEFAULT 0x00000000 6281 #define smnBIF_CFG_DEV0_EPF0_VF29_SUB_CLASS_DEFAULT 0x00000000 6282 #define smnBIF_CFG_DEV0_EPF0_VF29_BASE_CLASS_DEFAULT 0x00000000 6283 #define smnBIF_CFG_DEV0_EPF0_VF29_CACHE_LINE_DEFAULT 0x00000000 6284 #define smnBIF_CFG_DEV0_EPF0_VF29_LATENCY_DEFAULT 0x00000000 6285 #define smnBIF_CFG_DEV0_EPF0_VF29_HEADER_DEFAULT 0x00000000 6286 #define smnBIF_CFG_DEV0_EPF0_VF29_BIST_DEFAULT 0x00000000 6287 #define smnBIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_1_DEFAULT 0x00000000 6288 #define smnBIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_2_DEFAULT 0x00000000 6289 #define smnBIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_3_DEFAULT 0x00000000 6290 #define smnBIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_4_DEFAULT 0x00000000 6291 #define smnBIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_5_DEFAULT 0x00000000 6292 #define smnBIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_6_DEFAULT 0x00000000 6293 #define smnBIF_CFG_DEV0_EPF0_VF29_CARDBUS_CIS_PTR_DEFAULT 0x00000000 6294 #define smnBIF_CFG_DEV0_EPF0_VF29_ADAPTER_ID_DEFAULT 0x73101002 6295 #define smnBIF_CFG_DEV0_EPF0_VF29_ROM_BASE_ADDR_DEFAULT 0x00000000 6296 #define smnBIF_CFG_DEV0_EPF0_VF29_CAP_PTR_DEFAULT 0x00000048 6297 #define smnBIF_CFG_DEV0_EPF0_VF29_INTERRUPT_LINE_DEFAULT 0x00000000 6298 #define smnBIF_CFG_DEV0_EPF0_VF29_INTERRUPT_PIN_DEFAULT 0x00000000 6299 #define smnBIF_CFG_DEV0_EPF0_VF29_MIN_GRANT_DEFAULT 0x00000000 6300 #define smnBIF_CFG_DEV0_EPF0_VF29_MAX_LATENCY_DEFAULT 0x00000000 6301 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_CAP_LIST_DEFAULT 0x0000a000 6302 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_CAP_DEFAULT 0x00000002 6303 #define smnBIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP_DEFAULT 0x00000000 6304 #define smnBIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL_DEFAULT 0x00000000 6305 #define smnBIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS_DEFAULT 0x00000000 6306 #define smnBIF_CFG_DEV0_EPF0_VF29_LINK_CAP_DEFAULT 0x00000d04 6307 #define smnBIF_CFG_DEV0_EPF0_VF29_LINK_CNTL_DEFAULT 0x00000000 6308 #define smnBIF_CFG_DEV0_EPF0_VF29_LINK_STATUS_DEFAULT 0x00000000 6309 #define smnBIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2_DEFAULT 0x00010000 6310 #define smnBIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2_DEFAULT 0x00000000 6311 #define smnBIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS2_DEFAULT 0x00000000 6312 #define smnBIF_CFG_DEV0_EPF0_VF29_LINK_CAP2_DEFAULT 0x0000001e 6313 #define smnBIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2_DEFAULT 0x00000000 6314 #define smnBIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2_DEFAULT 0x00000000 6315 #define smnBIF_CFG_DEV0_EPF0_VF29_MSI_CAP_LIST_DEFAULT 0x0000c000 6316 #define smnBIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL_DEFAULT 0x00000082 6317 #define smnBIF_CFG_DEV0_EPF0_VF29_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 6318 #define smnBIF_CFG_DEV0_EPF0_VF29_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 6319 #define smnBIF_CFG_DEV0_EPF0_VF29_MSI_MSG_DATA_DEFAULT 0x00000000 6320 #define smnBIF_CFG_DEV0_EPF0_VF29_MSI_MASK_DEFAULT 0x00000000 6321 #define smnBIF_CFG_DEV0_EPF0_VF29_MSI_MSG_DATA_64_DEFAULT 0x00000000 6322 #define smnBIF_CFG_DEV0_EPF0_VF29_MSI_MASK_64_DEFAULT 0x00000000 6323 #define smnBIF_CFG_DEV0_EPF0_VF29_MSI_PENDING_DEFAULT 0x00000000 6324 #define smnBIF_CFG_DEV0_EPF0_VF29_MSI_PENDING_64_DEFAULT 0x00000000 6325 #define smnBIF_CFG_DEV0_EPF0_VF29_MSIX_CAP_LIST_DEFAULT 0x00000000 6326 #define smnBIF_CFG_DEV0_EPF0_VF29_MSIX_MSG_CNTL_DEFAULT 0x00000000 6327 #define smnBIF_CFG_DEV0_EPF0_VF29_MSIX_TABLE_DEFAULT 0x00000000 6328 #define smnBIF_CFG_DEV0_EPF0_VF29_MSIX_PBA_DEFAULT 0x00000000 6329 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 6330 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 6331 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 6332 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 6333 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 6334 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 6335 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 6336 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 6337 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 6338 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 6339 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 6340 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG0_DEFAULT 0x00000000 6341 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG1_DEFAULT 0x00000000 6342 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG2_DEFAULT 0x00000000 6343 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG3_DEFAULT 0x00000000 6344 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 6345 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 6346 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 6347 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 6348 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 6349 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CAP_DEFAULT 0x00000000 6350 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CNTL_DEFAULT 0x00000000 6351 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 6352 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CAP_DEFAULT 0x00000000 6353 #define smnBIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CNTL_DEFAULT 0x00000000 6354 6355 6356 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf30_bifcfgdecp 6357 #define smnBIF_CFG_DEV0_EPF0_VF30_VENDOR_ID_DEFAULT 0x00000000 6358 #define smnBIF_CFG_DEV0_EPF0_VF30_DEVICE_ID_DEFAULT 0x00000000 6359 #define smnBIF_CFG_DEV0_EPF0_VF30_COMMAND_DEFAULT 0x00000000 6360 #define smnBIF_CFG_DEV0_EPF0_VF30_STATUS_DEFAULT 0x00000000 6361 #define smnBIF_CFG_DEV0_EPF0_VF30_REVISION_ID_DEFAULT 0x00000000 6362 #define smnBIF_CFG_DEV0_EPF0_VF30_PROG_INTERFACE_DEFAULT 0x00000000 6363 #define smnBIF_CFG_DEV0_EPF0_VF30_SUB_CLASS_DEFAULT 0x00000000 6364 #define smnBIF_CFG_DEV0_EPF0_VF30_BASE_CLASS_DEFAULT 0x00000000 6365 #define smnBIF_CFG_DEV0_EPF0_VF30_CACHE_LINE_DEFAULT 0x00000000 6366 #define smnBIF_CFG_DEV0_EPF0_VF30_LATENCY_DEFAULT 0x00000000 6367 #define smnBIF_CFG_DEV0_EPF0_VF30_HEADER_DEFAULT 0x00000000 6368 #define smnBIF_CFG_DEV0_EPF0_VF30_BIST_DEFAULT 0x00000000 6369 #define smnBIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_1_DEFAULT 0x00000000 6370 #define smnBIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_2_DEFAULT 0x00000000 6371 #define smnBIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_3_DEFAULT 0x00000000 6372 #define smnBIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_4_DEFAULT 0x00000000 6373 #define smnBIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_5_DEFAULT 0x00000000 6374 #define smnBIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_6_DEFAULT 0x00000000 6375 #define smnBIF_CFG_DEV0_EPF0_VF30_CARDBUS_CIS_PTR_DEFAULT 0x00000000 6376 #define smnBIF_CFG_DEV0_EPF0_VF30_ADAPTER_ID_DEFAULT 0x73101002 6377 #define smnBIF_CFG_DEV0_EPF0_VF30_ROM_BASE_ADDR_DEFAULT 0x00000000 6378 #define smnBIF_CFG_DEV0_EPF0_VF30_CAP_PTR_DEFAULT 0x00000048 6379 #define smnBIF_CFG_DEV0_EPF0_VF30_INTERRUPT_LINE_DEFAULT 0x00000000 6380 #define smnBIF_CFG_DEV0_EPF0_VF30_INTERRUPT_PIN_DEFAULT 0x00000000 6381 #define smnBIF_CFG_DEV0_EPF0_VF30_MIN_GRANT_DEFAULT 0x00000000 6382 #define smnBIF_CFG_DEV0_EPF0_VF30_MAX_LATENCY_DEFAULT 0x00000000 6383 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_CAP_LIST_DEFAULT 0x0000a000 6384 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_CAP_DEFAULT 0x00000002 6385 #define smnBIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP_DEFAULT 0x00000000 6386 #define smnBIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL_DEFAULT 0x00000000 6387 #define smnBIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS_DEFAULT 0x00000000 6388 #define smnBIF_CFG_DEV0_EPF0_VF30_LINK_CAP_DEFAULT 0x00000d04 6389 #define smnBIF_CFG_DEV0_EPF0_VF30_LINK_CNTL_DEFAULT 0x00000000 6390 #define smnBIF_CFG_DEV0_EPF0_VF30_LINK_STATUS_DEFAULT 0x00000000 6391 #define smnBIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2_DEFAULT 0x00010000 6392 #define smnBIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2_DEFAULT 0x00000000 6393 #define smnBIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS2_DEFAULT 0x00000000 6394 #define smnBIF_CFG_DEV0_EPF0_VF30_LINK_CAP2_DEFAULT 0x0000001e 6395 #define smnBIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2_DEFAULT 0x00000000 6396 #define smnBIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2_DEFAULT 0x00000000 6397 #define smnBIF_CFG_DEV0_EPF0_VF30_MSI_CAP_LIST_DEFAULT 0x0000c000 6398 #define smnBIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL_DEFAULT 0x00000082 6399 #define smnBIF_CFG_DEV0_EPF0_VF30_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 6400 #define smnBIF_CFG_DEV0_EPF0_VF30_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 6401 #define smnBIF_CFG_DEV0_EPF0_VF30_MSI_MSG_DATA_DEFAULT 0x00000000 6402 #define smnBIF_CFG_DEV0_EPF0_VF30_MSI_MASK_DEFAULT 0x00000000 6403 #define smnBIF_CFG_DEV0_EPF0_VF30_MSI_MSG_DATA_64_DEFAULT 0x00000000 6404 #define smnBIF_CFG_DEV0_EPF0_VF30_MSI_MASK_64_DEFAULT 0x00000000 6405 #define smnBIF_CFG_DEV0_EPF0_VF30_MSI_PENDING_DEFAULT 0x00000000 6406 #define smnBIF_CFG_DEV0_EPF0_VF30_MSI_PENDING_64_DEFAULT 0x00000000 6407 #define smnBIF_CFG_DEV0_EPF0_VF30_MSIX_CAP_LIST_DEFAULT 0x00000000 6408 #define smnBIF_CFG_DEV0_EPF0_VF30_MSIX_MSG_CNTL_DEFAULT 0x00000000 6409 #define smnBIF_CFG_DEV0_EPF0_VF30_MSIX_TABLE_DEFAULT 0x00000000 6410 #define smnBIF_CFG_DEV0_EPF0_VF30_MSIX_PBA_DEFAULT 0x00000000 6411 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 6412 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 6413 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 6414 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 6415 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 6416 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 6417 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 6418 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 6419 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 6420 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 6421 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 6422 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG0_DEFAULT 0x00000000 6423 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG1_DEFAULT 0x00000000 6424 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG2_DEFAULT 0x00000000 6425 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG3_DEFAULT 0x00000000 6426 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 6427 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 6428 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 6429 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 6430 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 6431 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CAP_DEFAULT 0x00000000 6432 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CNTL_DEFAULT 0x00000000 6433 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 6434 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CAP_DEFAULT 0x00000000 6435 #define smnBIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CNTL_DEFAULT 0x00000000 6436 6437 6438 // addressBlock: nbio_nbif0_pciemsix_0_usb_MSIXTDEC 6439 #define smnPCIEMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 6440 #define smnPCIEMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 6441 #define smnPCIEMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 6442 #define smnPCIEMSIX_VECT0_CONTROL_DEFAULT 0x00000000 6443 #define smnPCIEMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 6444 #define smnPCIEMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 6445 #define smnPCIEMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 6446 #define smnPCIEMSIX_VECT1_CONTROL_DEFAULT 0x00000000 6447 #define smnPCIEMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 6448 #define smnPCIEMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 6449 #define smnPCIEMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 6450 #define smnPCIEMSIX_VECT2_CONTROL_DEFAULT 0x00000000 6451 #define smnPCIEMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 6452 #define smnPCIEMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 6453 #define smnPCIEMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 6454 #define smnPCIEMSIX_VECT3_CONTROL_DEFAULT 0x00000000 6455 #define smnPCIEMSIX_VECT4_ADDR_LO_DEFAULT 0x00000000 6456 #define smnPCIEMSIX_VECT4_ADDR_HI_DEFAULT 0x00000000 6457 #define smnPCIEMSIX_VECT4_MSG_DATA_DEFAULT 0x00000000 6458 #define smnPCIEMSIX_VECT4_CONTROL_DEFAULT 0x00000000 6459 #define smnPCIEMSIX_VECT5_ADDR_LO_DEFAULT 0x00000000 6460 #define smnPCIEMSIX_VECT5_ADDR_HI_DEFAULT 0x00000000 6461 #define smnPCIEMSIX_VECT5_MSG_DATA_DEFAULT 0x00000000 6462 #define smnPCIEMSIX_VECT5_CONTROL_DEFAULT 0x00000000 6463 #define smnPCIEMSIX_VECT6_ADDR_LO_DEFAULT 0x00000000 6464 #define smnPCIEMSIX_VECT6_ADDR_HI_DEFAULT 0x00000000 6465 #define smnPCIEMSIX_VECT6_MSG_DATA_DEFAULT 0x00000000 6466 #define smnPCIEMSIX_VECT6_CONTROL_DEFAULT 0x00000000 6467 #define smnPCIEMSIX_VECT7_ADDR_LO_DEFAULT 0x00000000 6468 #define smnPCIEMSIX_VECT7_ADDR_HI_DEFAULT 0x00000000 6469 #define smnPCIEMSIX_VECT7_MSG_DATA_DEFAULT 0x00000000 6470 #define smnPCIEMSIX_VECT7_CONTROL_DEFAULT 0x00000000 6471 #define smnPCIEMSIX_VECT8_ADDR_LO_DEFAULT 0x00000000 6472 #define smnPCIEMSIX_VECT8_ADDR_HI_DEFAULT 0x00000000 6473 #define smnPCIEMSIX_VECT8_MSG_DATA_DEFAULT 0x00000000 6474 #define smnPCIEMSIX_VECT8_CONTROL_DEFAULT 0x00000000 6475 #define smnPCIEMSIX_VECT9_ADDR_LO_DEFAULT 0x00000000 6476 #define smnPCIEMSIX_VECT9_ADDR_HI_DEFAULT 0x00000000 6477 #define smnPCIEMSIX_VECT9_MSG_DATA_DEFAULT 0x00000000 6478 #define smnPCIEMSIX_VECT9_CONTROL_DEFAULT 0x00000000 6479 #define smnPCIEMSIX_VECT10_ADDR_LO_DEFAULT 0x00000000 6480 #define smnPCIEMSIX_VECT10_ADDR_HI_DEFAULT 0x00000000 6481 #define smnPCIEMSIX_VECT10_MSG_DATA_DEFAULT 0x00000000 6482 #define smnPCIEMSIX_VECT10_CONTROL_DEFAULT 0x00000000 6483 #define smnPCIEMSIX_VECT11_ADDR_LO_DEFAULT 0x00000000 6484 #define smnPCIEMSIX_VECT11_ADDR_HI_DEFAULT 0x00000000 6485 #define smnPCIEMSIX_VECT11_MSG_DATA_DEFAULT 0x00000000 6486 #define smnPCIEMSIX_VECT11_CONTROL_DEFAULT 0x00000000 6487 #define smnPCIEMSIX_VECT12_ADDR_LO_DEFAULT 0x00000000 6488 #define smnPCIEMSIX_VECT12_ADDR_HI_DEFAULT 0x00000000 6489 #define smnPCIEMSIX_VECT12_MSG_DATA_DEFAULT 0x00000000 6490 #define smnPCIEMSIX_VECT12_CONTROL_DEFAULT 0x00000000 6491 #define smnPCIEMSIX_VECT13_ADDR_LO_DEFAULT 0x00000000 6492 #define smnPCIEMSIX_VECT13_ADDR_HI_DEFAULT 0x00000000 6493 #define smnPCIEMSIX_VECT13_MSG_DATA_DEFAULT 0x00000000 6494 #define smnPCIEMSIX_VECT13_CONTROL_DEFAULT 0x00000000 6495 #define smnPCIEMSIX_VECT14_ADDR_LO_DEFAULT 0x00000000 6496 #define smnPCIEMSIX_VECT14_ADDR_HI_DEFAULT 0x00000000 6497 #define smnPCIEMSIX_VECT14_MSG_DATA_DEFAULT 0x00000000 6498 #define smnPCIEMSIX_VECT14_CONTROL_DEFAULT 0x00000000 6499 #define smnPCIEMSIX_VECT15_ADDR_LO_DEFAULT 0x00000000 6500 #define smnPCIEMSIX_VECT15_ADDR_HI_DEFAULT 0x00000000 6501 #define smnPCIEMSIX_VECT15_MSG_DATA_DEFAULT 0x00000000 6502 #define smnPCIEMSIX_VECT15_CONTROL_DEFAULT 0x00000000 6503 #define smnPCIEMSIX_VECT16_ADDR_LO_DEFAULT 0x00000000 6504 #define smnPCIEMSIX_VECT16_ADDR_HI_DEFAULT 0x00000000 6505 #define smnPCIEMSIX_VECT16_MSG_DATA_DEFAULT 0x00000000 6506 #define smnPCIEMSIX_VECT16_CONTROL_DEFAULT 0x00000000 6507 #define smnPCIEMSIX_VECT17_ADDR_LO_DEFAULT 0x00000000 6508 #define smnPCIEMSIX_VECT17_ADDR_HI_DEFAULT 0x00000000 6509 #define smnPCIEMSIX_VECT17_MSG_DATA_DEFAULT 0x00000000 6510 #define smnPCIEMSIX_VECT17_CONTROL_DEFAULT 0x00000000 6511 #define smnPCIEMSIX_VECT18_ADDR_LO_DEFAULT 0x00000000 6512 #define smnPCIEMSIX_VECT18_ADDR_HI_DEFAULT 0x00000000 6513 #define smnPCIEMSIX_VECT18_MSG_DATA_DEFAULT 0x00000000 6514 #define smnPCIEMSIX_VECT18_CONTROL_DEFAULT 0x00000000 6515 #define smnPCIEMSIX_VECT19_ADDR_LO_DEFAULT 0x00000000 6516 #define smnPCIEMSIX_VECT19_ADDR_HI_DEFAULT 0x00000000 6517 #define smnPCIEMSIX_VECT19_MSG_DATA_DEFAULT 0x00000000 6518 #define smnPCIEMSIX_VECT19_CONTROL_DEFAULT 0x00000000 6519 #define smnPCIEMSIX_VECT20_ADDR_LO_DEFAULT 0x00000000 6520 #define smnPCIEMSIX_VECT20_ADDR_HI_DEFAULT 0x00000000 6521 #define smnPCIEMSIX_VECT20_MSG_DATA_DEFAULT 0x00000000 6522 #define smnPCIEMSIX_VECT20_CONTROL_DEFAULT 0x00000000 6523 #define smnPCIEMSIX_VECT21_ADDR_LO_DEFAULT 0x00000000 6524 #define smnPCIEMSIX_VECT21_ADDR_HI_DEFAULT 0x00000000 6525 #define smnPCIEMSIX_VECT21_MSG_DATA_DEFAULT 0x00000000 6526 #define smnPCIEMSIX_VECT21_CONTROL_DEFAULT 0x00000000 6527 #define smnPCIEMSIX_VECT22_ADDR_LO_DEFAULT 0x00000000 6528 #define smnPCIEMSIX_VECT22_ADDR_HI_DEFAULT 0x00000000 6529 #define smnPCIEMSIX_VECT22_MSG_DATA_DEFAULT 0x00000000 6530 #define smnPCIEMSIX_VECT22_CONTROL_DEFAULT 0x00000000 6531 #define smnPCIEMSIX_VECT23_ADDR_LO_DEFAULT 0x00000000 6532 #define smnPCIEMSIX_VECT23_ADDR_HI_DEFAULT 0x00000000 6533 #define smnPCIEMSIX_VECT23_MSG_DATA_DEFAULT 0x00000000 6534 #define smnPCIEMSIX_VECT23_CONTROL_DEFAULT 0x00000000 6535 #define smnPCIEMSIX_VECT24_ADDR_LO_DEFAULT 0x00000000 6536 #define smnPCIEMSIX_VECT24_ADDR_HI_DEFAULT 0x00000000 6537 #define smnPCIEMSIX_VECT24_MSG_DATA_DEFAULT 0x00000000 6538 #define smnPCIEMSIX_VECT24_CONTROL_DEFAULT 0x00000000 6539 #define smnPCIEMSIX_VECT25_ADDR_LO_DEFAULT 0x00000000 6540 #define smnPCIEMSIX_VECT25_ADDR_HI_DEFAULT 0x00000000 6541 #define smnPCIEMSIX_VECT25_MSG_DATA_DEFAULT 0x00000000 6542 #define smnPCIEMSIX_VECT25_CONTROL_DEFAULT 0x00000000 6543 #define smnPCIEMSIX_VECT26_ADDR_LO_DEFAULT 0x00000000 6544 #define smnPCIEMSIX_VECT26_ADDR_HI_DEFAULT 0x00000000 6545 #define smnPCIEMSIX_VECT26_MSG_DATA_DEFAULT 0x00000000 6546 #define smnPCIEMSIX_VECT26_CONTROL_DEFAULT 0x00000000 6547 #define smnPCIEMSIX_VECT27_ADDR_LO_DEFAULT 0x00000000 6548 #define smnPCIEMSIX_VECT27_ADDR_HI_DEFAULT 0x00000000 6549 #define smnPCIEMSIX_VECT27_MSG_DATA_DEFAULT 0x00000000 6550 #define smnPCIEMSIX_VECT27_CONTROL_DEFAULT 0x00000000 6551 #define smnPCIEMSIX_VECT28_ADDR_LO_DEFAULT 0x00000000 6552 #define smnPCIEMSIX_VECT28_ADDR_HI_DEFAULT 0x00000000 6553 #define smnPCIEMSIX_VECT28_MSG_DATA_DEFAULT 0x00000000 6554 #define smnPCIEMSIX_VECT28_CONTROL_DEFAULT 0x00000000 6555 #define smnPCIEMSIX_VECT29_ADDR_LO_DEFAULT 0x00000000 6556 #define smnPCIEMSIX_VECT29_ADDR_HI_DEFAULT 0x00000000 6557 #define smnPCIEMSIX_VECT29_MSG_DATA_DEFAULT 0x00000000 6558 #define smnPCIEMSIX_VECT29_CONTROL_DEFAULT 0x00000000 6559 #define smnPCIEMSIX_VECT30_ADDR_LO_DEFAULT 0x00000000 6560 #define smnPCIEMSIX_VECT30_ADDR_HI_DEFAULT 0x00000000 6561 #define smnPCIEMSIX_VECT30_MSG_DATA_DEFAULT 0x00000000 6562 #define smnPCIEMSIX_VECT30_CONTROL_DEFAULT 0x00000000 6563 #define smnPCIEMSIX_VECT31_ADDR_LO_DEFAULT 0x00000000 6564 #define smnPCIEMSIX_VECT31_ADDR_HI_DEFAULT 0x00000000 6565 #define smnPCIEMSIX_VECT31_MSG_DATA_DEFAULT 0x00000000 6566 #define smnPCIEMSIX_VECT31_CONTROL_DEFAULT 0x00000000 6567 #define smnPCIEMSIX_VECT32_ADDR_LO_DEFAULT 0x00000000 6568 #define smnPCIEMSIX_VECT32_ADDR_HI_DEFAULT 0x00000000 6569 #define smnPCIEMSIX_VECT32_MSG_DATA_DEFAULT 0x00000000 6570 #define smnPCIEMSIX_VECT32_CONTROL_DEFAULT 0x00000000 6571 #define smnPCIEMSIX_VECT33_ADDR_LO_DEFAULT 0x00000000 6572 #define smnPCIEMSIX_VECT33_ADDR_HI_DEFAULT 0x00000000 6573 #define smnPCIEMSIX_VECT33_MSG_DATA_DEFAULT 0x00000000 6574 #define smnPCIEMSIX_VECT33_CONTROL_DEFAULT 0x00000000 6575 #define smnPCIEMSIX_VECT34_ADDR_LO_DEFAULT 0x00000000 6576 #define smnPCIEMSIX_VECT34_ADDR_HI_DEFAULT 0x00000000 6577 #define smnPCIEMSIX_VECT34_MSG_DATA_DEFAULT 0x00000000 6578 #define smnPCIEMSIX_VECT34_CONTROL_DEFAULT 0x00000000 6579 #define smnPCIEMSIX_VECT35_ADDR_LO_DEFAULT 0x00000000 6580 #define smnPCIEMSIX_VECT35_ADDR_HI_DEFAULT 0x00000000 6581 #define smnPCIEMSIX_VECT35_MSG_DATA_DEFAULT 0x00000000 6582 #define smnPCIEMSIX_VECT35_CONTROL_DEFAULT 0x00000000 6583 #define smnPCIEMSIX_VECT36_ADDR_LO_DEFAULT 0x00000000 6584 #define smnPCIEMSIX_VECT36_ADDR_HI_DEFAULT 0x00000000 6585 #define smnPCIEMSIX_VECT36_MSG_DATA_DEFAULT 0x00000000 6586 #define smnPCIEMSIX_VECT36_CONTROL_DEFAULT 0x00000000 6587 #define smnPCIEMSIX_VECT37_ADDR_LO_DEFAULT 0x00000000 6588 #define smnPCIEMSIX_VECT37_ADDR_HI_DEFAULT 0x00000000 6589 #define smnPCIEMSIX_VECT37_MSG_DATA_DEFAULT 0x00000000 6590 #define smnPCIEMSIX_VECT37_CONTROL_DEFAULT 0x00000000 6591 #define smnPCIEMSIX_VECT38_ADDR_LO_DEFAULT 0x00000000 6592 #define smnPCIEMSIX_VECT38_ADDR_HI_DEFAULT 0x00000000 6593 #define smnPCIEMSIX_VECT38_MSG_DATA_DEFAULT 0x00000000 6594 #define smnPCIEMSIX_VECT38_CONTROL_DEFAULT 0x00000000 6595 #define smnPCIEMSIX_VECT39_ADDR_LO_DEFAULT 0x00000000 6596 #define smnPCIEMSIX_VECT39_ADDR_HI_DEFAULT 0x00000000 6597 #define smnPCIEMSIX_VECT39_MSG_DATA_DEFAULT 0x00000000 6598 #define smnPCIEMSIX_VECT39_CONTROL_DEFAULT 0x00000000 6599 #define smnPCIEMSIX_VECT40_ADDR_LO_DEFAULT 0x00000000 6600 #define smnPCIEMSIX_VECT40_ADDR_HI_DEFAULT 0x00000000 6601 #define smnPCIEMSIX_VECT40_MSG_DATA_DEFAULT 0x00000000 6602 #define smnPCIEMSIX_VECT40_CONTROL_DEFAULT 0x00000000 6603 #define smnPCIEMSIX_VECT41_ADDR_LO_DEFAULT 0x00000000 6604 #define smnPCIEMSIX_VECT41_ADDR_HI_DEFAULT 0x00000000 6605 #define smnPCIEMSIX_VECT41_MSG_DATA_DEFAULT 0x00000000 6606 #define smnPCIEMSIX_VECT41_CONTROL_DEFAULT 0x00000000 6607 #define smnPCIEMSIX_VECT42_ADDR_LO_DEFAULT 0x00000000 6608 #define smnPCIEMSIX_VECT42_ADDR_HI_DEFAULT 0x00000000 6609 #define smnPCIEMSIX_VECT42_MSG_DATA_DEFAULT 0x00000000 6610 #define smnPCIEMSIX_VECT42_CONTROL_DEFAULT 0x00000000 6611 #define smnPCIEMSIX_VECT43_ADDR_LO_DEFAULT 0x00000000 6612 #define smnPCIEMSIX_VECT43_ADDR_HI_DEFAULT 0x00000000 6613 #define smnPCIEMSIX_VECT43_MSG_DATA_DEFAULT 0x00000000 6614 #define smnPCIEMSIX_VECT43_CONTROL_DEFAULT 0x00000000 6615 #define smnPCIEMSIX_VECT44_ADDR_LO_DEFAULT 0x00000000 6616 #define smnPCIEMSIX_VECT44_ADDR_HI_DEFAULT 0x00000000 6617 #define smnPCIEMSIX_VECT44_MSG_DATA_DEFAULT 0x00000000 6618 #define smnPCIEMSIX_VECT44_CONTROL_DEFAULT 0x00000000 6619 #define smnPCIEMSIX_VECT45_ADDR_LO_DEFAULT 0x00000000 6620 #define smnPCIEMSIX_VECT45_ADDR_HI_DEFAULT 0x00000000 6621 #define smnPCIEMSIX_VECT45_MSG_DATA_DEFAULT 0x00000000 6622 #define smnPCIEMSIX_VECT45_CONTROL_DEFAULT 0x00000000 6623 #define smnPCIEMSIX_VECT46_ADDR_LO_DEFAULT 0x00000000 6624 #define smnPCIEMSIX_VECT46_ADDR_HI_DEFAULT 0x00000000 6625 #define smnPCIEMSIX_VECT46_MSG_DATA_DEFAULT 0x00000000 6626 #define smnPCIEMSIX_VECT46_CONTROL_DEFAULT 0x00000000 6627 #define smnPCIEMSIX_VECT47_ADDR_LO_DEFAULT 0x00000000 6628 #define smnPCIEMSIX_VECT47_ADDR_HI_DEFAULT 0x00000000 6629 #define smnPCIEMSIX_VECT47_MSG_DATA_DEFAULT 0x00000000 6630 #define smnPCIEMSIX_VECT47_CONTROL_DEFAULT 0x00000000 6631 #define smnPCIEMSIX_VECT48_ADDR_LO_DEFAULT 0x00000000 6632 #define smnPCIEMSIX_VECT48_ADDR_HI_DEFAULT 0x00000000 6633 #define smnPCIEMSIX_VECT48_MSG_DATA_DEFAULT 0x00000000 6634 #define smnPCIEMSIX_VECT48_CONTROL_DEFAULT 0x00000000 6635 #define smnPCIEMSIX_VECT49_ADDR_LO_DEFAULT 0x00000000 6636 #define smnPCIEMSIX_VECT49_ADDR_HI_DEFAULT 0x00000000 6637 #define smnPCIEMSIX_VECT49_MSG_DATA_DEFAULT 0x00000000 6638 #define smnPCIEMSIX_VECT49_CONTROL_DEFAULT 0x00000000 6639 #define smnPCIEMSIX_VECT50_ADDR_LO_DEFAULT 0x00000000 6640 #define smnPCIEMSIX_VECT50_ADDR_HI_DEFAULT 0x00000000 6641 #define smnPCIEMSIX_VECT50_MSG_DATA_DEFAULT 0x00000000 6642 #define smnPCIEMSIX_VECT50_CONTROL_DEFAULT 0x00000000 6643 #define smnPCIEMSIX_VECT51_ADDR_LO_DEFAULT 0x00000000 6644 #define smnPCIEMSIX_VECT51_ADDR_HI_DEFAULT 0x00000000 6645 #define smnPCIEMSIX_VECT51_MSG_DATA_DEFAULT 0x00000000 6646 #define smnPCIEMSIX_VECT51_CONTROL_DEFAULT 0x00000000 6647 #define smnPCIEMSIX_VECT52_ADDR_LO_DEFAULT 0x00000000 6648 #define smnPCIEMSIX_VECT52_ADDR_HI_DEFAULT 0x00000000 6649 #define smnPCIEMSIX_VECT52_MSG_DATA_DEFAULT 0x00000000 6650 #define smnPCIEMSIX_VECT52_CONTROL_DEFAULT 0x00000000 6651 #define smnPCIEMSIX_VECT53_ADDR_LO_DEFAULT 0x00000000 6652 #define smnPCIEMSIX_VECT53_ADDR_HI_DEFAULT 0x00000000 6653 #define smnPCIEMSIX_VECT53_MSG_DATA_DEFAULT 0x00000000 6654 #define smnPCIEMSIX_VECT53_CONTROL_DEFAULT 0x00000000 6655 #define smnPCIEMSIX_VECT54_ADDR_LO_DEFAULT 0x00000000 6656 #define smnPCIEMSIX_VECT54_ADDR_HI_DEFAULT 0x00000000 6657 #define smnPCIEMSIX_VECT54_MSG_DATA_DEFAULT 0x00000000 6658 #define smnPCIEMSIX_VECT54_CONTROL_DEFAULT 0x00000000 6659 #define smnPCIEMSIX_VECT55_ADDR_LO_DEFAULT 0x00000000 6660 #define smnPCIEMSIX_VECT55_ADDR_HI_DEFAULT 0x00000000 6661 #define smnPCIEMSIX_VECT55_MSG_DATA_DEFAULT 0x00000000 6662 #define smnPCIEMSIX_VECT55_CONTROL_DEFAULT 0x00000000 6663 #define smnPCIEMSIX_VECT56_ADDR_LO_DEFAULT 0x00000000 6664 #define smnPCIEMSIX_VECT56_ADDR_HI_DEFAULT 0x00000000 6665 #define smnPCIEMSIX_VECT56_MSG_DATA_DEFAULT 0x00000000 6666 #define smnPCIEMSIX_VECT56_CONTROL_DEFAULT 0x00000000 6667 #define smnPCIEMSIX_VECT57_ADDR_LO_DEFAULT 0x00000000 6668 #define smnPCIEMSIX_VECT57_ADDR_HI_DEFAULT 0x00000000 6669 #define smnPCIEMSIX_VECT57_MSG_DATA_DEFAULT 0x00000000 6670 #define smnPCIEMSIX_VECT57_CONTROL_DEFAULT 0x00000000 6671 #define smnPCIEMSIX_VECT58_ADDR_LO_DEFAULT 0x00000000 6672 #define smnPCIEMSIX_VECT58_ADDR_HI_DEFAULT 0x00000000 6673 #define smnPCIEMSIX_VECT58_MSG_DATA_DEFAULT 0x00000000 6674 #define smnPCIEMSIX_VECT58_CONTROL_DEFAULT 0x00000000 6675 #define smnPCIEMSIX_VECT59_ADDR_LO_DEFAULT 0x00000000 6676 #define smnPCIEMSIX_VECT59_ADDR_HI_DEFAULT 0x00000000 6677 #define smnPCIEMSIX_VECT59_MSG_DATA_DEFAULT 0x00000000 6678 #define smnPCIEMSIX_VECT59_CONTROL_DEFAULT 0x00000000 6679 #define smnPCIEMSIX_VECT60_ADDR_LO_DEFAULT 0x00000000 6680 #define smnPCIEMSIX_VECT60_ADDR_HI_DEFAULT 0x00000000 6681 #define smnPCIEMSIX_VECT60_MSG_DATA_DEFAULT 0x00000000 6682 #define smnPCIEMSIX_VECT60_CONTROL_DEFAULT 0x00000000 6683 #define smnPCIEMSIX_VECT61_ADDR_LO_DEFAULT 0x00000000 6684 #define smnPCIEMSIX_VECT61_ADDR_HI_DEFAULT 0x00000000 6685 #define smnPCIEMSIX_VECT61_MSG_DATA_DEFAULT 0x00000000 6686 #define smnPCIEMSIX_VECT61_CONTROL_DEFAULT 0x00000000 6687 #define smnPCIEMSIX_VECT62_ADDR_LO_DEFAULT 0x00000000 6688 #define smnPCIEMSIX_VECT62_ADDR_HI_DEFAULT 0x00000000 6689 #define smnPCIEMSIX_VECT62_MSG_DATA_DEFAULT 0x00000000 6690 #define smnPCIEMSIX_VECT62_CONTROL_DEFAULT 0x00000000 6691 #define smnPCIEMSIX_VECT63_ADDR_LO_DEFAULT 0x00000000 6692 #define smnPCIEMSIX_VECT63_ADDR_HI_DEFAULT 0x00000000 6693 #define smnPCIEMSIX_VECT63_MSG_DATA_DEFAULT 0x00000000 6694 #define smnPCIEMSIX_VECT63_CONTROL_DEFAULT 0x00000000 6695 #define smnPCIEMSIX_VECT64_ADDR_LO_DEFAULT 0x00000000 6696 #define smnPCIEMSIX_VECT64_ADDR_HI_DEFAULT 0x00000000 6697 #define smnPCIEMSIX_VECT64_MSG_DATA_DEFAULT 0x00000000 6698 #define smnPCIEMSIX_VECT64_CONTROL_DEFAULT 0x00000000 6699 #define smnPCIEMSIX_VECT65_ADDR_LO_DEFAULT 0x00000000 6700 #define smnPCIEMSIX_VECT65_ADDR_HI_DEFAULT 0x00000000 6701 #define smnPCIEMSIX_VECT65_MSG_DATA_DEFAULT 0x00000000 6702 #define smnPCIEMSIX_VECT65_CONTROL_DEFAULT 0x00000000 6703 #define smnPCIEMSIX_VECT66_ADDR_LO_DEFAULT 0x00000000 6704 #define smnPCIEMSIX_VECT66_ADDR_HI_DEFAULT 0x00000000 6705 #define smnPCIEMSIX_VECT66_MSG_DATA_DEFAULT 0x00000000 6706 #define smnPCIEMSIX_VECT66_CONTROL_DEFAULT 0x00000000 6707 #define smnPCIEMSIX_VECT67_ADDR_LO_DEFAULT 0x00000000 6708 #define smnPCIEMSIX_VECT67_ADDR_HI_DEFAULT 0x00000000 6709 #define smnPCIEMSIX_VECT67_MSG_DATA_DEFAULT 0x00000000 6710 #define smnPCIEMSIX_VECT67_CONTROL_DEFAULT 0x00000000 6711 #define smnPCIEMSIX_VECT68_ADDR_LO_DEFAULT 0x00000000 6712 #define smnPCIEMSIX_VECT68_ADDR_HI_DEFAULT 0x00000000 6713 #define smnPCIEMSIX_VECT68_MSG_DATA_DEFAULT 0x00000000 6714 #define smnPCIEMSIX_VECT68_CONTROL_DEFAULT 0x00000000 6715 #define smnPCIEMSIX_VECT69_ADDR_LO_DEFAULT 0x00000000 6716 #define smnPCIEMSIX_VECT69_ADDR_HI_DEFAULT 0x00000000 6717 #define smnPCIEMSIX_VECT69_MSG_DATA_DEFAULT 0x00000000 6718 #define smnPCIEMSIX_VECT69_CONTROL_DEFAULT 0x00000000 6719 #define smnPCIEMSIX_VECT70_ADDR_LO_DEFAULT 0x00000000 6720 #define smnPCIEMSIX_VECT70_ADDR_HI_DEFAULT 0x00000000 6721 #define smnPCIEMSIX_VECT70_MSG_DATA_DEFAULT 0x00000000 6722 #define smnPCIEMSIX_VECT70_CONTROL_DEFAULT 0x00000000 6723 #define smnPCIEMSIX_VECT71_ADDR_LO_DEFAULT 0x00000000 6724 #define smnPCIEMSIX_VECT71_ADDR_HI_DEFAULT 0x00000000 6725 #define smnPCIEMSIX_VECT71_MSG_DATA_DEFAULT 0x00000000 6726 #define smnPCIEMSIX_VECT71_CONTROL_DEFAULT 0x00000000 6727 #define smnPCIEMSIX_VECT72_ADDR_LO_DEFAULT 0x00000000 6728 #define smnPCIEMSIX_VECT72_ADDR_HI_DEFAULT 0x00000000 6729 #define smnPCIEMSIX_VECT72_MSG_DATA_DEFAULT 0x00000000 6730 #define smnPCIEMSIX_VECT72_CONTROL_DEFAULT 0x00000000 6731 #define smnPCIEMSIX_VECT73_ADDR_LO_DEFAULT 0x00000000 6732 #define smnPCIEMSIX_VECT73_ADDR_HI_DEFAULT 0x00000000 6733 #define smnPCIEMSIX_VECT73_MSG_DATA_DEFAULT 0x00000000 6734 #define smnPCIEMSIX_VECT73_CONTROL_DEFAULT 0x00000000 6735 #define smnPCIEMSIX_VECT74_ADDR_LO_DEFAULT 0x00000000 6736 #define smnPCIEMSIX_VECT74_ADDR_HI_DEFAULT 0x00000000 6737 #define smnPCIEMSIX_VECT74_MSG_DATA_DEFAULT 0x00000000 6738 #define smnPCIEMSIX_VECT74_CONTROL_DEFAULT 0x00000000 6739 #define smnPCIEMSIX_VECT75_ADDR_LO_DEFAULT 0x00000000 6740 #define smnPCIEMSIX_VECT75_ADDR_HI_DEFAULT 0x00000000 6741 #define smnPCIEMSIX_VECT75_MSG_DATA_DEFAULT 0x00000000 6742 #define smnPCIEMSIX_VECT75_CONTROL_DEFAULT 0x00000000 6743 #define smnPCIEMSIX_VECT76_ADDR_LO_DEFAULT 0x00000000 6744 #define smnPCIEMSIX_VECT76_ADDR_HI_DEFAULT 0x00000000 6745 #define smnPCIEMSIX_VECT76_MSG_DATA_DEFAULT 0x00000000 6746 #define smnPCIEMSIX_VECT76_CONTROL_DEFAULT 0x00000000 6747 #define smnPCIEMSIX_VECT77_ADDR_LO_DEFAULT 0x00000000 6748 #define smnPCIEMSIX_VECT77_ADDR_HI_DEFAULT 0x00000000 6749 #define smnPCIEMSIX_VECT77_MSG_DATA_DEFAULT 0x00000000 6750 #define smnPCIEMSIX_VECT77_CONTROL_DEFAULT 0x00000000 6751 #define smnPCIEMSIX_VECT78_ADDR_LO_DEFAULT 0x00000000 6752 #define smnPCIEMSIX_VECT78_ADDR_HI_DEFAULT 0x00000000 6753 #define smnPCIEMSIX_VECT78_MSG_DATA_DEFAULT 0x00000000 6754 #define smnPCIEMSIX_VECT78_CONTROL_DEFAULT 0x00000000 6755 #define smnPCIEMSIX_VECT79_ADDR_LO_DEFAULT 0x00000000 6756 #define smnPCIEMSIX_VECT79_ADDR_HI_DEFAULT 0x00000000 6757 #define smnPCIEMSIX_VECT79_MSG_DATA_DEFAULT 0x00000000 6758 #define smnPCIEMSIX_VECT79_CONTROL_DEFAULT 0x00000000 6759 #define smnPCIEMSIX_VECT80_ADDR_LO_DEFAULT 0x00000000 6760 #define smnPCIEMSIX_VECT80_ADDR_HI_DEFAULT 0x00000000 6761 #define smnPCIEMSIX_VECT80_MSG_DATA_DEFAULT 0x00000000 6762 #define smnPCIEMSIX_VECT80_CONTROL_DEFAULT 0x00000000 6763 #define smnPCIEMSIX_VECT81_ADDR_LO_DEFAULT 0x00000000 6764 #define smnPCIEMSIX_VECT81_ADDR_HI_DEFAULT 0x00000000 6765 #define smnPCIEMSIX_VECT81_MSG_DATA_DEFAULT 0x00000000 6766 #define smnPCIEMSIX_VECT81_CONTROL_DEFAULT 0x00000000 6767 #define smnPCIEMSIX_VECT82_ADDR_LO_DEFAULT 0x00000000 6768 #define smnPCIEMSIX_VECT82_ADDR_HI_DEFAULT 0x00000000 6769 #define smnPCIEMSIX_VECT82_MSG_DATA_DEFAULT 0x00000000 6770 #define smnPCIEMSIX_VECT82_CONTROL_DEFAULT 0x00000000 6771 #define smnPCIEMSIX_VECT83_ADDR_LO_DEFAULT 0x00000000 6772 #define smnPCIEMSIX_VECT83_ADDR_HI_DEFAULT 0x00000000 6773 #define smnPCIEMSIX_VECT83_MSG_DATA_DEFAULT 0x00000000 6774 #define smnPCIEMSIX_VECT83_CONTROL_DEFAULT 0x00000000 6775 #define smnPCIEMSIX_VECT84_ADDR_LO_DEFAULT 0x00000000 6776 #define smnPCIEMSIX_VECT84_ADDR_HI_DEFAULT 0x00000000 6777 #define smnPCIEMSIX_VECT84_MSG_DATA_DEFAULT 0x00000000 6778 #define smnPCIEMSIX_VECT84_CONTROL_DEFAULT 0x00000000 6779 #define smnPCIEMSIX_VECT85_ADDR_LO_DEFAULT 0x00000000 6780 #define smnPCIEMSIX_VECT85_ADDR_HI_DEFAULT 0x00000000 6781 #define smnPCIEMSIX_VECT85_MSG_DATA_DEFAULT 0x00000000 6782 #define smnPCIEMSIX_VECT85_CONTROL_DEFAULT 0x00000000 6783 #define smnPCIEMSIX_VECT86_ADDR_LO_DEFAULT 0x00000000 6784 #define smnPCIEMSIX_VECT86_ADDR_HI_DEFAULT 0x00000000 6785 #define smnPCIEMSIX_VECT86_MSG_DATA_DEFAULT 0x00000000 6786 #define smnPCIEMSIX_VECT86_CONTROL_DEFAULT 0x00000000 6787 #define smnPCIEMSIX_VECT87_ADDR_LO_DEFAULT 0x00000000 6788 #define smnPCIEMSIX_VECT87_ADDR_HI_DEFAULT 0x00000000 6789 #define smnPCIEMSIX_VECT87_MSG_DATA_DEFAULT 0x00000000 6790 #define smnPCIEMSIX_VECT87_CONTROL_DEFAULT 0x00000000 6791 #define smnPCIEMSIX_VECT88_ADDR_LO_DEFAULT 0x00000000 6792 #define smnPCIEMSIX_VECT88_ADDR_HI_DEFAULT 0x00000000 6793 #define smnPCIEMSIX_VECT88_MSG_DATA_DEFAULT 0x00000000 6794 #define smnPCIEMSIX_VECT88_CONTROL_DEFAULT 0x00000000 6795 #define smnPCIEMSIX_VECT89_ADDR_LO_DEFAULT 0x00000000 6796 #define smnPCIEMSIX_VECT89_ADDR_HI_DEFAULT 0x00000000 6797 #define smnPCIEMSIX_VECT89_MSG_DATA_DEFAULT 0x00000000 6798 #define smnPCIEMSIX_VECT89_CONTROL_DEFAULT 0x00000000 6799 #define smnPCIEMSIX_VECT90_ADDR_LO_DEFAULT 0x00000000 6800 #define smnPCIEMSIX_VECT90_ADDR_HI_DEFAULT 0x00000000 6801 #define smnPCIEMSIX_VECT90_MSG_DATA_DEFAULT 0x00000000 6802 #define smnPCIEMSIX_VECT90_CONTROL_DEFAULT 0x00000000 6803 #define smnPCIEMSIX_VECT91_ADDR_LO_DEFAULT 0x00000000 6804 #define smnPCIEMSIX_VECT91_ADDR_HI_DEFAULT 0x00000000 6805 #define smnPCIEMSIX_VECT91_MSG_DATA_DEFAULT 0x00000000 6806 #define smnPCIEMSIX_VECT91_CONTROL_DEFAULT 0x00000000 6807 #define smnPCIEMSIX_VECT92_ADDR_LO_DEFAULT 0x00000000 6808 #define smnPCIEMSIX_VECT92_ADDR_HI_DEFAULT 0x00000000 6809 #define smnPCIEMSIX_VECT92_MSG_DATA_DEFAULT 0x00000000 6810 #define smnPCIEMSIX_VECT92_CONTROL_DEFAULT 0x00000000 6811 #define smnPCIEMSIX_VECT93_ADDR_LO_DEFAULT 0x00000000 6812 #define smnPCIEMSIX_VECT93_ADDR_HI_DEFAULT 0x00000000 6813 #define smnPCIEMSIX_VECT93_MSG_DATA_DEFAULT 0x00000000 6814 #define smnPCIEMSIX_VECT93_CONTROL_DEFAULT 0x00000000 6815 #define smnPCIEMSIX_VECT94_ADDR_LO_DEFAULT 0x00000000 6816 #define smnPCIEMSIX_VECT94_ADDR_HI_DEFAULT 0x00000000 6817 #define smnPCIEMSIX_VECT94_MSG_DATA_DEFAULT 0x00000000 6818 #define smnPCIEMSIX_VECT94_CONTROL_DEFAULT 0x00000000 6819 #define smnPCIEMSIX_VECT95_ADDR_LO_DEFAULT 0x00000000 6820 #define smnPCIEMSIX_VECT95_ADDR_HI_DEFAULT 0x00000000 6821 #define smnPCIEMSIX_VECT95_MSG_DATA_DEFAULT 0x00000000 6822 #define smnPCIEMSIX_VECT95_CONTROL_DEFAULT 0x00000000 6823 #define smnPCIEMSIX_VECT96_ADDR_LO_DEFAULT 0x00000000 6824 #define smnPCIEMSIX_VECT96_ADDR_HI_DEFAULT 0x00000000 6825 #define smnPCIEMSIX_VECT96_MSG_DATA_DEFAULT 0x00000000 6826 #define smnPCIEMSIX_VECT96_CONTROL_DEFAULT 0x00000000 6827 #define smnPCIEMSIX_VECT97_ADDR_LO_DEFAULT 0x00000000 6828 #define smnPCIEMSIX_VECT97_ADDR_HI_DEFAULT 0x00000000 6829 #define smnPCIEMSIX_VECT97_MSG_DATA_DEFAULT 0x00000000 6830 #define smnPCIEMSIX_VECT97_CONTROL_DEFAULT 0x00000000 6831 #define smnPCIEMSIX_VECT98_ADDR_LO_DEFAULT 0x00000000 6832 #define smnPCIEMSIX_VECT98_ADDR_HI_DEFAULT 0x00000000 6833 #define smnPCIEMSIX_VECT98_MSG_DATA_DEFAULT 0x00000000 6834 #define smnPCIEMSIX_VECT98_CONTROL_DEFAULT 0x00000000 6835 #define smnPCIEMSIX_VECT99_ADDR_LO_DEFAULT 0x00000000 6836 #define smnPCIEMSIX_VECT99_ADDR_HI_DEFAULT 0x00000000 6837 #define smnPCIEMSIX_VECT99_MSG_DATA_DEFAULT 0x00000000 6838 #define smnPCIEMSIX_VECT99_CONTROL_DEFAULT 0x00000000 6839 #define smnPCIEMSIX_VECT100_ADDR_LO_DEFAULT 0x00000000 6840 #define smnPCIEMSIX_VECT100_ADDR_HI_DEFAULT 0x00000000 6841 #define smnPCIEMSIX_VECT100_MSG_DATA_DEFAULT 0x00000000 6842 #define smnPCIEMSIX_VECT100_CONTROL_DEFAULT 0x00000000 6843 #define smnPCIEMSIX_VECT101_ADDR_LO_DEFAULT 0x00000000 6844 #define smnPCIEMSIX_VECT101_ADDR_HI_DEFAULT 0x00000000 6845 #define smnPCIEMSIX_VECT101_MSG_DATA_DEFAULT 0x00000000 6846 #define smnPCIEMSIX_VECT101_CONTROL_DEFAULT 0x00000000 6847 #define smnPCIEMSIX_VECT102_ADDR_LO_DEFAULT 0x00000000 6848 #define smnPCIEMSIX_VECT102_ADDR_HI_DEFAULT 0x00000000 6849 #define smnPCIEMSIX_VECT102_MSG_DATA_DEFAULT 0x00000000 6850 #define smnPCIEMSIX_VECT102_CONTROL_DEFAULT 0x00000000 6851 #define smnPCIEMSIX_VECT103_ADDR_LO_DEFAULT 0x00000000 6852 #define smnPCIEMSIX_VECT103_ADDR_HI_DEFAULT 0x00000000 6853 #define smnPCIEMSIX_VECT103_MSG_DATA_DEFAULT 0x00000000 6854 #define smnPCIEMSIX_VECT103_CONTROL_DEFAULT 0x00000000 6855 #define smnPCIEMSIX_VECT104_ADDR_LO_DEFAULT 0x00000000 6856 #define smnPCIEMSIX_VECT104_ADDR_HI_DEFAULT 0x00000000 6857 #define smnPCIEMSIX_VECT104_MSG_DATA_DEFAULT 0x00000000 6858 #define smnPCIEMSIX_VECT104_CONTROL_DEFAULT 0x00000000 6859 #define smnPCIEMSIX_VECT105_ADDR_LO_DEFAULT 0x00000000 6860 #define smnPCIEMSIX_VECT105_ADDR_HI_DEFAULT 0x00000000 6861 #define smnPCIEMSIX_VECT105_MSG_DATA_DEFAULT 0x00000000 6862 #define smnPCIEMSIX_VECT105_CONTROL_DEFAULT 0x00000000 6863 #define smnPCIEMSIX_VECT106_ADDR_LO_DEFAULT 0x00000000 6864 #define smnPCIEMSIX_VECT106_ADDR_HI_DEFAULT 0x00000000 6865 #define smnPCIEMSIX_VECT106_MSG_DATA_DEFAULT 0x00000000 6866 #define smnPCIEMSIX_VECT106_CONTROL_DEFAULT 0x00000000 6867 #define smnPCIEMSIX_VECT107_ADDR_LO_DEFAULT 0x00000000 6868 #define smnPCIEMSIX_VECT107_ADDR_HI_DEFAULT 0x00000000 6869 #define smnPCIEMSIX_VECT107_MSG_DATA_DEFAULT 0x00000000 6870 #define smnPCIEMSIX_VECT107_CONTROL_DEFAULT 0x00000000 6871 #define smnPCIEMSIX_VECT108_ADDR_LO_DEFAULT 0x00000000 6872 #define smnPCIEMSIX_VECT108_ADDR_HI_DEFAULT 0x00000000 6873 #define smnPCIEMSIX_VECT108_MSG_DATA_DEFAULT 0x00000000 6874 #define smnPCIEMSIX_VECT108_CONTROL_DEFAULT 0x00000000 6875 #define smnPCIEMSIX_VECT109_ADDR_LO_DEFAULT 0x00000000 6876 #define smnPCIEMSIX_VECT109_ADDR_HI_DEFAULT 0x00000000 6877 #define smnPCIEMSIX_VECT109_MSG_DATA_DEFAULT 0x00000000 6878 #define smnPCIEMSIX_VECT109_CONTROL_DEFAULT 0x00000000 6879 #define smnPCIEMSIX_VECT110_ADDR_LO_DEFAULT 0x00000000 6880 #define smnPCIEMSIX_VECT110_ADDR_HI_DEFAULT 0x00000000 6881 #define smnPCIEMSIX_VECT110_MSG_DATA_DEFAULT 0x00000000 6882 #define smnPCIEMSIX_VECT110_CONTROL_DEFAULT 0x00000000 6883 #define smnPCIEMSIX_VECT111_ADDR_LO_DEFAULT 0x00000000 6884 #define smnPCIEMSIX_VECT111_ADDR_HI_DEFAULT 0x00000000 6885 #define smnPCIEMSIX_VECT111_MSG_DATA_DEFAULT 0x00000000 6886 #define smnPCIEMSIX_VECT111_CONTROL_DEFAULT 0x00000000 6887 #define smnPCIEMSIX_VECT112_ADDR_LO_DEFAULT 0x00000000 6888 #define smnPCIEMSIX_VECT112_ADDR_HI_DEFAULT 0x00000000 6889 #define smnPCIEMSIX_VECT112_MSG_DATA_DEFAULT 0x00000000 6890 #define smnPCIEMSIX_VECT112_CONTROL_DEFAULT 0x00000000 6891 #define smnPCIEMSIX_VECT113_ADDR_LO_DEFAULT 0x00000000 6892 #define smnPCIEMSIX_VECT113_ADDR_HI_DEFAULT 0x00000000 6893 #define smnPCIEMSIX_VECT113_MSG_DATA_DEFAULT 0x00000000 6894 #define smnPCIEMSIX_VECT113_CONTROL_DEFAULT 0x00000000 6895 #define smnPCIEMSIX_VECT114_ADDR_LO_DEFAULT 0x00000000 6896 #define smnPCIEMSIX_VECT114_ADDR_HI_DEFAULT 0x00000000 6897 #define smnPCIEMSIX_VECT114_MSG_DATA_DEFAULT 0x00000000 6898 #define smnPCIEMSIX_VECT114_CONTROL_DEFAULT 0x00000000 6899 #define smnPCIEMSIX_VECT115_ADDR_LO_DEFAULT 0x00000000 6900 #define smnPCIEMSIX_VECT115_ADDR_HI_DEFAULT 0x00000000 6901 #define smnPCIEMSIX_VECT115_MSG_DATA_DEFAULT 0x00000000 6902 #define smnPCIEMSIX_VECT115_CONTROL_DEFAULT 0x00000000 6903 #define smnPCIEMSIX_VECT116_ADDR_LO_DEFAULT 0x00000000 6904 #define smnPCIEMSIX_VECT116_ADDR_HI_DEFAULT 0x00000000 6905 #define smnPCIEMSIX_VECT116_MSG_DATA_DEFAULT 0x00000000 6906 #define smnPCIEMSIX_VECT116_CONTROL_DEFAULT 0x00000000 6907 #define smnPCIEMSIX_VECT117_ADDR_LO_DEFAULT 0x00000000 6908 #define smnPCIEMSIX_VECT117_ADDR_HI_DEFAULT 0x00000000 6909 #define smnPCIEMSIX_VECT117_MSG_DATA_DEFAULT 0x00000000 6910 #define smnPCIEMSIX_VECT117_CONTROL_DEFAULT 0x00000000 6911 #define smnPCIEMSIX_VECT118_ADDR_LO_DEFAULT 0x00000000 6912 #define smnPCIEMSIX_VECT118_ADDR_HI_DEFAULT 0x00000000 6913 #define smnPCIEMSIX_VECT118_MSG_DATA_DEFAULT 0x00000000 6914 #define smnPCIEMSIX_VECT118_CONTROL_DEFAULT 0x00000000 6915 #define smnPCIEMSIX_VECT119_ADDR_LO_DEFAULT 0x00000000 6916 #define smnPCIEMSIX_VECT119_ADDR_HI_DEFAULT 0x00000000 6917 #define smnPCIEMSIX_VECT119_MSG_DATA_DEFAULT 0x00000000 6918 #define smnPCIEMSIX_VECT119_CONTROL_DEFAULT 0x00000000 6919 #define smnPCIEMSIX_VECT120_ADDR_LO_DEFAULT 0x00000000 6920 #define smnPCIEMSIX_VECT120_ADDR_HI_DEFAULT 0x00000000 6921 #define smnPCIEMSIX_VECT120_MSG_DATA_DEFAULT 0x00000000 6922 #define smnPCIEMSIX_VECT120_CONTROL_DEFAULT 0x00000000 6923 #define smnPCIEMSIX_VECT121_ADDR_LO_DEFAULT 0x00000000 6924 #define smnPCIEMSIX_VECT121_ADDR_HI_DEFAULT 0x00000000 6925 #define smnPCIEMSIX_VECT121_MSG_DATA_DEFAULT 0x00000000 6926 #define smnPCIEMSIX_VECT121_CONTROL_DEFAULT 0x00000000 6927 #define smnPCIEMSIX_VECT122_ADDR_LO_DEFAULT 0x00000000 6928 #define smnPCIEMSIX_VECT122_ADDR_HI_DEFAULT 0x00000000 6929 #define smnPCIEMSIX_VECT122_MSG_DATA_DEFAULT 0x00000000 6930 #define smnPCIEMSIX_VECT122_CONTROL_DEFAULT 0x00000000 6931 #define smnPCIEMSIX_VECT123_ADDR_LO_DEFAULT 0x00000000 6932 #define smnPCIEMSIX_VECT123_ADDR_HI_DEFAULT 0x00000000 6933 #define smnPCIEMSIX_VECT123_MSG_DATA_DEFAULT 0x00000000 6934 #define smnPCIEMSIX_VECT123_CONTROL_DEFAULT 0x00000000 6935 #define smnPCIEMSIX_VECT124_ADDR_LO_DEFAULT 0x00000000 6936 #define smnPCIEMSIX_VECT124_ADDR_HI_DEFAULT 0x00000000 6937 #define smnPCIEMSIX_VECT124_MSG_DATA_DEFAULT 0x00000000 6938 #define smnPCIEMSIX_VECT124_CONTROL_DEFAULT 0x00000000 6939 #define smnPCIEMSIX_VECT125_ADDR_LO_DEFAULT 0x00000000 6940 #define smnPCIEMSIX_VECT125_ADDR_HI_DEFAULT 0x00000000 6941 #define smnPCIEMSIX_VECT125_MSG_DATA_DEFAULT 0x00000000 6942 #define smnPCIEMSIX_VECT125_CONTROL_DEFAULT 0x00000000 6943 #define smnPCIEMSIX_VECT126_ADDR_LO_DEFAULT 0x00000000 6944 #define smnPCIEMSIX_VECT126_ADDR_HI_DEFAULT 0x00000000 6945 #define smnPCIEMSIX_VECT126_MSG_DATA_DEFAULT 0x00000000 6946 #define smnPCIEMSIX_VECT126_CONTROL_DEFAULT 0x00000000 6947 #define smnPCIEMSIX_VECT127_ADDR_LO_DEFAULT 0x00000000 6948 #define smnPCIEMSIX_VECT127_ADDR_HI_DEFAULT 0x00000000 6949 #define smnPCIEMSIX_VECT127_MSG_DATA_DEFAULT 0x00000000 6950 #define smnPCIEMSIX_VECT127_CONTROL_DEFAULT 0x00000000 6951 #define smnPCIEMSIX_VECT128_ADDR_LO_DEFAULT 0x00000000 6952 #define smnPCIEMSIX_VECT128_ADDR_HI_DEFAULT 0x00000000 6953 #define smnPCIEMSIX_VECT128_MSG_DATA_DEFAULT 0x00000000 6954 #define smnPCIEMSIX_VECT128_CONTROL_DEFAULT 0x00000000 6955 #define smnPCIEMSIX_VECT129_ADDR_LO_DEFAULT 0x00000000 6956 #define smnPCIEMSIX_VECT129_ADDR_HI_DEFAULT 0x00000000 6957 #define smnPCIEMSIX_VECT129_MSG_DATA_DEFAULT 0x00000000 6958 #define smnPCIEMSIX_VECT129_CONTROL_DEFAULT 0x00000000 6959 #define smnPCIEMSIX_VECT130_ADDR_LO_DEFAULT 0x00000000 6960 #define smnPCIEMSIX_VECT130_ADDR_HI_DEFAULT 0x00000000 6961 #define smnPCIEMSIX_VECT130_MSG_DATA_DEFAULT 0x00000000 6962 #define smnPCIEMSIX_VECT130_CONTROL_DEFAULT 0x00000000 6963 #define smnPCIEMSIX_VECT131_ADDR_LO_DEFAULT 0x00000000 6964 #define smnPCIEMSIX_VECT131_ADDR_HI_DEFAULT 0x00000000 6965 #define smnPCIEMSIX_VECT131_MSG_DATA_DEFAULT 0x00000000 6966 #define smnPCIEMSIX_VECT131_CONTROL_DEFAULT 0x00000000 6967 #define smnPCIEMSIX_VECT132_ADDR_LO_DEFAULT 0x00000000 6968 #define smnPCIEMSIX_VECT132_ADDR_HI_DEFAULT 0x00000000 6969 #define smnPCIEMSIX_VECT132_MSG_DATA_DEFAULT 0x00000000 6970 #define smnPCIEMSIX_VECT132_CONTROL_DEFAULT 0x00000000 6971 #define smnPCIEMSIX_VECT133_ADDR_LO_DEFAULT 0x00000000 6972 #define smnPCIEMSIX_VECT133_ADDR_HI_DEFAULT 0x00000000 6973 #define smnPCIEMSIX_VECT133_MSG_DATA_DEFAULT 0x00000000 6974 #define smnPCIEMSIX_VECT133_CONTROL_DEFAULT 0x00000000 6975 #define smnPCIEMSIX_VECT134_ADDR_LO_DEFAULT 0x00000000 6976 #define smnPCIEMSIX_VECT134_ADDR_HI_DEFAULT 0x00000000 6977 #define smnPCIEMSIX_VECT134_MSG_DATA_DEFAULT 0x00000000 6978 #define smnPCIEMSIX_VECT134_CONTROL_DEFAULT 0x00000000 6979 #define smnPCIEMSIX_VECT135_ADDR_LO_DEFAULT 0x00000000 6980 #define smnPCIEMSIX_VECT135_ADDR_HI_DEFAULT 0x00000000 6981 #define smnPCIEMSIX_VECT135_MSG_DATA_DEFAULT 0x00000000 6982 #define smnPCIEMSIX_VECT135_CONTROL_DEFAULT 0x00000000 6983 #define smnPCIEMSIX_VECT136_ADDR_LO_DEFAULT 0x00000000 6984 #define smnPCIEMSIX_VECT136_ADDR_HI_DEFAULT 0x00000000 6985 #define smnPCIEMSIX_VECT136_MSG_DATA_DEFAULT 0x00000000 6986 #define smnPCIEMSIX_VECT136_CONTROL_DEFAULT 0x00000000 6987 #define smnPCIEMSIX_VECT137_ADDR_LO_DEFAULT 0x00000000 6988 #define smnPCIEMSIX_VECT137_ADDR_HI_DEFAULT 0x00000000 6989 #define smnPCIEMSIX_VECT137_MSG_DATA_DEFAULT 0x00000000 6990 #define smnPCIEMSIX_VECT137_CONTROL_DEFAULT 0x00000000 6991 #define smnPCIEMSIX_VECT138_ADDR_LO_DEFAULT 0x00000000 6992 #define smnPCIEMSIX_VECT138_ADDR_HI_DEFAULT 0x00000000 6993 #define smnPCIEMSIX_VECT138_MSG_DATA_DEFAULT 0x00000000 6994 #define smnPCIEMSIX_VECT138_CONTROL_DEFAULT 0x00000000 6995 #define smnPCIEMSIX_VECT139_ADDR_LO_DEFAULT 0x00000000 6996 #define smnPCIEMSIX_VECT139_ADDR_HI_DEFAULT 0x00000000 6997 #define smnPCIEMSIX_VECT139_MSG_DATA_DEFAULT 0x00000000 6998 #define smnPCIEMSIX_VECT139_CONTROL_DEFAULT 0x00000000 6999 #define smnPCIEMSIX_VECT140_ADDR_LO_DEFAULT 0x00000000 7000 #define smnPCIEMSIX_VECT140_ADDR_HI_DEFAULT 0x00000000 7001 #define smnPCIEMSIX_VECT140_MSG_DATA_DEFAULT 0x00000000 7002 #define smnPCIEMSIX_VECT140_CONTROL_DEFAULT 0x00000000 7003 #define smnPCIEMSIX_VECT141_ADDR_LO_DEFAULT 0x00000000 7004 #define smnPCIEMSIX_VECT141_ADDR_HI_DEFAULT 0x00000000 7005 #define smnPCIEMSIX_VECT141_MSG_DATA_DEFAULT 0x00000000 7006 #define smnPCIEMSIX_VECT141_CONTROL_DEFAULT 0x00000000 7007 #define smnPCIEMSIX_VECT142_ADDR_LO_DEFAULT 0x00000000 7008 #define smnPCIEMSIX_VECT142_ADDR_HI_DEFAULT 0x00000000 7009 #define smnPCIEMSIX_VECT142_MSG_DATA_DEFAULT 0x00000000 7010 #define smnPCIEMSIX_VECT142_CONTROL_DEFAULT 0x00000000 7011 #define smnPCIEMSIX_VECT143_ADDR_LO_DEFAULT 0x00000000 7012 #define smnPCIEMSIX_VECT143_ADDR_HI_DEFAULT 0x00000000 7013 #define smnPCIEMSIX_VECT143_MSG_DATA_DEFAULT 0x00000000 7014 #define smnPCIEMSIX_VECT143_CONTROL_DEFAULT 0x00000000 7015 #define smnPCIEMSIX_VECT144_ADDR_LO_DEFAULT 0x00000000 7016 #define smnPCIEMSIX_VECT144_ADDR_HI_DEFAULT 0x00000000 7017 #define smnPCIEMSIX_VECT144_MSG_DATA_DEFAULT 0x00000000 7018 #define smnPCIEMSIX_VECT144_CONTROL_DEFAULT 0x00000000 7019 #define smnPCIEMSIX_VECT145_ADDR_LO_DEFAULT 0x00000000 7020 #define smnPCIEMSIX_VECT145_ADDR_HI_DEFAULT 0x00000000 7021 #define smnPCIEMSIX_VECT145_MSG_DATA_DEFAULT 0x00000000 7022 #define smnPCIEMSIX_VECT145_CONTROL_DEFAULT 0x00000000 7023 #define smnPCIEMSIX_VECT146_ADDR_LO_DEFAULT 0x00000000 7024 #define smnPCIEMSIX_VECT146_ADDR_HI_DEFAULT 0x00000000 7025 #define smnPCIEMSIX_VECT146_MSG_DATA_DEFAULT 0x00000000 7026 #define smnPCIEMSIX_VECT146_CONTROL_DEFAULT 0x00000000 7027 #define smnPCIEMSIX_VECT147_ADDR_LO_DEFAULT 0x00000000 7028 #define smnPCIEMSIX_VECT147_ADDR_HI_DEFAULT 0x00000000 7029 #define smnPCIEMSIX_VECT147_MSG_DATA_DEFAULT 0x00000000 7030 #define smnPCIEMSIX_VECT147_CONTROL_DEFAULT 0x00000000 7031 #define smnPCIEMSIX_VECT148_ADDR_LO_DEFAULT 0x00000000 7032 #define smnPCIEMSIX_VECT148_ADDR_HI_DEFAULT 0x00000000 7033 #define smnPCIEMSIX_VECT148_MSG_DATA_DEFAULT 0x00000000 7034 #define smnPCIEMSIX_VECT148_CONTROL_DEFAULT 0x00000000 7035 #define smnPCIEMSIX_VECT149_ADDR_LO_DEFAULT 0x00000000 7036 #define smnPCIEMSIX_VECT149_ADDR_HI_DEFAULT 0x00000000 7037 #define smnPCIEMSIX_VECT149_MSG_DATA_DEFAULT 0x00000000 7038 #define smnPCIEMSIX_VECT149_CONTROL_DEFAULT 0x00000000 7039 #define smnPCIEMSIX_VECT150_ADDR_LO_DEFAULT 0x00000000 7040 #define smnPCIEMSIX_VECT150_ADDR_HI_DEFAULT 0x00000000 7041 #define smnPCIEMSIX_VECT150_MSG_DATA_DEFAULT 0x00000000 7042 #define smnPCIEMSIX_VECT150_CONTROL_DEFAULT 0x00000000 7043 #define smnPCIEMSIX_VECT151_ADDR_LO_DEFAULT 0x00000000 7044 #define smnPCIEMSIX_VECT151_ADDR_HI_DEFAULT 0x00000000 7045 #define smnPCIEMSIX_VECT151_MSG_DATA_DEFAULT 0x00000000 7046 #define smnPCIEMSIX_VECT151_CONTROL_DEFAULT 0x00000000 7047 #define smnPCIEMSIX_VECT152_ADDR_LO_DEFAULT 0x00000000 7048 #define smnPCIEMSIX_VECT152_ADDR_HI_DEFAULT 0x00000000 7049 #define smnPCIEMSIX_VECT152_MSG_DATA_DEFAULT 0x00000000 7050 #define smnPCIEMSIX_VECT152_CONTROL_DEFAULT 0x00000000 7051 #define smnPCIEMSIX_VECT153_ADDR_LO_DEFAULT 0x00000000 7052 #define smnPCIEMSIX_VECT153_ADDR_HI_DEFAULT 0x00000000 7053 #define smnPCIEMSIX_VECT153_MSG_DATA_DEFAULT 0x00000000 7054 #define smnPCIEMSIX_VECT153_CONTROL_DEFAULT 0x00000000 7055 #define smnPCIEMSIX_VECT154_ADDR_LO_DEFAULT 0x00000000 7056 #define smnPCIEMSIX_VECT154_ADDR_HI_DEFAULT 0x00000000 7057 #define smnPCIEMSIX_VECT154_MSG_DATA_DEFAULT 0x00000000 7058 #define smnPCIEMSIX_VECT154_CONTROL_DEFAULT 0x00000000 7059 #define smnPCIEMSIX_VECT155_ADDR_LO_DEFAULT 0x00000000 7060 #define smnPCIEMSIX_VECT155_ADDR_HI_DEFAULT 0x00000000 7061 #define smnPCIEMSIX_VECT155_MSG_DATA_DEFAULT 0x00000000 7062 #define smnPCIEMSIX_VECT155_CONTROL_DEFAULT 0x00000000 7063 #define smnPCIEMSIX_VECT156_ADDR_LO_DEFAULT 0x00000000 7064 #define smnPCIEMSIX_VECT156_ADDR_HI_DEFAULT 0x00000000 7065 #define smnPCIEMSIX_VECT156_MSG_DATA_DEFAULT 0x00000000 7066 #define smnPCIEMSIX_VECT156_CONTROL_DEFAULT 0x00000000 7067 #define smnPCIEMSIX_VECT157_ADDR_LO_DEFAULT 0x00000000 7068 #define smnPCIEMSIX_VECT157_ADDR_HI_DEFAULT 0x00000000 7069 #define smnPCIEMSIX_VECT157_MSG_DATA_DEFAULT 0x00000000 7070 #define smnPCIEMSIX_VECT157_CONTROL_DEFAULT 0x00000000 7071 #define smnPCIEMSIX_VECT158_ADDR_LO_DEFAULT 0x00000000 7072 #define smnPCIEMSIX_VECT158_ADDR_HI_DEFAULT 0x00000000 7073 #define smnPCIEMSIX_VECT158_MSG_DATA_DEFAULT 0x00000000 7074 #define smnPCIEMSIX_VECT158_CONTROL_DEFAULT 0x00000000 7075 #define smnPCIEMSIX_VECT159_ADDR_LO_DEFAULT 0x00000000 7076 #define smnPCIEMSIX_VECT159_ADDR_HI_DEFAULT 0x00000000 7077 #define smnPCIEMSIX_VECT159_MSG_DATA_DEFAULT 0x00000000 7078 #define smnPCIEMSIX_VECT159_CONTROL_DEFAULT 0x00000000 7079 #define smnPCIEMSIX_VECT160_ADDR_LO_DEFAULT 0x00000000 7080 #define smnPCIEMSIX_VECT160_ADDR_HI_DEFAULT 0x00000000 7081 #define smnPCIEMSIX_VECT160_MSG_DATA_DEFAULT 0x00000000 7082 #define smnPCIEMSIX_VECT160_CONTROL_DEFAULT 0x00000000 7083 #define smnPCIEMSIX_VECT161_ADDR_LO_DEFAULT 0x00000000 7084 #define smnPCIEMSIX_VECT161_ADDR_HI_DEFAULT 0x00000000 7085 #define smnPCIEMSIX_VECT161_MSG_DATA_DEFAULT 0x00000000 7086 #define smnPCIEMSIX_VECT161_CONTROL_DEFAULT 0x00000000 7087 #define smnPCIEMSIX_VECT162_ADDR_LO_DEFAULT 0x00000000 7088 #define smnPCIEMSIX_VECT162_ADDR_HI_DEFAULT 0x00000000 7089 #define smnPCIEMSIX_VECT162_MSG_DATA_DEFAULT 0x00000000 7090 #define smnPCIEMSIX_VECT162_CONTROL_DEFAULT 0x00000000 7091 #define smnPCIEMSIX_VECT163_ADDR_LO_DEFAULT 0x00000000 7092 #define smnPCIEMSIX_VECT163_ADDR_HI_DEFAULT 0x00000000 7093 #define smnPCIEMSIX_VECT163_MSG_DATA_DEFAULT 0x00000000 7094 #define smnPCIEMSIX_VECT163_CONTROL_DEFAULT 0x00000000 7095 #define smnPCIEMSIX_VECT164_ADDR_LO_DEFAULT 0x00000000 7096 #define smnPCIEMSIX_VECT164_ADDR_HI_DEFAULT 0x00000000 7097 #define smnPCIEMSIX_VECT164_MSG_DATA_DEFAULT 0x00000000 7098 #define smnPCIEMSIX_VECT164_CONTROL_DEFAULT 0x00000000 7099 #define smnPCIEMSIX_VECT165_ADDR_LO_DEFAULT 0x00000000 7100 #define smnPCIEMSIX_VECT165_ADDR_HI_DEFAULT 0x00000000 7101 #define smnPCIEMSIX_VECT165_MSG_DATA_DEFAULT 0x00000000 7102 #define smnPCIEMSIX_VECT165_CONTROL_DEFAULT 0x00000000 7103 #define smnPCIEMSIX_VECT166_ADDR_LO_DEFAULT 0x00000000 7104 #define smnPCIEMSIX_VECT166_ADDR_HI_DEFAULT 0x00000000 7105 #define smnPCIEMSIX_VECT166_MSG_DATA_DEFAULT 0x00000000 7106 #define smnPCIEMSIX_VECT166_CONTROL_DEFAULT 0x00000000 7107 #define smnPCIEMSIX_VECT167_ADDR_LO_DEFAULT 0x00000000 7108 #define smnPCIEMSIX_VECT167_ADDR_HI_DEFAULT 0x00000000 7109 #define smnPCIEMSIX_VECT167_MSG_DATA_DEFAULT 0x00000000 7110 #define smnPCIEMSIX_VECT167_CONTROL_DEFAULT 0x00000000 7111 #define smnPCIEMSIX_VECT168_ADDR_LO_DEFAULT 0x00000000 7112 #define smnPCIEMSIX_VECT168_ADDR_HI_DEFAULT 0x00000000 7113 #define smnPCIEMSIX_VECT168_MSG_DATA_DEFAULT 0x00000000 7114 #define smnPCIEMSIX_VECT168_CONTROL_DEFAULT 0x00000000 7115 #define smnPCIEMSIX_VECT169_ADDR_LO_DEFAULT 0x00000000 7116 #define smnPCIEMSIX_VECT169_ADDR_HI_DEFAULT 0x00000000 7117 #define smnPCIEMSIX_VECT169_MSG_DATA_DEFAULT 0x00000000 7118 #define smnPCIEMSIX_VECT169_CONTROL_DEFAULT 0x00000000 7119 #define smnPCIEMSIX_VECT170_ADDR_LO_DEFAULT 0x00000000 7120 #define smnPCIEMSIX_VECT170_ADDR_HI_DEFAULT 0x00000000 7121 #define smnPCIEMSIX_VECT170_MSG_DATA_DEFAULT 0x00000000 7122 #define smnPCIEMSIX_VECT170_CONTROL_DEFAULT 0x00000000 7123 #define smnPCIEMSIX_VECT171_ADDR_LO_DEFAULT 0x00000000 7124 #define smnPCIEMSIX_VECT171_ADDR_HI_DEFAULT 0x00000000 7125 #define smnPCIEMSIX_VECT171_MSG_DATA_DEFAULT 0x00000000 7126 #define smnPCIEMSIX_VECT171_CONTROL_DEFAULT 0x00000000 7127 #define smnPCIEMSIX_VECT172_ADDR_LO_DEFAULT 0x00000000 7128 #define smnPCIEMSIX_VECT172_ADDR_HI_DEFAULT 0x00000000 7129 #define smnPCIEMSIX_VECT172_MSG_DATA_DEFAULT 0x00000000 7130 #define smnPCIEMSIX_VECT172_CONTROL_DEFAULT 0x00000000 7131 #define smnPCIEMSIX_VECT173_ADDR_LO_DEFAULT 0x00000000 7132 #define smnPCIEMSIX_VECT173_ADDR_HI_DEFAULT 0x00000000 7133 #define smnPCIEMSIX_VECT173_MSG_DATA_DEFAULT 0x00000000 7134 #define smnPCIEMSIX_VECT173_CONTROL_DEFAULT 0x00000000 7135 #define smnPCIEMSIX_VECT174_ADDR_LO_DEFAULT 0x00000000 7136 #define smnPCIEMSIX_VECT174_ADDR_HI_DEFAULT 0x00000000 7137 #define smnPCIEMSIX_VECT174_MSG_DATA_DEFAULT 0x00000000 7138 #define smnPCIEMSIX_VECT174_CONTROL_DEFAULT 0x00000000 7139 #define smnPCIEMSIX_VECT175_ADDR_LO_DEFAULT 0x00000000 7140 #define smnPCIEMSIX_VECT175_ADDR_HI_DEFAULT 0x00000000 7141 #define smnPCIEMSIX_VECT175_MSG_DATA_DEFAULT 0x00000000 7142 #define smnPCIEMSIX_VECT175_CONTROL_DEFAULT 0x00000000 7143 #define smnPCIEMSIX_VECT176_ADDR_LO_DEFAULT 0x00000000 7144 #define smnPCIEMSIX_VECT176_ADDR_HI_DEFAULT 0x00000000 7145 #define smnPCIEMSIX_VECT176_MSG_DATA_DEFAULT 0x00000000 7146 #define smnPCIEMSIX_VECT176_CONTROL_DEFAULT 0x00000000 7147 #define smnPCIEMSIX_VECT177_ADDR_LO_DEFAULT 0x00000000 7148 #define smnPCIEMSIX_VECT177_ADDR_HI_DEFAULT 0x00000000 7149 #define smnPCIEMSIX_VECT177_MSG_DATA_DEFAULT 0x00000000 7150 #define smnPCIEMSIX_VECT177_CONTROL_DEFAULT 0x00000000 7151 #define smnPCIEMSIX_VECT178_ADDR_LO_DEFAULT 0x00000000 7152 #define smnPCIEMSIX_VECT178_ADDR_HI_DEFAULT 0x00000000 7153 #define smnPCIEMSIX_VECT178_MSG_DATA_DEFAULT 0x00000000 7154 #define smnPCIEMSIX_VECT178_CONTROL_DEFAULT 0x00000000 7155 #define smnPCIEMSIX_VECT179_ADDR_LO_DEFAULT 0x00000000 7156 #define smnPCIEMSIX_VECT179_ADDR_HI_DEFAULT 0x00000000 7157 #define smnPCIEMSIX_VECT179_MSG_DATA_DEFAULT 0x00000000 7158 #define smnPCIEMSIX_VECT179_CONTROL_DEFAULT 0x00000000 7159 #define smnPCIEMSIX_VECT180_ADDR_LO_DEFAULT 0x00000000 7160 #define smnPCIEMSIX_VECT180_ADDR_HI_DEFAULT 0x00000000 7161 #define smnPCIEMSIX_VECT180_MSG_DATA_DEFAULT 0x00000000 7162 #define smnPCIEMSIX_VECT180_CONTROL_DEFAULT 0x00000000 7163 #define smnPCIEMSIX_VECT181_ADDR_LO_DEFAULT 0x00000000 7164 #define smnPCIEMSIX_VECT181_ADDR_HI_DEFAULT 0x00000000 7165 #define smnPCIEMSIX_VECT181_MSG_DATA_DEFAULT 0x00000000 7166 #define smnPCIEMSIX_VECT181_CONTROL_DEFAULT 0x00000000 7167 #define smnPCIEMSIX_VECT182_ADDR_LO_DEFAULT 0x00000000 7168 #define smnPCIEMSIX_VECT182_ADDR_HI_DEFAULT 0x00000000 7169 #define smnPCIEMSIX_VECT182_MSG_DATA_DEFAULT 0x00000000 7170 #define smnPCIEMSIX_VECT182_CONTROL_DEFAULT 0x00000000 7171 #define smnPCIEMSIX_VECT183_ADDR_LO_DEFAULT 0x00000000 7172 #define smnPCIEMSIX_VECT183_ADDR_HI_DEFAULT 0x00000000 7173 #define smnPCIEMSIX_VECT183_MSG_DATA_DEFAULT 0x00000000 7174 #define smnPCIEMSIX_VECT183_CONTROL_DEFAULT 0x00000000 7175 #define smnPCIEMSIX_VECT184_ADDR_LO_DEFAULT 0x00000000 7176 #define smnPCIEMSIX_VECT184_ADDR_HI_DEFAULT 0x00000000 7177 #define smnPCIEMSIX_VECT184_MSG_DATA_DEFAULT 0x00000000 7178 #define smnPCIEMSIX_VECT184_CONTROL_DEFAULT 0x00000000 7179 #define smnPCIEMSIX_VECT185_ADDR_LO_DEFAULT 0x00000000 7180 #define smnPCIEMSIX_VECT185_ADDR_HI_DEFAULT 0x00000000 7181 #define smnPCIEMSIX_VECT185_MSG_DATA_DEFAULT 0x00000000 7182 #define smnPCIEMSIX_VECT185_CONTROL_DEFAULT 0x00000000 7183 #define smnPCIEMSIX_VECT186_ADDR_LO_DEFAULT 0x00000000 7184 #define smnPCIEMSIX_VECT186_ADDR_HI_DEFAULT 0x00000000 7185 #define smnPCIEMSIX_VECT186_MSG_DATA_DEFAULT 0x00000000 7186 #define smnPCIEMSIX_VECT186_CONTROL_DEFAULT 0x00000000 7187 #define smnPCIEMSIX_VECT187_ADDR_LO_DEFAULT 0x00000000 7188 #define smnPCIEMSIX_VECT187_ADDR_HI_DEFAULT 0x00000000 7189 #define smnPCIEMSIX_VECT187_MSG_DATA_DEFAULT 0x00000000 7190 #define smnPCIEMSIX_VECT187_CONTROL_DEFAULT 0x00000000 7191 #define smnPCIEMSIX_VECT188_ADDR_LO_DEFAULT 0x00000000 7192 #define smnPCIEMSIX_VECT188_ADDR_HI_DEFAULT 0x00000000 7193 #define smnPCIEMSIX_VECT188_MSG_DATA_DEFAULT 0x00000000 7194 #define smnPCIEMSIX_VECT188_CONTROL_DEFAULT 0x00000000 7195 #define smnPCIEMSIX_VECT189_ADDR_LO_DEFAULT 0x00000000 7196 #define smnPCIEMSIX_VECT189_ADDR_HI_DEFAULT 0x00000000 7197 #define smnPCIEMSIX_VECT189_MSG_DATA_DEFAULT 0x00000000 7198 #define smnPCIEMSIX_VECT189_CONTROL_DEFAULT 0x00000000 7199 #define smnPCIEMSIX_VECT190_ADDR_LO_DEFAULT 0x00000000 7200 #define smnPCIEMSIX_VECT190_ADDR_HI_DEFAULT 0x00000000 7201 #define smnPCIEMSIX_VECT190_MSG_DATA_DEFAULT 0x00000000 7202 #define smnPCIEMSIX_VECT190_CONTROL_DEFAULT 0x00000000 7203 #define smnPCIEMSIX_VECT191_ADDR_LO_DEFAULT 0x00000000 7204 #define smnPCIEMSIX_VECT191_ADDR_HI_DEFAULT 0x00000000 7205 #define smnPCIEMSIX_VECT191_MSG_DATA_DEFAULT 0x00000000 7206 #define smnPCIEMSIX_VECT191_CONTROL_DEFAULT 0x00000000 7207 #define smnPCIEMSIX_VECT192_ADDR_LO_DEFAULT 0x00000000 7208 #define smnPCIEMSIX_VECT192_ADDR_HI_DEFAULT 0x00000000 7209 #define smnPCIEMSIX_VECT192_MSG_DATA_DEFAULT 0x00000000 7210 #define smnPCIEMSIX_VECT192_CONTROL_DEFAULT 0x00000000 7211 #define smnPCIEMSIX_VECT193_ADDR_LO_DEFAULT 0x00000000 7212 #define smnPCIEMSIX_VECT193_ADDR_HI_DEFAULT 0x00000000 7213 #define smnPCIEMSIX_VECT193_MSG_DATA_DEFAULT 0x00000000 7214 #define smnPCIEMSIX_VECT193_CONTROL_DEFAULT 0x00000000 7215 #define smnPCIEMSIX_VECT194_ADDR_LO_DEFAULT 0x00000000 7216 #define smnPCIEMSIX_VECT194_ADDR_HI_DEFAULT 0x00000000 7217 #define smnPCIEMSIX_VECT194_MSG_DATA_DEFAULT 0x00000000 7218 #define smnPCIEMSIX_VECT194_CONTROL_DEFAULT 0x00000000 7219 #define smnPCIEMSIX_VECT195_ADDR_LO_DEFAULT 0x00000000 7220 #define smnPCIEMSIX_VECT195_ADDR_HI_DEFAULT 0x00000000 7221 #define smnPCIEMSIX_VECT195_MSG_DATA_DEFAULT 0x00000000 7222 #define smnPCIEMSIX_VECT195_CONTROL_DEFAULT 0x00000000 7223 #define smnPCIEMSIX_VECT196_ADDR_LO_DEFAULT 0x00000000 7224 #define smnPCIEMSIX_VECT196_ADDR_HI_DEFAULT 0x00000000 7225 #define smnPCIEMSIX_VECT196_MSG_DATA_DEFAULT 0x00000000 7226 #define smnPCIEMSIX_VECT196_CONTROL_DEFAULT 0x00000000 7227 #define smnPCIEMSIX_VECT197_ADDR_LO_DEFAULT 0x00000000 7228 #define smnPCIEMSIX_VECT197_ADDR_HI_DEFAULT 0x00000000 7229 #define smnPCIEMSIX_VECT197_MSG_DATA_DEFAULT 0x00000000 7230 #define smnPCIEMSIX_VECT197_CONTROL_DEFAULT 0x00000000 7231 #define smnPCIEMSIX_VECT198_ADDR_LO_DEFAULT 0x00000000 7232 #define smnPCIEMSIX_VECT198_ADDR_HI_DEFAULT 0x00000000 7233 #define smnPCIEMSIX_VECT198_MSG_DATA_DEFAULT 0x00000000 7234 #define smnPCIEMSIX_VECT198_CONTROL_DEFAULT 0x00000000 7235 #define smnPCIEMSIX_VECT199_ADDR_LO_DEFAULT 0x00000000 7236 #define smnPCIEMSIX_VECT199_ADDR_HI_DEFAULT 0x00000000 7237 #define smnPCIEMSIX_VECT199_MSG_DATA_DEFAULT 0x00000000 7238 #define smnPCIEMSIX_VECT199_CONTROL_DEFAULT 0x00000000 7239 #define smnPCIEMSIX_VECT200_ADDR_LO_DEFAULT 0x00000000 7240 #define smnPCIEMSIX_VECT200_ADDR_HI_DEFAULT 0x00000000 7241 #define smnPCIEMSIX_VECT200_MSG_DATA_DEFAULT 0x00000000 7242 #define smnPCIEMSIX_VECT200_CONTROL_DEFAULT 0x00000000 7243 #define smnPCIEMSIX_VECT201_ADDR_LO_DEFAULT 0x00000000 7244 #define smnPCIEMSIX_VECT201_ADDR_HI_DEFAULT 0x00000000 7245 #define smnPCIEMSIX_VECT201_MSG_DATA_DEFAULT 0x00000000 7246 #define smnPCIEMSIX_VECT201_CONTROL_DEFAULT 0x00000000 7247 #define smnPCIEMSIX_VECT202_ADDR_LO_DEFAULT 0x00000000 7248 #define smnPCIEMSIX_VECT202_ADDR_HI_DEFAULT 0x00000000 7249 #define smnPCIEMSIX_VECT202_MSG_DATA_DEFAULT 0x00000000 7250 #define smnPCIEMSIX_VECT202_CONTROL_DEFAULT 0x00000000 7251 #define smnPCIEMSIX_VECT203_ADDR_LO_DEFAULT 0x00000000 7252 #define smnPCIEMSIX_VECT203_ADDR_HI_DEFAULT 0x00000000 7253 #define smnPCIEMSIX_VECT203_MSG_DATA_DEFAULT 0x00000000 7254 #define smnPCIEMSIX_VECT203_CONTROL_DEFAULT 0x00000000 7255 #define smnPCIEMSIX_VECT204_ADDR_LO_DEFAULT 0x00000000 7256 #define smnPCIEMSIX_VECT204_ADDR_HI_DEFAULT 0x00000000 7257 #define smnPCIEMSIX_VECT204_MSG_DATA_DEFAULT 0x00000000 7258 #define smnPCIEMSIX_VECT204_CONTROL_DEFAULT 0x00000000 7259 #define smnPCIEMSIX_VECT205_ADDR_LO_DEFAULT 0x00000000 7260 #define smnPCIEMSIX_VECT205_ADDR_HI_DEFAULT 0x00000000 7261 #define smnPCIEMSIX_VECT205_MSG_DATA_DEFAULT 0x00000000 7262 #define smnPCIEMSIX_VECT205_CONTROL_DEFAULT 0x00000000 7263 #define smnPCIEMSIX_VECT206_ADDR_LO_DEFAULT 0x00000000 7264 #define smnPCIEMSIX_VECT206_ADDR_HI_DEFAULT 0x00000000 7265 #define smnPCIEMSIX_VECT206_MSG_DATA_DEFAULT 0x00000000 7266 #define smnPCIEMSIX_VECT206_CONTROL_DEFAULT 0x00000000 7267 #define smnPCIEMSIX_VECT207_ADDR_LO_DEFAULT 0x00000000 7268 #define smnPCIEMSIX_VECT207_ADDR_HI_DEFAULT 0x00000000 7269 #define smnPCIEMSIX_VECT207_MSG_DATA_DEFAULT 0x00000000 7270 #define smnPCIEMSIX_VECT207_CONTROL_DEFAULT 0x00000000 7271 #define smnPCIEMSIX_VECT208_ADDR_LO_DEFAULT 0x00000000 7272 #define smnPCIEMSIX_VECT208_ADDR_HI_DEFAULT 0x00000000 7273 #define smnPCIEMSIX_VECT208_MSG_DATA_DEFAULT 0x00000000 7274 #define smnPCIEMSIX_VECT208_CONTROL_DEFAULT 0x00000000 7275 #define smnPCIEMSIX_VECT209_ADDR_LO_DEFAULT 0x00000000 7276 #define smnPCIEMSIX_VECT209_ADDR_HI_DEFAULT 0x00000000 7277 #define smnPCIEMSIX_VECT209_MSG_DATA_DEFAULT 0x00000000 7278 #define smnPCIEMSIX_VECT209_CONTROL_DEFAULT 0x00000000 7279 #define smnPCIEMSIX_VECT210_ADDR_LO_DEFAULT 0x00000000 7280 #define smnPCIEMSIX_VECT210_ADDR_HI_DEFAULT 0x00000000 7281 #define smnPCIEMSIX_VECT210_MSG_DATA_DEFAULT 0x00000000 7282 #define smnPCIEMSIX_VECT210_CONTROL_DEFAULT 0x00000000 7283 #define smnPCIEMSIX_VECT211_ADDR_LO_DEFAULT 0x00000000 7284 #define smnPCIEMSIX_VECT211_ADDR_HI_DEFAULT 0x00000000 7285 #define smnPCIEMSIX_VECT211_MSG_DATA_DEFAULT 0x00000000 7286 #define smnPCIEMSIX_VECT211_CONTROL_DEFAULT 0x00000000 7287 #define smnPCIEMSIX_VECT212_ADDR_LO_DEFAULT 0x00000000 7288 #define smnPCIEMSIX_VECT212_ADDR_HI_DEFAULT 0x00000000 7289 #define smnPCIEMSIX_VECT212_MSG_DATA_DEFAULT 0x00000000 7290 #define smnPCIEMSIX_VECT212_CONTROL_DEFAULT 0x00000000 7291 #define smnPCIEMSIX_VECT213_ADDR_LO_DEFAULT 0x00000000 7292 #define smnPCIEMSIX_VECT213_ADDR_HI_DEFAULT 0x00000000 7293 #define smnPCIEMSIX_VECT213_MSG_DATA_DEFAULT 0x00000000 7294 #define smnPCIEMSIX_VECT213_CONTROL_DEFAULT 0x00000000 7295 #define smnPCIEMSIX_VECT214_ADDR_LO_DEFAULT 0x00000000 7296 #define smnPCIEMSIX_VECT214_ADDR_HI_DEFAULT 0x00000000 7297 #define smnPCIEMSIX_VECT214_MSG_DATA_DEFAULT 0x00000000 7298 #define smnPCIEMSIX_VECT214_CONTROL_DEFAULT 0x00000000 7299 #define smnPCIEMSIX_VECT215_ADDR_LO_DEFAULT 0x00000000 7300 #define smnPCIEMSIX_VECT215_ADDR_HI_DEFAULT 0x00000000 7301 #define smnPCIEMSIX_VECT215_MSG_DATA_DEFAULT 0x00000000 7302 #define smnPCIEMSIX_VECT215_CONTROL_DEFAULT 0x00000000 7303 #define smnPCIEMSIX_VECT216_ADDR_LO_DEFAULT 0x00000000 7304 #define smnPCIEMSIX_VECT216_ADDR_HI_DEFAULT 0x00000000 7305 #define smnPCIEMSIX_VECT216_MSG_DATA_DEFAULT 0x00000000 7306 #define smnPCIEMSIX_VECT216_CONTROL_DEFAULT 0x00000000 7307 #define smnPCIEMSIX_VECT217_ADDR_LO_DEFAULT 0x00000000 7308 #define smnPCIEMSIX_VECT217_ADDR_HI_DEFAULT 0x00000000 7309 #define smnPCIEMSIX_VECT217_MSG_DATA_DEFAULT 0x00000000 7310 #define smnPCIEMSIX_VECT217_CONTROL_DEFAULT 0x00000000 7311 #define smnPCIEMSIX_VECT218_ADDR_LO_DEFAULT 0x00000000 7312 #define smnPCIEMSIX_VECT218_ADDR_HI_DEFAULT 0x00000000 7313 #define smnPCIEMSIX_VECT218_MSG_DATA_DEFAULT 0x00000000 7314 #define smnPCIEMSIX_VECT218_CONTROL_DEFAULT 0x00000000 7315 #define smnPCIEMSIX_VECT219_ADDR_LO_DEFAULT 0x00000000 7316 #define smnPCIEMSIX_VECT219_ADDR_HI_DEFAULT 0x00000000 7317 #define smnPCIEMSIX_VECT219_MSG_DATA_DEFAULT 0x00000000 7318 #define smnPCIEMSIX_VECT219_CONTROL_DEFAULT 0x00000000 7319 #define smnPCIEMSIX_VECT220_ADDR_LO_DEFAULT 0x00000000 7320 #define smnPCIEMSIX_VECT220_ADDR_HI_DEFAULT 0x00000000 7321 #define smnPCIEMSIX_VECT220_MSG_DATA_DEFAULT 0x00000000 7322 #define smnPCIEMSIX_VECT220_CONTROL_DEFAULT 0x00000000 7323 #define smnPCIEMSIX_VECT221_ADDR_LO_DEFAULT 0x00000000 7324 #define smnPCIEMSIX_VECT221_ADDR_HI_DEFAULT 0x00000000 7325 #define smnPCIEMSIX_VECT221_MSG_DATA_DEFAULT 0x00000000 7326 #define smnPCIEMSIX_VECT221_CONTROL_DEFAULT 0x00000000 7327 #define smnPCIEMSIX_VECT222_ADDR_LO_DEFAULT 0x00000000 7328 #define smnPCIEMSIX_VECT222_ADDR_HI_DEFAULT 0x00000000 7329 #define smnPCIEMSIX_VECT222_MSG_DATA_DEFAULT 0x00000000 7330 #define smnPCIEMSIX_VECT222_CONTROL_DEFAULT 0x00000000 7331 #define smnPCIEMSIX_VECT223_ADDR_LO_DEFAULT 0x00000000 7332 #define smnPCIEMSIX_VECT223_ADDR_HI_DEFAULT 0x00000000 7333 #define smnPCIEMSIX_VECT223_MSG_DATA_DEFAULT 0x00000000 7334 #define smnPCIEMSIX_VECT223_CONTROL_DEFAULT 0x00000000 7335 #define smnPCIEMSIX_VECT224_ADDR_LO_DEFAULT 0x00000000 7336 #define smnPCIEMSIX_VECT224_ADDR_HI_DEFAULT 0x00000000 7337 #define smnPCIEMSIX_VECT224_MSG_DATA_DEFAULT 0x00000000 7338 #define smnPCIEMSIX_VECT224_CONTROL_DEFAULT 0x00000000 7339 #define smnPCIEMSIX_VECT225_ADDR_LO_DEFAULT 0x00000000 7340 #define smnPCIEMSIX_VECT225_ADDR_HI_DEFAULT 0x00000000 7341 #define smnPCIEMSIX_VECT225_MSG_DATA_DEFAULT 0x00000000 7342 #define smnPCIEMSIX_VECT225_CONTROL_DEFAULT 0x00000000 7343 #define smnPCIEMSIX_VECT226_ADDR_LO_DEFAULT 0x00000000 7344 #define smnPCIEMSIX_VECT226_ADDR_HI_DEFAULT 0x00000000 7345 #define smnPCIEMSIX_VECT226_MSG_DATA_DEFAULT 0x00000000 7346 #define smnPCIEMSIX_VECT226_CONTROL_DEFAULT 0x00000000 7347 #define smnPCIEMSIX_VECT227_ADDR_LO_DEFAULT 0x00000000 7348 #define smnPCIEMSIX_VECT227_ADDR_HI_DEFAULT 0x00000000 7349 #define smnPCIEMSIX_VECT227_MSG_DATA_DEFAULT 0x00000000 7350 #define smnPCIEMSIX_VECT227_CONTROL_DEFAULT 0x00000000 7351 #define smnPCIEMSIX_VECT228_ADDR_LO_DEFAULT 0x00000000 7352 #define smnPCIEMSIX_VECT228_ADDR_HI_DEFAULT 0x00000000 7353 #define smnPCIEMSIX_VECT228_MSG_DATA_DEFAULT 0x00000000 7354 #define smnPCIEMSIX_VECT228_CONTROL_DEFAULT 0x00000000 7355 #define smnPCIEMSIX_VECT229_ADDR_LO_DEFAULT 0x00000000 7356 #define smnPCIEMSIX_VECT229_ADDR_HI_DEFAULT 0x00000000 7357 #define smnPCIEMSIX_VECT229_MSG_DATA_DEFAULT 0x00000000 7358 #define smnPCIEMSIX_VECT229_CONTROL_DEFAULT 0x00000000 7359 #define smnPCIEMSIX_VECT230_ADDR_LO_DEFAULT 0x00000000 7360 #define smnPCIEMSIX_VECT230_ADDR_HI_DEFAULT 0x00000000 7361 #define smnPCIEMSIX_VECT230_MSG_DATA_DEFAULT 0x00000000 7362 #define smnPCIEMSIX_VECT230_CONTROL_DEFAULT 0x00000000 7363 #define smnPCIEMSIX_VECT231_ADDR_LO_DEFAULT 0x00000000 7364 #define smnPCIEMSIX_VECT231_ADDR_HI_DEFAULT 0x00000000 7365 #define smnPCIEMSIX_VECT231_MSG_DATA_DEFAULT 0x00000000 7366 #define smnPCIEMSIX_VECT231_CONTROL_DEFAULT 0x00000000 7367 #define smnPCIEMSIX_VECT232_ADDR_LO_DEFAULT 0x00000000 7368 #define smnPCIEMSIX_VECT232_ADDR_HI_DEFAULT 0x00000000 7369 #define smnPCIEMSIX_VECT232_MSG_DATA_DEFAULT 0x00000000 7370 #define smnPCIEMSIX_VECT232_CONTROL_DEFAULT 0x00000000 7371 #define smnPCIEMSIX_VECT233_ADDR_LO_DEFAULT 0x00000000 7372 #define smnPCIEMSIX_VECT233_ADDR_HI_DEFAULT 0x00000000 7373 #define smnPCIEMSIX_VECT233_MSG_DATA_DEFAULT 0x00000000 7374 #define smnPCIEMSIX_VECT233_CONTROL_DEFAULT 0x00000000 7375 #define smnPCIEMSIX_VECT234_ADDR_LO_DEFAULT 0x00000000 7376 #define smnPCIEMSIX_VECT234_ADDR_HI_DEFAULT 0x00000000 7377 #define smnPCIEMSIX_VECT234_MSG_DATA_DEFAULT 0x00000000 7378 #define smnPCIEMSIX_VECT234_CONTROL_DEFAULT 0x00000000 7379 #define smnPCIEMSIX_VECT235_ADDR_LO_DEFAULT 0x00000000 7380 #define smnPCIEMSIX_VECT235_ADDR_HI_DEFAULT 0x00000000 7381 #define smnPCIEMSIX_VECT235_MSG_DATA_DEFAULT 0x00000000 7382 #define smnPCIEMSIX_VECT235_CONTROL_DEFAULT 0x00000000 7383 #define smnPCIEMSIX_VECT236_ADDR_LO_DEFAULT 0x00000000 7384 #define smnPCIEMSIX_VECT236_ADDR_HI_DEFAULT 0x00000000 7385 #define smnPCIEMSIX_VECT236_MSG_DATA_DEFAULT 0x00000000 7386 #define smnPCIEMSIX_VECT236_CONTROL_DEFAULT 0x00000000 7387 #define smnPCIEMSIX_VECT237_ADDR_LO_DEFAULT 0x00000000 7388 #define smnPCIEMSIX_VECT237_ADDR_HI_DEFAULT 0x00000000 7389 #define smnPCIEMSIX_VECT237_MSG_DATA_DEFAULT 0x00000000 7390 #define smnPCIEMSIX_VECT237_CONTROL_DEFAULT 0x00000000 7391 #define smnPCIEMSIX_VECT238_ADDR_LO_DEFAULT 0x00000000 7392 #define smnPCIEMSIX_VECT238_ADDR_HI_DEFAULT 0x00000000 7393 #define smnPCIEMSIX_VECT238_MSG_DATA_DEFAULT 0x00000000 7394 #define smnPCIEMSIX_VECT238_CONTROL_DEFAULT 0x00000000 7395 #define smnPCIEMSIX_VECT239_ADDR_LO_DEFAULT 0x00000000 7396 #define smnPCIEMSIX_VECT239_ADDR_HI_DEFAULT 0x00000000 7397 #define smnPCIEMSIX_VECT239_MSG_DATA_DEFAULT 0x00000000 7398 #define smnPCIEMSIX_VECT239_CONTROL_DEFAULT 0x00000000 7399 #define smnPCIEMSIX_VECT240_ADDR_LO_DEFAULT 0x00000000 7400 #define smnPCIEMSIX_VECT240_ADDR_HI_DEFAULT 0x00000000 7401 #define smnPCIEMSIX_VECT240_MSG_DATA_DEFAULT 0x00000000 7402 #define smnPCIEMSIX_VECT240_CONTROL_DEFAULT 0x00000000 7403 #define smnPCIEMSIX_VECT241_ADDR_LO_DEFAULT 0x00000000 7404 #define smnPCIEMSIX_VECT241_ADDR_HI_DEFAULT 0x00000000 7405 #define smnPCIEMSIX_VECT241_MSG_DATA_DEFAULT 0x00000000 7406 #define smnPCIEMSIX_VECT241_CONTROL_DEFAULT 0x00000000 7407 #define smnPCIEMSIX_VECT242_ADDR_LO_DEFAULT 0x00000000 7408 #define smnPCIEMSIX_VECT242_ADDR_HI_DEFAULT 0x00000000 7409 #define smnPCIEMSIX_VECT242_MSG_DATA_DEFAULT 0x00000000 7410 #define smnPCIEMSIX_VECT242_CONTROL_DEFAULT 0x00000000 7411 #define smnPCIEMSIX_VECT243_ADDR_LO_DEFAULT 0x00000000 7412 #define smnPCIEMSIX_VECT243_ADDR_HI_DEFAULT 0x00000000 7413 #define smnPCIEMSIX_VECT243_MSG_DATA_DEFAULT 0x00000000 7414 #define smnPCIEMSIX_VECT243_CONTROL_DEFAULT 0x00000000 7415 #define smnPCIEMSIX_VECT244_ADDR_LO_DEFAULT 0x00000000 7416 #define smnPCIEMSIX_VECT244_ADDR_HI_DEFAULT 0x00000000 7417 #define smnPCIEMSIX_VECT244_MSG_DATA_DEFAULT 0x00000000 7418 #define smnPCIEMSIX_VECT244_CONTROL_DEFAULT 0x00000000 7419 #define smnPCIEMSIX_VECT245_ADDR_LO_DEFAULT 0x00000000 7420 #define smnPCIEMSIX_VECT245_ADDR_HI_DEFAULT 0x00000000 7421 #define smnPCIEMSIX_VECT245_MSG_DATA_DEFAULT 0x00000000 7422 #define smnPCIEMSIX_VECT245_CONTROL_DEFAULT 0x00000000 7423 #define smnPCIEMSIX_VECT246_ADDR_LO_DEFAULT 0x00000000 7424 #define smnPCIEMSIX_VECT246_ADDR_HI_DEFAULT 0x00000000 7425 #define smnPCIEMSIX_VECT246_MSG_DATA_DEFAULT 0x00000000 7426 #define smnPCIEMSIX_VECT246_CONTROL_DEFAULT 0x00000000 7427 #define smnPCIEMSIX_VECT247_ADDR_LO_DEFAULT 0x00000000 7428 #define smnPCIEMSIX_VECT247_ADDR_HI_DEFAULT 0x00000000 7429 #define smnPCIEMSIX_VECT247_MSG_DATA_DEFAULT 0x00000000 7430 #define smnPCIEMSIX_VECT247_CONTROL_DEFAULT 0x00000000 7431 #define smnPCIEMSIX_VECT248_ADDR_LO_DEFAULT 0x00000000 7432 #define smnPCIEMSIX_VECT248_ADDR_HI_DEFAULT 0x00000000 7433 #define smnPCIEMSIX_VECT248_MSG_DATA_DEFAULT 0x00000000 7434 #define smnPCIEMSIX_VECT248_CONTROL_DEFAULT 0x00000000 7435 #define smnPCIEMSIX_VECT249_ADDR_LO_DEFAULT 0x00000000 7436 #define smnPCIEMSIX_VECT249_ADDR_HI_DEFAULT 0x00000000 7437 #define smnPCIEMSIX_VECT249_MSG_DATA_DEFAULT 0x00000000 7438 #define smnPCIEMSIX_VECT249_CONTROL_DEFAULT 0x00000000 7439 #define smnPCIEMSIX_VECT250_ADDR_LO_DEFAULT 0x00000000 7440 #define smnPCIEMSIX_VECT250_ADDR_HI_DEFAULT 0x00000000 7441 #define smnPCIEMSIX_VECT250_MSG_DATA_DEFAULT 0x00000000 7442 #define smnPCIEMSIX_VECT250_CONTROL_DEFAULT 0x00000000 7443 #define smnPCIEMSIX_VECT251_ADDR_LO_DEFAULT 0x00000000 7444 #define smnPCIEMSIX_VECT251_ADDR_HI_DEFAULT 0x00000000 7445 #define smnPCIEMSIX_VECT251_MSG_DATA_DEFAULT 0x00000000 7446 #define smnPCIEMSIX_VECT251_CONTROL_DEFAULT 0x00000000 7447 #define smnPCIEMSIX_VECT252_ADDR_LO_DEFAULT 0x00000000 7448 #define smnPCIEMSIX_VECT252_ADDR_HI_DEFAULT 0x00000000 7449 #define smnPCIEMSIX_VECT252_MSG_DATA_DEFAULT 0x00000000 7450 #define smnPCIEMSIX_VECT252_CONTROL_DEFAULT 0x00000000 7451 #define smnPCIEMSIX_VECT253_ADDR_LO_DEFAULT 0x00000000 7452 #define smnPCIEMSIX_VECT253_ADDR_HI_DEFAULT 0x00000000 7453 #define smnPCIEMSIX_VECT253_MSG_DATA_DEFAULT 0x00000000 7454 #define smnPCIEMSIX_VECT253_CONTROL_DEFAULT 0x00000000 7455 #define smnPCIEMSIX_VECT254_ADDR_LO_DEFAULT 0x00000000 7456 #define smnPCIEMSIX_VECT254_ADDR_HI_DEFAULT 0x00000000 7457 #define smnPCIEMSIX_VECT254_MSG_DATA_DEFAULT 0x00000000 7458 #define smnPCIEMSIX_VECT254_CONTROL_DEFAULT 0x00000000 7459 #define smnPCIEMSIX_VECT255_ADDR_LO_DEFAULT 0x00000000 7460 #define smnPCIEMSIX_VECT255_ADDR_HI_DEFAULT 0x00000000 7461 #define smnPCIEMSIX_VECT255_MSG_DATA_DEFAULT 0x00000000 7462 #define smnPCIEMSIX_VECT255_CONTROL_DEFAULT 0x00000000 7463 7464 7465 // addressBlock: nbio_nbif0_pciemsix_0_usb_MSIXPDEC 7466 #define smnPCIEMSIX_PBA_0_DEFAULT 0x00000000 7467 #define smnPCIEMSIX_PBA_1_DEFAULT 0x00000000 7468 #define smnPCIEMSIX_PBA_2_DEFAULT 0x00000000 7469 #define smnPCIEMSIX_PBA_3_DEFAULT 0x00000000 7470 #define smnPCIEMSIX_PBA_4_DEFAULT 0x00000000 7471 #define smnPCIEMSIX_PBA_5_DEFAULT 0x00000000 7472 #define smnPCIEMSIX_PBA_6_DEFAULT 0x00000000 7473 #define smnPCIEMSIX_PBA_7_DEFAULT 0x00000000 7474 7475 7476 // addressBlock: nbio_pcie0_pswusp0_pciedir_p 7477 #define smnPCIEP_RESERVED_DEFAULT 0x00000000 7478 #define smnPCIEP_SCRATCH_DEFAULT 0x00000000 7479 #define smnPCIEP_PORT_CNTL_DEFAULT 0x06000009 7480 #define smnPCIE_TX_CNTL_DEFAULT 0x00408000 7481 #define smnPCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 7482 #define smnPCIE_TX_VENDOR_SPECIFIC_DEFAULT 0x00000000 7483 #define smnPCIE_TX_REQUEST_NUM_CNTL_DEFAULT 0x02000000 7484 #define smnPCIE_TX_SEQ_DEFAULT 0x00000000 7485 #define smnPCIE_TX_REPLAY_DEFAULT 0x00480003 7486 #define smnPCIE_TX_ACK_LATENCY_LIMIT_DEFAULT 0x00000000 7487 #define smnPCIE_TX_NOP_DLLP_DEFAULT 0x00000000 7488 #define smnPCIE_TX_CNTL_2_DEFAULT 0x00000004 7489 #define smnPCIE_TX_CREDITS_ADVT_P_DEFAULT 0x00000000 7490 #define smnPCIE_TX_CREDITS_ADVT_NP_DEFAULT 0x00000000 7491 #define smnPCIE_TX_CREDITS_ADVT_CPL_DEFAULT 0x00000000 7492 #define smnPCIE_TX_CREDITS_INIT_P_DEFAULT 0x00000000 7493 #define smnPCIE_TX_CREDITS_INIT_NP_DEFAULT 0x00000000 7494 #define smnPCIE_TX_CREDITS_INIT_CPL_DEFAULT 0x00000000 7495 #define smnPCIE_TX_CREDITS_STATUS_DEFAULT 0x00000000 7496 #define smnPCIE_TX_CREDITS_FCU_THRESHOLD_DEFAULT 0x03330333 7497 #define smnPCIE_P_PORT_LANE_STATUS_DEFAULT 0x00000000 7498 #define smnPCIE_FC_P_DEFAULT 0x00020008 7499 #define smnPCIE_FC_NP_DEFAULT 0x00020002 7500 #define smnPCIE_FC_CPL_DEFAULT 0x00000000 7501 #define smnPCIE_FC_P_VC1_DEFAULT 0x00020008 7502 #define smnPCIE_FC_NP_VC1_DEFAULT 0x00000000 7503 #define smnPCIE_FC_CPL_VC1_DEFAULT 0x00000000 7504 #define smnPSWUSP0_PCIE_ERR_CNTL_DEFAULT 0x00000500 7505 #define smnPSWUSP0_PCIE_RX_CNTL_DEFAULT 0x01084000 7506 #define smnPCIE_RX_EXPECTED_SEQNUM_DEFAULT 0x00000000 7507 #define smnPCIE_RX_VENDOR_SPECIFIC_DEFAULT 0x00000000 7508 #define smnPCIE_RX_CNTL3_DEFAULT 0x00000000 7509 #define smnPCIE_RX_CREDITS_ALLOCATED_P_DEFAULT 0x00000000 7510 #define smnPCIE_RX_CREDITS_ALLOCATED_NP_DEFAULT 0x00000000 7511 #define smnPCIE_RX_CREDITS_ALLOCATED_CPL_DEFAULT 0x00000000 7512 #define smnPCIEP_ERROR_INJECT_PHYSICAL_DEFAULT 0x00000000 7513 #define smnPCIEP_ERROR_INJECT_TRANSACTION_DEFAULT 0x00000000 7514 #define smnPCIEP_SRIOV_PRIV_CTRL_DEFAULT 0x00000000 7515 #define smnPCIEP_NAK_COUNTER_DEFAULT 0x00000000 7516 #define smnPCIE_LC_CNTL_DEFAULT 0x40010050 7517 #define smnPCIE_LC_TRAINING_CNTL_DEFAULT 0x94009880 7518 #define smnPCIE_LC_LINK_WIDTH_CNTL_DEFAULT 0xda800006 7519 #define smnPCIE_LC_N_FTS_CNTL_DEFAULT 0x00ffc20c 7520 #define smnPSWUSP0_PCIE_LC_SPEED_CNTL_DEFAULT 0x10000200 7521 #define smnPCIE_LC_STATE0_DEFAULT 0x00000000 7522 #define smnPCIE_LC_STATE1_DEFAULT 0x00000000 7523 #define smnPCIE_LC_STATE2_DEFAULT 0x00000000 7524 #define smnPCIE_LC_STATE3_DEFAULT 0x00000000 7525 #define smnPCIE_LC_STATE4_DEFAULT 0x00000000 7526 #define smnPCIE_LC_STATE5_DEFAULT 0x00000000 7527 #define smnPCIE_LINK_MANAGEMENT_CNTL2_DEFAULT 0x00000000 7528 #define smnPSWUSP0_PCIE_LC_CNTL2_DEFAULT 0x96180280 7529 #define smnPCIE_LC_BW_CHANGE_CNTL_DEFAULT 0x00000000 7530 #define smnPCIE_LC_CDR_CNTL_DEFAULT 0x01018060 7531 #define smnPCIE_LC_LANE_CNTL_DEFAULT 0x00000000 7532 #define smnPCIE_LC_CNTL3_DEFAULT 0xa850a020 7533 #define smnPCIE_LC_CNTL4_DEFAULT 0x0340048c 7534 #define smnPCIE_LC_CNTL5_DEFAULT 0x40200000 7535 #define smnPCIE_LC_FORCE_COEFF_DEFAULT 0x00080000 7536 #define smnPCIE_LC_BEST_EQ_SETTINGS_DEFAULT 0x00000000 7537 #define smnPCIE_LC_FORCE_EQ_REQ_COEFF_DEFAULT 0x00000000 7538 #define smnPCIE_LC_CNTL6_DEFAULT 0x8a000090 7539 #define smnPCIE_LC_CNTL7_DEFAULT 0x010002ee 7540 #define smnPCIE_LINK_MANAGEMENT_STATUS_DEFAULT 0x00000000 7541 #define smnPCIE_LINK_MANAGEMENT_MASK_DEFAULT 0x00003fff 7542 #define smnPCIE_LINK_MANAGEMENT_CNTL_DEFAULT 0x00000000 7543 #define smnPCIEP_STRAP_LC_DEFAULT 0x00000000 7544 #define smnPSWUSP0_PCIEP_STRAP_MISC_DEFAULT 0x00000000 7545 #define smnPCIEP_STRAP_LC2_DEFAULT 0x00000000 7546 #define smnPCIE_LC_L1_PM_SUBSTATE_DEFAULT 0x04540000 7547 #define smnPCIE_LC_L1_PM_SUBSTATE2_DEFAULT 0x00000000 7548 #define smnPCIE_LC_PORT_ORDER_DEFAULT 0x00000000 7549 #define smnPCIEP_BCH_ECC_CNTL_DEFAULT 0x00000100 7550 #define smnPCIE_LC_CNTL8_DEFAULT 0x00400000 7551 #define smnPCIE_LC_CNTL9_DEFAULT 0xf0ffec00 7552 #define smnPCIE_LC_FORCE_COEFF2_DEFAULT 0x00080000 7553 #define smnPCIE_LC_FORCE_EQ_REQ_COEFF2_DEFAULT 0x00000000 7554 #define smnPCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES_DEFAULT 0x00000003 7555 #define smnPCIE_LC_CNTL10_DEFAULT 0x30000003 7556 #define smnPCIE_LC_CNTL11_DEFAULT 0x00602000 7557 #define smnPCIE_LC_CNTL12_DEFAULT 0x00000017 7558 #define smnPCIE_LC_SAVE_RESTORE_1_DEFAULT 0x00000000 7559 #define smnPCIE_LC_SAVE_RESTORE_2_DEFAULT 0x00000000 7560 7561 7562 // addressBlock: nbio_pcie0_pciedir 7563 #define smnPCIE_RESERVED_DEFAULT 0x00000000 7564 #define smnPCIE_SCRATCH_DEFAULT 0x00000000 7565 #define smnPCIE_RX_NUM_NAK_DEFAULT 0x00000000 7566 #define smnPCIE_RX_NUM_NAK_GENERATED_DEFAULT 0x00000000 7567 #define smnPCIE_CNTL_DEFAULT 0x80811000 7568 #define smnPCIE_CONFIG_CNTL_DEFAULT 0x0000000f 7569 #define smnPCIE_DEBUG_CNTL_DEFAULT 0x00000001 7570 #define smnPCIE_TX_TRACKING_ADDR_LO_DEFAULT 0x00000000 7571 #define smnPCIE_TX_TRACKING_ADDR_HI_DEFAULT 0x00000000 7572 #define smnPCIE_TX_TRACKING_CTRL_STATUS_DEFAULT 0x00000000 7573 #define smnPCIE_BW_BY_UNITID_DEFAULT 0x00000000 7574 #define smnPCIE_CNTL2_DEFAULT 0x0e000109 7575 #define smnPCIE_RX_CNTL2_DEFAULT 0x00000000 7576 #define smnPCIE_TX_F0_ATTR_CNTL_DEFAULT 0x00000000 7577 #define smnPCIE_TX_SWUS_ATTR_CNTL_DEFAULT 0x00000000 7578 #define smnPCIE_CI_CNTL_DEFAULT 0x40000010 7579 #define smnPCIE_BUS_CNTL_DEFAULT 0x00000000 7580 #define smnPCIE_LC_STATE6_DEFAULT 0x00000000 7581 #define smnPCIE_LC_STATE7_DEFAULT 0x00000000 7582 #define smnPCIE_LC_STATE8_DEFAULT 0x00000000 7583 #define smnPCIE_LC_STATE9_DEFAULT 0x00000000 7584 #define smnPCIE_LC_STATE10_DEFAULT 0x00000000 7585 #define smnPCIE_LC_STATE11_DEFAULT 0x00000000 7586 #define smnPCIE_LC_STATUS1_DEFAULT 0x00000000 7587 #define smnPCIE_LC_STATUS2_DEFAULT 0x00000000 7588 #define smnPCIE_TX_CNTL3_DEFAULT 0x001808c0 7589 #define smnPCIE_TX_STATUS_DEFAULT 0x00000000 7590 #define smnPCIE_WPR_CNTL_DEFAULT 0x00000005 7591 #define smnPCIE_RX_LAST_TLP0_DEFAULT 0x00000000 7592 #define smnPCIE_RX_LAST_TLP1_DEFAULT 0x00000000 7593 #define smnPCIE_RX_LAST_TLP2_DEFAULT 0x00000000 7594 #define smnPCIE_RX_LAST_TLP3_DEFAULT 0x00000000 7595 #define smnPCIE_TX_LAST_TLP0_DEFAULT 0x00000000 7596 #define smnPCIE_TX_LAST_TLP1_DEFAULT 0x00000000 7597 #define smnPCIE_TX_LAST_TLP2_DEFAULT 0x00000000 7598 #define smnPCIE_TX_LAST_TLP3_DEFAULT 0x00000000 7599 #define smnPCIE_I2C_REG_ADDR_EXPAND_DEFAULT 0x00000000 7600 #define smnPCIE_I2C_REG_DATA_DEFAULT 0x00000000 7601 #define smnPCIE_CFG_CNTL_DEFAULT 0x00000000 7602 #define smnPCIE_LC_PM_CNTL_DEFAULT 0x76543210 7603 #define smnPCIE_LC_PORT_ORDER_CNTL_DEFAULT 0x00000000 7604 #define smnPCIE_P_CNTL_DEFAULT 0x00850000 7605 #define smnPCIE_P_BUF_STATUS_DEFAULT 0x00000000 7606 #define smnPCIE_P_DECODER_STATUS_DEFAULT 0x00000000 7607 #define smnPCIE_P_MISC_STATUS_DEFAULT 0x00000000 7608 #define smnPCIE_P_RCV_L0S_FTS_DET_DEFAULT 0x000000ff 7609 #define smnPCIE_RX_AD_DEFAULT 0x00000003 7610 #define smnPCIE_SDP_CTRL_DEFAULT 0x00000002 7611 #define smnPCIE_SDP_SWUS_SLV_ATTR_CTRL_DEFAULT 0x00000000 7612 #define smnPCIE_PERF_COUNT_CNTL_DEFAULT 0x00000000 7613 #define smnPCIE_PERF_CNTL_TXCLK1_DEFAULT 0x00000000 7614 #define smnPCIE_PERF_COUNT0_TXCLK1_DEFAULT 0x00000000 7615 #define smnPCIE_PERF_COUNT1_TXCLK1_DEFAULT 0x00000000 7616 #define smnPCIE_PERF_CNTL_TXCLK2_DEFAULT 0x00000000 7617 #define smnPCIE_PERF_COUNT0_TXCLK2_DEFAULT 0x00000000 7618 #define smnPCIE_PERF_COUNT1_TXCLK2_DEFAULT 0x00000000 7619 #define smnPCIE_PERF_CNTL_TXCLK3_DEFAULT 0x00000000 7620 #define smnPCIE_PERF_COUNT0_TXCLK3_DEFAULT 0x00000000 7621 #define smnPCIE_PERF_COUNT1_TXCLK3_DEFAULT 0x00000000 7622 #define smnPCIE_PERF_CNTL_TXCLK4_DEFAULT 0x00000000 7623 #define smnPCIE_PERF_COUNT0_TXCLK4_DEFAULT 0x00000000 7624 #define smnPCIE_PERF_COUNT1_TXCLK4_DEFAULT 0x00000000 7625 #define smnPCIE_PERF_CNTL_SCLK1_DEFAULT 0x00000000 7626 #define smnPCIE_PERF_COUNT0_SCLK1_DEFAULT 0x00000000 7627 #define smnPCIE_PERF_COUNT1_SCLK1_DEFAULT 0x00000000 7628 #define smnPCIE_PERF_CNTL_SCLK2_DEFAULT 0x00000000 7629 #define smnPCIE_PERF_COUNT0_SCLK2_DEFAULT 0x00000000 7630 #define smnPCIE_PERF_COUNT1_SCLK2_DEFAULT 0x00000000 7631 #define smnPCIE_PERF_CNTL_EVENT_LC_PORT_SEL_DEFAULT 0x00000000 7632 #define smnPCIE_PERF_CNTL_EVENT_CI_PORT_SEL_DEFAULT 0x00000000 7633 #define smnPCIE_HIP_REG0_DEFAULT 0x00000000 7634 #define smnPCIE_HIP_REG1_DEFAULT 0x00000000 7635 #define smnPCIE_HIP_REG2_DEFAULT 0x00000000 7636 #define smnPCIE_HIP_REG3_DEFAULT 0x00000000 7637 #define smnPCIE_HIP_REG4_DEFAULT 0x00000000 7638 #define smnPCIE_HIP_REG5_DEFAULT 0x00000000 7639 #define smnPCIE_HIP_REG6_DEFAULT 0x00000000 7640 #define smnPCIE_HIP_REG7_DEFAULT 0x00000000 7641 #define smnPCIE_HIP_REG8_DEFAULT 0x00008000 7642 #define smnPCIE_STRAP_F0_DEFAULT 0x00000000 7643 #define smnPCIE_STRAP_MISC_DEFAULT 0x00000000 7644 #define smnPCIE_STRAP_MISC2_DEFAULT 0x00000000 7645 #define smnPCIE_STRAP_PI_DEFAULT 0x00000000 7646 #define smnPCIE_STRAP_I2C_BD_DEFAULT 0x00000000 7647 #define smnPCIE_PRBS_CLR_DEFAULT 0x00000000 7648 #define smnPCIE_PRBS_STATUS1_DEFAULT 0x00000000 7649 #define smnPCIE_PRBS_STATUS2_DEFAULT 0x00000000 7650 #define smnPCIE_PRBS_FREERUN_DEFAULT 0x00000000 7651 #define smnPCIE_PRBS_MISC_DEFAULT 0x00000000 7652 #define smnPCIE_PRBS_USER_PATTERN_DEFAULT 0x00000000 7653 #define smnPCIE_PRBS_LO_BITCNT_DEFAULT 0x00000000 7654 #define smnPCIE_PRBS_HI_BITCNT_DEFAULT 0x00000000 7655 #define smnPCIE_PRBS_ERRCNT_0_DEFAULT 0x00000000 7656 #define smnPCIE_PRBS_ERRCNT_1_DEFAULT 0x00000000 7657 #define smnPCIE_PRBS_ERRCNT_2_DEFAULT 0x00000000 7658 #define smnPCIE_PRBS_ERRCNT_3_DEFAULT 0x00000000 7659 #define smnPCIE_PRBS_ERRCNT_4_DEFAULT 0x00000000 7660 #define smnPCIE_PRBS_ERRCNT_5_DEFAULT 0x00000000 7661 #define smnPCIE_PRBS_ERRCNT_6_DEFAULT 0x00000000 7662 #define smnPCIE_PRBS_ERRCNT_7_DEFAULT 0x00000000 7663 #define smnPCIE_PRBS_ERRCNT_8_DEFAULT 0x00000000 7664 #define smnPCIE_PRBS_ERRCNT_9_DEFAULT 0x00000000 7665 #define smnPCIE_PRBS_ERRCNT_10_DEFAULT 0x00000000 7666 #define smnPCIE_PRBS_ERRCNT_11_DEFAULT 0x00000000 7667 #define smnPCIE_PRBS_ERRCNT_12_DEFAULT 0x00000000 7668 #define smnPCIE_PRBS_ERRCNT_13_DEFAULT 0x00000000 7669 #define smnPCIE_PRBS_ERRCNT_14_DEFAULT 0x00000000 7670 #define smnPCIE_PRBS_ERRCNT_15_DEFAULT 0x00000000 7671 #define smnSWRST_COMMAND_STATUS_DEFAULT 0x00000000 7672 #define smnSWRST_GENERAL_CONTROL_DEFAULT 0x02001002 7673 #define smnSWRST_COMMAND_0_DEFAULT 0x00000000 7674 #define smnSWRST_COMMAND_1_DEFAULT 0x04000000 7675 #define smnSWRST_CONTROL_0_DEFAULT 0x5600ff00 7676 #define smnSWRST_CONTROL_1_DEFAULT 0xc220ffff 7677 #define smnSWRST_CONTROL_2_DEFAULT 0x00000000 7678 #define smnSWRST_CONTROL_3_DEFAULT 0x00000000 7679 #define smnSWRST_CONTROL_4_DEFAULT 0x5c00ff01 7680 #define smnSWRST_CONTROL_5_DEFAULT 0xfe20ffff 7681 #define smnSWRST_CONTROL_6_DEFAULT 0x000007ff 7682 #define smnSWRST_EP_COMMAND_0_DEFAULT 0x00000000 7683 #define smnSWRST_EP_CONTROL_0_DEFAULT 0x00000500 7684 #define smnCPM_CONTROL_DEFAULT 0x0080ca00 7685 #define smnCPM_SPLIT_CONTROL_DEFAULT 0x00000000 7686 #define smnSMN_APERTURE_ID_A_DEFAULT 0x00000000 7687 #define smnSMN_APERTURE_ID_B_DEFAULT 0x00000000 7688 #define smnLNCNT_CONTROL_DEFAULT 0x00000000 7689 #define smnLNCNT_QUAN_THRD_DEFAULT 0x00000000 7690 #define smnLNCNT_WEIGHT_DEFAULT 0x00000000 7691 #define smnSMU_INT_PIN_SHARING_PORT_INDICATOR_DEFAULT 0x00000000 7692 #define smnPCIE_PGMST_CNTL_DEFAULT 0x00000000 7693 #define smnPCIE_PGSLV_CNTL_DEFAULT 0x00000004 7694 #define smnLC_CPM_CONTROL_0_DEFAULT 0x00000000 7695 #define smnLC_CPM_CONTROL_1_DEFAULT 0x00000001 7696 #define smnPCIE_RXMARGIN_CONTROL_CAPABILITIES_DEFAULT 0x00000000 7697 #define smnPCIE_RXMARGIN_1_SETTINGS_DEFAULT 0x00000000 7698 #define smnPCIE_RXMARGIN_2_SETTINGS_DEFAULT 0x00000000 7699 #define smnPCIE_PRESENCE_DETECT_SELECT_DEFAULT 0x00000000 7700 #define smnPCIE_LC_DEBUG_CNTL_DEFAULT 0x00010000 7701 7702 7703 // addressBlock: nbio_nbif0_bif_cfg_dev0_swds_bifcfgdecp 7704 #define cfgBIF_CFG_DEV0_SWDS0_VENDOR_ID_DEFAULT 0x00001002 7705 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_ID_DEFAULT 0x00000000 7706 #define cfgBIF_CFG_DEV0_SWDS0_COMMAND_DEFAULT 0x00000000 7707 #define cfgBIF_CFG_DEV0_SWDS0_STATUS_DEFAULT 0x00000000 7708 #define cfgBIF_CFG_DEV0_SWDS0_REVISION_ID_DEFAULT 0x00000000 7709 #define cfgBIF_CFG_DEV0_SWDS0_PROG_INTERFACE_DEFAULT 0x00000000 7710 #define cfgBIF_CFG_DEV0_SWDS0_SUB_CLASS_DEFAULT 0x00000004 7711 #define cfgBIF_CFG_DEV0_SWDS0_BASE_CLASS_DEFAULT 0x00000006 7712 #define cfgBIF_CFG_DEV0_SWDS0_CACHE_LINE_DEFAULT 0x00000000 7713 #define cfgBIF_CFG_DEV0_SWDS0_LATENCY_DEFAULT 0x00000000 7714 #define cfgBIF_CFG_DEV0_SWDS0_HEADER_DEFAULT 0x00000000 7715 #define cfgBIF_CFG_DEV0_SWDS0_BIST_DEFAULT 0x00000000 7716 #define cfgBIF_CFG_DEV0_SWDS0_BASE_ADDR_1_DEFAULT 0x00000000 7717 #define cfgBIF_CFG_DEV0_SWDS0_BASE_ADDR_2_DEFAULT 0x00000000 7718 #define cfgBIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 7719 #define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_DEFAULT 0x00000000 7720 #define cfgBIF_CFG_DEV0_SWDS0_SECONDARY_STATUS_DEFAULT 0x00000000 7721 #define cfgBIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT_DEFAULT 0x00000000 7722 #define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT_DEFAULT 0x00000000 7723 #define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER_DEFAULT 0x00000000 7724 #define cfgBIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER_DEFAULT 0x00000000 7725 #define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 7726 #define cfgBIF_CFG_DEV0_SWDS0_CAP_PTR_DEFAULT 0x00000000 7727 #define cfgBIF_CFG_DEV0_SWDS0_ROM_BASE_ADDR_DEFAULT 0x00000000 7728 #define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_LINE_DEFAULT 0x000000ff 7729 #define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_PIN_DEFAULT 0x00000000 7730 #define cfgBIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 7731 #define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP_LIST_DEFAULT 0x00000000 7732 #define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP_DEFAULT 0x0000c800 7733 #define cfgBIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL_DEFAULT 0x00000000 7734 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST_DEFAULT 0x0000a000 7735 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP_DEFAULT 0x00000062 7736 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP_DEFAULT 0x00000000 7737 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL_DEFAULT 0x00002810 7738 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS_DEFAULT 0x00000000 7739 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP_DEFAULT 0x00000d04 7740 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL_DEFAULT 0x00000000 7741 #define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS_DEFAULT 0x00002001 7742 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP_DEFAULT 0x00000000 7743 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL_DEFAULT 0x00000000 7744 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS_DEFAULT 0x00000000 7745 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP2_DEFAULT 0x00010000 7746 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL2_DEFAULT 0x00000000 7747 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS2_DEFAULT 0x00000000 7748 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP2_DEFAULT 0x0000001e 7749 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL2_DEFAULT 0x00000004 7750 #define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS2_DEFAULT 0x00000000 7751 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP2_DEFAULT 0x00000000 7752 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL2_DEFAULT 0x00000000 7753 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS2_DEFAULT 0x00000000 7754 #define cfgBIF_CFG_DEV0_SWDS0_MSI_CAP_LIST_DEFAULT 0x0000c000 7755 #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL_DEFAULT 0x00000080 7756 #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 7757 #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 7758 #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_DEFAULT 0x00000000 7759 #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64_DEFAULT 0x00000000 7760 #define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP_LIST_DEFAULT 0x00000000 7761 #define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP_DEFAULT 0x00000000 7762 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 7763 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 7764 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 7765 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 7766 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 7767 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 7768 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 7769 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 7770 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 7771 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 7772 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe 7773 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 7774 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 7775 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 7776 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 7777 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 7778 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 7779 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 7780 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 7781 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 7782 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 7783 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 7784 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 7785 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 7786 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 7787 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0_DEFAULT 0x00000000 7788 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1_DEFAULT 0x00000000 7789 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2_DEFAULT 0x00000000 7790 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3_DEFAULT 0x00000000 7791 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 7792 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 7793 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 7794 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 7795 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 7796 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 7797 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 7798 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 7799 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 7800 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 7801 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 7802 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 7803 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 7804 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 7805 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 7806 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 7807 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 7808 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 7809 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 7810 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 7811 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 7812 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 7813 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 7814 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 7815 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP_DEFAULT 0x00000000 7816 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL_DEFAULT 0x00000000 7817 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41000000 7818 #define cfgBIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_CAP_DEFAULT 0x00000001 7819 #define cfgBIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000 7820 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44000000 7821 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP_16GT_DEFAULT 0x00000000 7822 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL_16GT_DEFAULT 0x00000000 7823 #define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT_DEFAULT 0x00000000 7824 #define cfgBIF_CFG_DEV0_SWDS0_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 7825 #define cfgBIF_CFG_DEV0_SWDS0_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 7826 #define cfgBIF_CFG_DEV0_SWDS0_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 7827 #define cfgBIF_CFG_DEV0_SWDS0_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 7828 #define cfgBIF_CFG_DEV0_SWDS0_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 7829 #define cfgBIF_CFG_DEV0_SWDS0_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 7830 #define cfgBIF_CFG_DEV0_SWDS0_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 7831 #define cfgBIF_CFG_DEV0_SWDS0_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 7832 #define cfgBIF_CFG_DEV0_SWDS0_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 7833 #define cfgBIF_CFG_DEV0_SWDS0_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 7834 #define cfgBIF_CFG_DEV0_SWDS0_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 7835 #define cfgBIF_CFG_DEV0_SWDS0_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 7836 #define cfgBIF_CFG_DEV0_SWDS0_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 7837 #define cfgBIF_CFG_DEV0_SWDS0_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 7838 #define cfgBIF_CFG_DEV0_SWDS0_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 7839 #define cfgBIF_CFG_DEV0_SWDS0_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 7840 #define cfgBIF_CFG_DEV0_SWDS0_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 7841 #define cfgBIF_CFG_DEV0_SWDS0_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 7842 #define cfgBIF_CFG_DEV0_SWDS0_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 7843 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x4c000000 7844 #define cfgBIF_CFG_DEV0_SWDS0_MARGINING_PORT_CAP_DEFAULT 0x00000000 7845 #define cfgBIF_CFG_DEV0_SWDS0_MARGINING_PORT_STATUS_DEFAULT 0x00000000 7846 #define cfgBIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 7847 #define cfgBIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000 7848 #define cfgBIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 7849 #define cfgBIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000 7850 #define cfgBIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 7851 #define cfgBIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000 7852 #define cfgBIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 7853 #define cfgBIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000 7854 #define cfgBIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 7855 #define cfgBIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000 7856 #define cfgBIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 7857 #define cfgBIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000 7858 #define cfgBIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 7859 #define cfgBIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000 7860 #define cfgBIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 7861 #define cfgBIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000 7862 #define cfgBIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 7863 #define cfgBIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000 7864 #define cfgBIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 7865 #define cfgBIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000 7866 #define cfgBIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 7867 #define cfgBIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000 7868 #define cfgBIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 7869 #define cfgBIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000 7870 #define cfgBIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 7871 #define cfgBIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000 7872 #define cfgBIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 7873 #define cfgBIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000 7874 #define cfgBIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 7875 #define cfgBIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000 7876 #define cfgBIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 7877 #define cfgBIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000 7878 7879 7880 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp 7881 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID_DEFAULT 0x00000000 7882 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID_DEFAULT 0x00000000 7883 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_COMMAND_DEFAULT 0x00000000 7884 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_STATUS_DEFAULT 0x00000000 7885 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID_DEFAULT 0x00000000 7886 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE_DEFAULT 0x00000000 7887 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS_DEFAULT 0x00000000 7888 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS_DEFAULT 0x00000000 7889 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE_DEFAULT 0x00000000 7890 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LATENCY_DEFAULT 0x00000000 7891 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_HEADER_DEFAULT 0x00000000 7892 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BIST_DEFAULT 0x00000000 7893 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1_DEFAULT 0x00000000 7894 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2_DEFAULT 0x00000000 7895 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3_DEFAULT 0x00000000 7896 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4_DEFAULT 0x00000000 7897 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5_DEFAULT 0x00000000 7898 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6_DEFAULT 0x00000000 7899 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 7900 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID_DEFAULT 0x73101002 7901 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR_DEFAULT 0x00000000 7902 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR_DEFAULT 0x00000048 7903 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE_DEFAULT 0x00000000 7904 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN_DEFAULT 0x00000000 7905 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT_DEFAULT 0x00000000 7906 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY_DEFAULT 0x00000000 7907 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 7908 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_DEFAULT 0x00000002 7909 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP_DEFAULT 0x00000000 7910 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL_DEFAULT 0x00000000 7911 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS_DEFAULT 0x00000000 7912 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP_DEFAULT 0x00000d04 7913 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL_DEFAULT 0x00000000 7914 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS_DEFAULT 0x00000000 7915 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2_DEFAULT 0x00010000 7916 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2_DEFAULT 0x00000000 7917 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2_DEFAULT 0x00000000 7918 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2_DEFAULT 0x0000001e 7919 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2_DEFAULT 0x00000000 7920 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2_DEFAULT 0x00000000 7921 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST_DEFAULT 0x0000c000 7922 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL_DEFAULT 0x00000082 7923 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 7924 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 7925 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_DEFAULT 0x00000000 7926 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_DEFAULT 0x00000000 7927 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 7928 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64_DEFAULT 0x00000000 7929 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_DEFAULT 0x00000000 7930 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64_DEFAULT 0x00000000 7931 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST_DEFAULT 0x00000000 7932 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 7933 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE_DEFAULT 0x00000000 7934 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA_DEFAULT 0x00000000 7935 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 7936 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 7937 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 7938 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 7939 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 7940 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 7941 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 7942 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 7943 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 7944 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 7945 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 7946 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 7947 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 7948 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 7949 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 7950 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 7951 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 7952 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 7953 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 7954 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 7955 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP_DEFAULT 0x00000000 7956 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 7957 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 7958 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP_DEFAULT 0x00000000 7959 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 7960 7961 7962 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp 7963 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID_DEFAULT 0x00000000 7964 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID_DEFAULT 0x00000000 7965 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_COMMAND_DEFAULT 0x00000000 7966 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_STATUS_DEFAULT 0x00000000 7967 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID_DEFAULT 0x00000000 7968 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE_DEFAULT 0x00000000 7969 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS_DEFAULT 0x00000000 7970 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS_DEFAULT 0x00000000 7971 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE_DEFAULT 0x00000000 7972 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LATENCY_DEFAULT 0x00000000 7973 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_HEADER_DEFAULT 0x00000000 7974 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BIST_DEFAULT 0x00000000 7975 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1_DEFAULT 0x00000000 7976 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2_DEFAULT 0x00000000 7977 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3_DEFAULT 0x00000000 7978 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4_DEFAULT 0x00000000 7979 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5_DEFAULT 0x00000000 7980 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6_DEFAULT 0x00000000 7981 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 7982 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID_DEFAULT 0x73101002 7983 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR_DEFAULT 0x00000000 7984 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR_DEFAULT 0x00000048 7985 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE_DEFAULT 0x00000000 7986 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN_DEFAULT 0x00000000 7987 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT_DEFAULT 0x00000000 7988 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY_DEFAULT 0x00000000 7989 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 7990 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_DEFAULT 0x00000002 7991 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP_DEFAULT 0x00000000 7992 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL_DEFAULT 0x00000000 7993 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS_DEFAULT 0x00000000 7994 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP_DEFAULT 0x00000d04 7995 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL_DEFAULT 0x00000000 7996 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS_DEFAULT 0x00000000 7997 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2_DEFAULT 0x00010000 7998 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2_DEFAULT 0x00000000 7999 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2_DEFAULT 0x00000000 8000 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2_DEFAULT 0x0000001e 8001 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2_DEFAULT 0x00000000 8002 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2_DEFAULT 0x00000000 8003 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST_DEFAULT 0x0000c000 8004 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL_DEFAULT 0x00000082 8005 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 8006 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 8007 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_DEFAULT 0x00000000 8008 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_DEFAULT 0x00000000 8009 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 8010 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64_DEFAULT 0x00000000 8011 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_DEFAULT 0x00000000 8012 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64_DEFAULT 0x00000000 8013 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST_DEFAULT 0x00000000 8014 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 8015 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE_DEFAULT 0x00000000 8016 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA_DEFAULT 0x00000000 8017 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 8018 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 8019 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 8020 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 8021 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 8022 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 8023 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 8024 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 8025 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 8026 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 8027 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 8028 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 8029 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 8030 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 8031 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 8032 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 8033 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 8034 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 8035 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 8036 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 8037 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP_DEFAULT 0x00000000 8038 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 8039 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 8040 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP_DEFAULT 0x00000000 8041 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 8042 8043 8044 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp 8045 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID_DEFAULT 0x00000000 8046 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID_DEFAULT 0x00000000 8047 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_COMMAND_DEFAULT 0x00000000 8048 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_STATUS_DEFAULT 0x00000000 8049 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID_DEFAULT 0x00000000 8050 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE_DEFAULT 0x00000000 8051 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS_DEFAULT 0x00000000 8052 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS_DEFAULT 0x00000000 8053 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE_DEFAULT 0x00000000 8054 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LATENCY_DEFAULT 0x00000000 8055 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_HEADER_DEFAULT 0x00000000 8056 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BIST_DEFAULT 0x00000000 8057 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1_DEFAULT 0x00000000 8058 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2_DEFAULT 0x00000000 8059 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3_DEFAULT 0x00000000 8060 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4_DEFAULT 0x00000000 8061 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5_DEFAULT 0x00000000 8062 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6_DEFAULT 0x00000000 8063 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 8064 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID_DEFAULT 0x73101002 8065 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR_DEFAULT 0x00000000 8066 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR_DEFAULT 0x00000048 8067 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE_DEFAULT 0x00000000 8068 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN_DEFAULT 0x00000000 8069 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT_DEFAULT 0x00000000 8070 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY_DEFAULT 0x00000000 8071 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 8072 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_DEFAULT 0x00000002 8073 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP_DEFAULT 0x00000000 8074 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL_DEFAULT 0x00000000 8075 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS_DEFAULT 0x00000000 8076 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP_DEFAULT 0x00000d04 8077 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL_DEFAULT 0x00000000 8078 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS_DEFAULT 0x00000000 8079 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2_DEFAULT 0x00010000 8080 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2_DEFAULT 0x00000000 8081 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2_DEFAULT 0x00000000 8082 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2_DEFAULT 0x0000001e 8083 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2_DEFAULT 0x00000000 8084 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2_DEFAULT 0x00000000 8085 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST_DEFAULT 0x0000c000 8086 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL_DEFAULT 0x00000082 8087 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 8088 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 8089 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_DEFAULT 0x00000000 8090 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_DEFAULT 0x00000000 8091 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 8092 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64_DEFAULT 0x00000000 8093 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_DEFAULT 0x00000000 8094 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64_DEFAULT 0x00000000 8095 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST_DEFAULT 0x00000000 8096 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 8097 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE_DEFAULT 0x00000000 8098 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA_DEFAULT 0x00000000 8099 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 8100 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 8101 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 8102 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 8103 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 8104 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 8105 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 8106 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 8107 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 8108 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 8109 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 8110 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 8111 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 8112 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 8113 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 8114 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 8115 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 8116 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 8117 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 8118 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 8119 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP_DEFAULT 0x00000000 8120 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 8121 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 8122 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP_DEFAULT 0x00000000 8123 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 8124 8125 8126 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp 8127 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID_DEFAULT 0x00000000 8128 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID_DEFAULT 0x00000000 8129 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_COMMAND_DEFAULT 0x00000000 8130 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_STATUS_DEFAULT 0x00000000 8131 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID_DEFAULT 0x00000000 8132 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE_DEFAULT 0x00000000 8133 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS_DEFAULT 0x00000000 8134 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS_DEFAULT 0x00000000 8135 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE_DEFAULT 0x00000000 8136 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LATENCY_DEFAULT 0x00000000 8137 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_HEADER_DEFAULT 0x00000000 8138 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BIST_DEFAULT 0x00000000 8139 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1_DEFAULT 0x00000000 8140 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2_DEFAULT 0x00000000 8141 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3_DEFAULT 0x00000000 8142 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4_DEFAULT 0x00000000 8143 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5_DEFAULT 0x00000000 8144 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6_DEFAULT 0x00000000 8145 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 8146 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID_DEFAULT 0x73101002 8147 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR_DEFAULT 0x00000000 8148 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR_DEFAULT 0x00000048 8149 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE_DEFAULT 0x00000000 8150 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN_DEFAULT 0x00000000 8151 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT_DEFAULT 0x00000000 8152 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY_DEFAULT 0x00000000 8153 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 8154 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_DEFAULT 0x00000002 8155 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP_DEFAULT 0x00000000 8156 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL_DEFAULT 0x00000000 8157 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS_DEFAULT 0x00000000 8158 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP_DEFAULT 0x00000d04 8159 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL_DEFAULT 0x00000000 8160 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS_DEFAULT 0x00000000 8161 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2_DEFAULT 0x00010000 8162 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2_DEFAULT 0x00000000 8163 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2_DEFAULT 0x00000000 8164 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2_DEFAULT 0x0000001e 8165 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2_DEFAULT 0x00000000 8166 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2_DEFAULT 0x00000000 8167 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST_DEFAULT 0x0000c000 8168 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL_DEFAULT 0x00000082 8169 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 8170 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 8171 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_DEFAULT 0x00000000 8172 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_DEFAULT 0x00000000 8173 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 8174 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64_DEFAULT 0x00000000 8175 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_DEFAULT 0x00000000 8176 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64_DEFAULT 0x00000000 8177 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST_DEFAULT 0x00000000 8178 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 8179 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE_DEFAULT 0x00000000 8180 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA_DEFAULT 0x00000000 8181 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 8182 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 8183 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 8184 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 8185 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 8186 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 8187 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 8188 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 8189 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 8190 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 8191 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 8192 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 8193 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 8194 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 8195 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 8196 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 8197 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 8198 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 8199 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 8200 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 8201 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP_DEFAULT 0x00000000 8202 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 8203 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 8204 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP_DEFAULT 0x00000000 8205 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 8206 8207 8208 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp 8209 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID_DEFAULT 0x00000000 8210 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID_DEFAULT 0x00000000 8211 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_COMMAND_DEFAULT 0x00000000 8212 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_STATUS_DEFAULT 0x00000000 8213 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID_DEFAULT 0x00000000 8214 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE_DEFAULT 0x00000000 8215 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS_DEFAULT 0x00000000 8216 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS_DEFAULT 0x00000000 8217 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE_DEFAULT 0x00000000 8218 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LATENCY_DEFAULT 0x00000000 8219 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_HEADER_DEFAULT 0x00000000 8220 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BIST_DEFAULT 0x00000000 8221 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1_DEFAULT 0x00000000 8222 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2_DEFAULT 0x00000000 8223 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3_DEFAULT 0x00000000 8224 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4_DEFAULT 0x00000000 8225 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5_DEFAULT 0x00000000 8226 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6_DEFAULT 0x00000000 8227 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 8228 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID_DEFAULT 0x73101002 8229 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR_DEFAULT 0x00000000 8230 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR_DEFAULT 0x00000048 8231 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE_DEFAULT 0x00000000 8232 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN_DEFAULT 0x00000000 8233 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT_DEFAULT 0x00000000 8234 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY_DEFAULT 0x00000000 8235 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 8236 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_DEFAULT 0x00000002 8237 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP_DEFAULT 0x00000000 8238 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL_DEFAULT 0x00000000 8239 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS_DEFAULT 0x00000000 8240 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP_DEFAULT 0x00000d04 8241 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL_DEFAULT 0x00000000 8242 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS_DEFAULT 0x00000000 8243 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2_DEFAULT 0x00010000 8244 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2_DEFAULT 0x00000000 8245 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2_DEFAULT 0x00000000 8246 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2_DEFAULT 0x0000001e 8247 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2_DEFAULT 0x00000000 8248 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2_DEFAULT 0x00000000 8249 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST_DEFAULT 0x0000c000 8250 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL_DEFAULT 0x00000082 8251 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 8252 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 8253 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_DEFAULT 0x00000000 8254 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_DEFAULT 0x00000000 8255 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 8256 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64_DEFAULT 0x00000000 8257 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_DEFAULT 0x00000000 8258 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64_DEFAULT 0x00000000 8259 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST_DEFAULT 0x00000000 8260 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 8261 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE_DEFAULT 0x00000000 8262 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA_DEFAULT 0x00000000 8263 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 8264 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 8265 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 8266 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 8267 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 8268 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 8269 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 8270 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 8271 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 8272 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 8273 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 8274 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 8275 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 8276 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 8277 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 8278 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 8279 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 8280 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 8281 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 8282 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 8283 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP_DEFAULT 0x00000000 8284 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 8285 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 8286 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP_DEFAULT 0x00000000 8287 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 8288 8289 8290 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp 8291 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID_DEFAULT 0x00000000 8292 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID_DEFAULT 0x00000000 8293 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_COMMAND_DEFAULT 0x00000000 8294 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_STATUS_DEFAULT 0x00000000 8295 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID_DEFAULT 0x00000000 8296 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE_DEFAULT 0x00000000 8297 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS_DEFAULT 0x00000000 8298 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS_DEFAULT 0x00000000 8299 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE_DEFAULT 0x00000000 8300 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LATENCY_DEFAULT 0x00000000 8301 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_HEADER_DEFAULT 0x00000000 8302 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BIST_DEFAULT 0x00000000 8303 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1_DEFAULT 0x00000000 8304 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2_DEFAULT 0x00000000 8305 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3_DEFAULT 0x00000000 8306 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4_DEFAULT 0x00000000 8307 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5_DEFAULT 0x00000000 8308 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6_DEFAULT 0x00000000 8309 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 8310 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID_DEFAULT 0x73101002 8311 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR_DEFAULT 0x00000000 8312 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR_DEFAULT 0x00000048 8313 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE_DEFAULT 0x00000000 8314 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN_DEFAULT 0x00000000 8315 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT_DEFAULT 0x00000000 8316 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY_DEFAULT 0x00000000 8317 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 8318 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_DEFAULT 0x00000002 8319 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP_DEFAULT 0x00000000 8320 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL_DEFAULT 0x00000000 8321 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS_DEFAULT 0x00000000 8322 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP_DEFAULT 0x00000d04 8323 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL_DEFAULT 0x00000000 8324 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS_DEFAULT 0x00000000 8325 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2_DEFAULT 0x00010000 8326 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2_DEFAULT 0x00000000 8327 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2_DEFAULT 0x00000000 8328 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2_DEFAULT 0x0000001e 8329 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2_DEFAULT 0x00000000 8330 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2_DEFAULT 0x00000000 8331 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST_DEFAULT 0x0000c000 8332 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL_DEFAULT 0x00000082 8333 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 8334 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 8335 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_DEFAULT 0x00000000 8336 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_DEFAULT 0x00000000 8337 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 8338 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64_DEFAULT 0x00000000 8339 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_DEFAULT 0x00000000 8340 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64_DEFAULT 0x00000000 8341 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST_DEFAULT 0x00000000 8342 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 8343 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE_DEFAULT 0x00000000 8344 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA_DEFAULT 0x00000000 8345 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 8346 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 8347 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 8348 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 8349 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 8350 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 8351 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 8352 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 8353 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 8354 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 8355 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 8356 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 8357 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 8358 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 8359 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 8360 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 8361 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 8362 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 8363 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 8364 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 8365 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP_DEFAULT 0x00000000 8366 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 8367 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 8368 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP_DEFAULT 0x00000000 8369 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 8370 8371 8372 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp 8373 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID_DEFAULT 0x00000000 8374 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID_DEFAULT 0x00000000 8375 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_COMMAND_DEFAULT 0x00000000 8376 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_STATUS_DEFAULT 0x00000000 8377 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID_DEFAULT 0x00000000 8378 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE_DEFAULT 0x00000000 8379 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS_DEFAULT 0x00000000 8380 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS_DEFAULT 0x00000000 8381 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE_DEFAULT 0x00000000 8382 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LATENCY_DEFAULT 0x00000000 8383 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_HEADER_DEFAULT 0x00000000 8384 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BIST_DEFAULT 0x00000000 8385 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1_DEFAULT 0x00000000 8386 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2_DEFAULT 0x00000000 8387 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3_DEFAULT 0x00000000 8388 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4_DEFAULT 0x00000000 8389 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5_DEFAULT 0x00000000 8390 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6_DEFAULT 0x00000000 8391 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 8392 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID_DEFAULT 0x73101002 8393 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR_DEFAULT 0x00000000 8394 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR_DEFAULT 0x00000048 8395 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE_DEFAULT 0x00000000 8396 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN_DEFAULT 0x00000000 8397 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT_DEFAULT 0x00000000 8398 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY_DEFAULT 0x00000000 8399 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 8400 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_DEFAULT 0x00000002 8401 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP_DEFAULT 0x00000000 8402 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL_DEFAULT 0x00000000 8403 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS_DEFAULT 0x00000000 8404 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP_DEFAULT 0x00000d04 8405 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL_DEFAULT 0x00000000 8406 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS_DEFAULT 0x00000000 8407 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2_DEFAULT 0x00010000 8408 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2_DEFAULT 0x00000000 8409 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2_DEFAULT 0x00000000 8410 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2_DEFAULT 0x0000001e 8411 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2_DEFAULT 0x00000000 8412 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2_DEFAULT 0x00000000 8413 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST_DEFAULT 0x0000c000 8414 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL_DEFAULT 0x00000082 8415 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 8416 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 8417 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_DEFAULT 0x00000000 8418 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_DEFAULT 0x00000000 8419 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 8420 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64_DEFAULT 0x00000000 8421 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_DEFAULT 0x00000000 8422 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64_DEFAULT 0x00000000 8423 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST_DEFAULT 0x00000000 8424 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 8425 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE_DEFAULT 0x00000000 8426 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA_DEFAULT 0x00000000 8427 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 8428 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 8429 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 8430 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 8431 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 8432 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 8433 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 8434 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 8435 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 8436 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 8437 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 8438 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 8439 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 8440 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 8441 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 8442 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 8443 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 8444 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 8445 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 8446 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 8447 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP_DEFAULT 0x00000000 8448 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 8449 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 8450 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP_DEFAULT 0x00000000 8451 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 8452 8453 8454 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp 8455 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID_DEFAULT 0x00000000 8456 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID_DEFAULT 0x00000000 8457 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_COMMAND_DEFAULT 0x00000000 8458 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_STATUS_DEFAULT 0x00000000 8459 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID_DEFAULT 0x00000000 8460 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE_DEFAULT 0x00000000 8461 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS_DEFAULT 0x00000000 8462 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS_DEFAULT 0x00000000 8463 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE_DEFAULT 0x00000000 8464 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LATENCY_DEFAULT 0x00000000 8465 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_HEADER_DEFAULT 0x00000000 8466 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BIST_DEFAULT 0x00000000 8467 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1_DEFAULT 0x00000000 8468 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2_DEFAULT 0x00000000 8469 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3_DEFAULT 0x00000000 8470 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4_DEFAULT 0x00000000 8471 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5_DEFAULT 0x00000000 8472 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6_DEFAULT 0x00000000 8473 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 8474 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID_DEFAULT 0x73101002 8475 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR_DEFAULT 0x00000000 8476 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR_DEFAULT 0x00000048 8477 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE_DEFAULT 0x00000000 8478 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN_DEFAULT 0x00000000 8479 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT_DEFAULT 0x00000000 8480 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY_DEFAULT 0x00000000 8481 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 8482 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_DEFAULT 0x00000002 8483 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP_DEFAULT 0x00000000 8484 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL_DEFAULT 0x00000000 8485 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS_DEFAULT 0x00000000 8486 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP_DEFAULT 0x00000d04 8487 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL_DEFAULT 0x00000000 8488 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS_DEFAULT 0x00000000 8489 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2_DEFAULT 0x00010000 8490 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2_DEFAULT 0x00000000 8491 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2_DEFAULT 0x00000000 8492 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2_DEFAULT 0x0000001e 8493 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2_DEFAULT 0x00000000 8494 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2_DEFAULT 0x00000000 8495 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST_DEFAULT 0x0000c000 8496 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL_DEFAULT 0x00000082 8497 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 8498 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 8499 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_DEFAULT 0x00000000 8500 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_DEFAULT 0x00000000 8501 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 8502 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64_DEFAULT 0x00000000 8503 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_DEFAULT 0x00000000 8504 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64_DEFAULT 0x00000000 8505 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST_DEFAULT 0x00000000 8506 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 8507 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE_DEFAULT 0x00000000 8508 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA_DEFAULT 0x00000000 8509 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 8510 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 8511 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 8512 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 8513 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 8514 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 8515 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 8516 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 8517 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 8518 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 8519 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 8520 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 8521 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 8522 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 8523 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 8524 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 8525 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 8526 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 8527 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 8528 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 8529 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP_DEFAULT 0x00000000 8530 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 8531 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 8532 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP_DEFAULT 0x00000000 8533 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 8534 8535 8536 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp 8537 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID_DEFAULT 0x00000000 8538 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID_DEFAULT 0x00000000 8539 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_COMMAND_DEFAULT 0x00000000 8540 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_STATUS_DEFAULT 0x00000000 8541 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID_DEFAULT 0x00000000 8542 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE_DEFAULT 0x00000000 8543 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS_DEFAULT 0x00000000 8544 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS_DEFAULT 0x00000000 8545 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE_DEFAULT 0x00000000 8546 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LATENCY_DEFAULT 0x00000000 8547 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_HEADER_DEFAULT 0x00000000 8548 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BIST_DEFAULT 0x00000000 8549 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1_DEFAULT 0x00000000 8550 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2_DEFAULT 0x00000000 8551 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3_DEFAULT 0x00000000 8552 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4_DEFAULT 0x00000000 8553 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5_DEFAULT 0x00000000 8554 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6_DEFAULT 0x00000000 8555 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 8556 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID_DEFAULT 0x73101002 8557 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR_DEFAULT 0x00000000 8558 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR_DEFAULT 0x00000048 8559 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE_DEFAULT 0x00000000 8560 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN_DEFAULT 0x00000000 8561 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT_DEFAULT 0x00000000 8562 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY_DEFAULT 0x00000000 8563 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 8564 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_DEFAULT 0x00000002 8565 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP_DEFAULT 0x00000000 8566 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL_DEFAULT 0x00000000 8567 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS_DEFAULT 0x00000000 8568 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP_DEFAULT 0x00000d04 8569 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL_DEFAULT 0x00000000 8570 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS_DEFAULT 0x00000000 8571 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2_DEFAULT 0x00010000 8572 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2_DEFAULT 0x00000000 8573 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2_DEFAULT 0x00000000 8574 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2_DEFAULT 0x0000001e 8575 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2_DEFAULT 0x00000000 8576 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2_DEFAULT 0x00000000 8577 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST_DEFAULT 0x0000c000 8578 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL_DEFAULT 0x00000082 8579 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 8580 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 8581 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_DEFAULT 0x00000000 8582 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_DEFAULT 0x00000000 8583 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 8584 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64_DEFAULT 0x00000000 8585 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_DEFAULT 0x00000000 8586 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64_DEFAULT 0x00000000 8587 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST_DEFAULT 0x00000000 8588 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 8589 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE_DEFAULT 0x00000000 8590 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA_DEFAULT 0x00000000 8591 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 8592 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 8593 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 8594 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 8595 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 8596 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 8597 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 8598 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 8599 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 8600 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 8601 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 8602 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 8603 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 8604 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 8605 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 8606 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 8607 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 8608 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 8609 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 8610 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 8611 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP_DEFAULT 0x00000000 8612 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 8613 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 8614 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP_DEFAULT 0x00000000 8615 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 8616 8617 8618 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp 8619 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID_DEFAULT 0x00000000 8620 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID_DEFAULT 0x00000000 8621 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_COMMAND_DEFAULT 0x00000000 8622 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_STATUS_DEFAULT 0x00000000 8623 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID_DEFAULT 0x00000000 8624 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE_DEFAULT 0x00000000 8625 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS_DEFAULT 0x00000000 8626 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS_DEFAULT 0x00000000 8627 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE_DEFAULT 0x00000000 8628 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LATENCY_DEFAULT 0x00000000 8629 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_HEADER_DEFAULT 0x00000000 8630 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BIST_DEFAULT 0x00000000 8631 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1_DEFAULT 0x00000000 8632 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2_DEFAULT 0x00000000 8633 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3_DEFAULT 0x00000000 8634 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4_DEFAULT 0x00000000 8635 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5_DEFAULT 0x00000000 8636 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6_DEFAULT 0x00000000 8637 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 8638 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID_DEFAULT 0x73101002 8639 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR_DEFAULT 0x00000000 8640 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR_DEFAULT 0x00000048 8641 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE_DEFAULT 0x00000000 8642 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN_DEFAULT 0x00000000 8643 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT_DEFAULT 0x00000000 8644 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY_DEFAULT 0x00000000 8645 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 8646 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_DEFAULT 0x00000002 8647 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP_DEFAULT 0x00000000 8648 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL_DEFAULT 0x00000000 8649 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS_DEFAULT 0x00000000 8650 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP_DEFAULT 0x00000d04 8651 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL_DEFAULT 0x00000000 8652 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS_DEFAULT 0x00000000 8653 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2_DEFAULT 0x00010000 8654 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2_DEFAULT 0x00000000 8655 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2_DEFAULT 0x00000000 8656 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2_DEFAULT 0x0000001e 8657 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2_DEFAULT 0x00000000 8658 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2_DEFAULT 0x00000000 8659 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST_DEFAULT 0x0000c000 8660 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL_DEFAULT 0x00000082 8661 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 8662 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 8663 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_DEFAULT 0x00000000 8664 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_DEFAULT 0x00000000 8665 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 8666 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64_DEFAULT 0x00000000 8667 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_DEFAULT 0x00000000 8668 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64_DEFAULT 0x00000000 8669 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST_DEFAULT 0x00000000 8670 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 8671 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE_DEFAULT 0x00000000 8672 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA_DEFAULT 0x00000000 8673 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 8674 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 8675 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 8676 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 8677 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 8678 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 8679 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 8680 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 8681 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 8682 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 8683 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 8684 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 8685 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 8686 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 8687 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 8688 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 8689 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 8690 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 8691 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 8692 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 8693 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP_DEFAULT 0x00000000 8694 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 8695 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 8696 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP_DEFAULT 0x00000000 8697 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 8698 8699 8700 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp 8701 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID_DEFAULT 0x00000000 8702 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID_DEFAULT 0x00000000 8703 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_COMMAND_DEFAULT 0x00000000 8704 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_STATUS_DEFAULT 0x00000000 8705 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID_DEFAULT 0x00000000 8706 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE_DEFAULT 0x00000000 8707 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS_DEFAULT 0x00000000 8708 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS_DEFAULT 0x00000000 8709 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE_DEFAULT 0x00000000 8710 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LATENCY_DEFAULT 0x00000000 8711 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_HEADER_DEFAULT 0x00000000 8712 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BIST_DEFAULT 0x00000000 8713 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1_DEFAULT 0x00000000 8714 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2_DEFAULT 0x00000000 8715 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3_DEFAULT 0x00000000 8716 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4_DEFAULT 0x00000000 8717 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5_DEFAULT 0x00000000 8718 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6_DEFAULT 0x00000000 8719 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 8720 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID_DEFAULT 0x73101002 8721 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR_DEFAULT 0x00000000 8722 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR_DEFAULT 0x00000048 8723 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE_DEFAULT 0x00000000 8724 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN_DEFAULT 0x00000000 8725 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT_DEFAULT 0x00000000 8726 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY_DEFAULT 0x00000000 8727 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 8728 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_DEFAULT 0x00000002 8729 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP_DEFAULT 0x00000000 8730 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL_DEFAULT 0x00000000 8731 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS_DEFAULT 0x00000000 8732 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP_DEFAULT 0x00000d04 8733 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL_DEFAULT 0x00000000 8734 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS_DEFAULT 0x00000000 8735 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2_DEFAULT 0x00010000 8736 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2_DEFAULT 0x00000000 8737 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2_DEFAULT 0x00000000 8738 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2_DEFAULT 0x0000001e 8739 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2_DEFAULT 0x00000000 8740 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2_DEFAULT 0x00000000 8741 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST_DEFAULT 0x0000c000 8742 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL_DEFAULT 0x00000082 8743 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 8744 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 8745 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_DEFAULT 0x00000000 8746 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_DEFAULT 0x00000000 8747 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 8748 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64_DEFAULT 0x00000000 8749 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_DEFAULT 0x00000000 8750 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64_DEFAULT 0x00000000 8751 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST_DEFAULT 0x00000000 8752 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 8753 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE_DEFAULT 0x00000000 8754 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA_DEFAULT 0x00000000 8755 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 8756 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 8757 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 8758 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 8759 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 8760 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 8761 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 8762 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 8763 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 8764 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 8765 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 8766 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 8767 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 8768 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 8769 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 8770 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 8771 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 8772 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 8773 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 8774 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 8775 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP_DEFAULT 0x00000000 8776 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 8777 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 8778 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP_DEFAULT 0x00000000 8779 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 8780 8781 8782 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp 8783 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID_DEFAULT 0x00000000 8784 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID_DEFAULT 0x00000000 8785 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_COMMAND_DEFAULT 0x00000000 8786 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_STATUS_DEFAULT 0x00000000 8787 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID_DEFAULT 0x00000000 8788 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE_DEFAULT 0x00000000 8789 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS_DEFAULT 0x00000000 8790 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS_DEFAULT 0x00000000 8791 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE_DEFAULT 0x00000000 8792 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LATENCY_DEFAULT 0x00000000 8793 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_HEADER_DEFAULT 0x00000000 8794 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BIST_DEFAULT 0x00000000 8795 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1_DEFAULT 0x00000000 8796 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2_DEFAULT 0x00000000 8797 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3_DEFAULT 0x00000000 8798 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4_DEFAULT 0x00000000 8799 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5_DEFAULT 0x00000000 8800 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6_DEFAULT 0x00000000 8801 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 8802 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID_DEFAULT 0x73101002 8803 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR_DEFAULT 0x00000000 8804 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR_DEFAULT 0x00000048 8805 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE_DEFAULT 0x00000000 8806 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN_DEFAULT 0x00000000 8807 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT_DEFAULT 0x00000000 8808 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY_DEFAULT 0x00000000 8809 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 8810 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_DEFAULT 0x00000002 8811 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP_DEFAULT 0x00000000 8812 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL_DEFAULT 0x00000000 8813 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS_DEFAULT 0x00000000 8814 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP_DEFAULT 0x00000d04 8815 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL_DEFAULT 0x00000000 8816 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS_DEFAULT 0x00000000 8817 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2_DEFAULT 0x00010000 8818 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2_DEFAULT 0x00000000 8819 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2_DEFAULT 0x00000000 8820 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2_DEFAULT 0x0000001e 8821 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2_DEFAULT 0x00000000 8822 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2_DEFAULT 0x00000000 8823 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST_DEFAULT 0x0000c000 8824 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL_DEFAULT 0x00000082 8825 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 8826 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 8827 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_DEFAULT 0x00000000 8828 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_DEFAULT 0x00000000 8829 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 8830 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64_DEFAULT 0x00000000 8831 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_DEFAULT 0x00000000 8832 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64_DEFAULT 0x00000000 8833 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST_DEFAULT 0x00000000 8834 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 8835 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE_DEFAULT 0x00000000 8836 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA_DEFAULT 0x00000000 8837 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 8838 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 8839 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 8840 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 8841 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 8842 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 8843 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 8844 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 8845 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 8846 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 8847 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 8848 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 8849 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 8850 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 8851 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 8852 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 8853 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 8854 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 8855 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 8856 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 8857 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP_DEFAULT 0x00000000 8858 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 8859 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 8860 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP_DEFAULT 0x00000000 8861 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 8862 8863 8864 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp 8865 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID_DEFAULT 0x00000000 8866 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID_DEFAULT 0x00000000 8867 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_COMMAND_DEFAULT 0x00000000 8868 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_STATUS_DEFAULT 0x00000000 8869 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID_DEFAULT 0x00000000 8870 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE_DEFAULT 0x00000000 8871 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS_DEFAULT 0x00000000 8872 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS_DEFAULT 0x00000000 8873 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE_DEFAULT 0x00000000 8874 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LATENCY_DEFAULT 0x00000000 8875 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_HEADER_DEFAULT 0x00000000 8876 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BIST_DEFAULT 0x00000000 8877 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1_DEFAULT 0x00000000 8878 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2_DEFAULT 0x00000000 8879 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3_DEFAULT 0x00000000 8880 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4_DEFAULT 0x00000000 8881 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5_DEFAULT 0x00000000 8882 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6_DEFAULT 0x00000000 8883 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 8884 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID_DEFAULT 0x73101002 8885 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR_DEFAULT 0x00000000 8886 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR_DEFAULT 0x00000048 8887 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE_DEFAULT 0x00000000 8888 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN_DEFAULT 0x00000000 8889 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT_DEFAULT 0x00000000 8890 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY_DEFAULT 0x00000000 8891 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 8892 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_DEFAULT 0x00000002 8893 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP_DEFAULT 0x00000000 8894 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL_DEFAULT 0x00000000 8895 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS_DEFAULT 0x00000000 8896 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP_DEFAULT 0x00000d04 8897 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL_DEFAULT 0x00000000 8898 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS_DEFAULT 0x00000000 8899 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2_DEFAULT 0x00010000 8900 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2_DEFAULT 0x00000000 8901 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2_DEFAULT 0x00000000 8902 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2_DEFAULT 0x0000001e 8903 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2_DEFAULT 0x00000000 8904 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2_DEFAULT 0x00000000 8905 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST_DEFAULT 0x0000c000 8906 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL_DEFAULT 0x00000082 8907 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 8908 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 8909 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_DEFAULT 0x00000000 8910 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_DEFAULT 0x00000000 8911 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 8912 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64_DEFAULT 0x00000000 8913 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_DEFAULT 0x00000000 8914 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64_DEFAULT 0x00000000 8915 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST_DEFAULT 0x00000000 8916 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 8917 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE_DEFAULT 0x00000000 8918 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA_DEFAULT 0x00000000 8919 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 8920 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 8921 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 8922 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 8923 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 8924 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 8925 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 8926 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 8927 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 8928 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 8929 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 8930 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 8931 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 8932 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 8933 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 8934 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 8935 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 8936 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 8937 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 8938 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 8939 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP_DEFAULT 0x00000000 8940 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 8941 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 8942 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP_DEFAULT 0x00000000 8943 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 8944 8945 8946 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp 8947 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID_DEFAULT 0x00000000 8948 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID_DEFAULT 0x00000000 8949 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_COMMAND_DEFAULT 0x00000000 8950 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_STATUS_DEFAULT 0x00000000 8951 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID_DEFAULT 0x00000000 8952 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE_DEFAULT 0x00000000 8953 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS_DEFAULT 0x00000000 8954 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS_DEFAULT 0x00000000 8955 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE_DEFAULT 0x00000000 8956 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LATENCY_DEFAULT 0x00000000 8957 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_HEADER_DEFAULT 0x00000000 8958 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BIST_DEFAULT 0x00000000 8959 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1_DEFAULT 0x00000000 8960 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2_DEFAULT 0x00000000 8961 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3_DEFAULT 0x00000000 8962 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4_DEFAULT 0x00000000 8963 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5_DEFAULT 0x00000000 8964 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6_DEFAULT 0x00000000 8965 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 8966 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID_DEFAULT 0x73101002 8967 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR_DEFAULT 0x00000000 8968 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR_DEFAULT 0x00000048 8969 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE_DEFAULT 0x00000000 8970 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN_DEFAULT 0x00000000 8971 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT_DEFAULT 0x00000000 8972 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY_DEFAULT 0x00000000 8973 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 8974 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_DEFAULT 0x00000002 8975 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP_DEFAULT 0x00000000 8976 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL_DEFAULT 0x00000000 8977 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS_DEFAULT 0x00000000 8978 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP_DEFAULT 0x00000d04 8979 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL_DEFAULT 0x00000000 8980 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS_DEFAULT 0x00000000 8981 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2_DEFAULT 0x00010000 8982 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2_DEFAULT 0x00000000 8983 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2_DEFAULT 0x00000000 8984 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2_DEFAULT 0x0000001e 8985 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2_DEFAULT 0x00000000 8986 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2_DEFAULT 0x00000000 8987 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST_DEFAULT 0x0000c000 8988 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL_DEFAULT 0x00000082 8989 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 8990 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 8991 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_DEFAULT 0x00000000 8992 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_DEFAULT 0x00000000 8993 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 8994 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64_DEFAULT 0x00000000 8995 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_DEFAULT 0x00000000 8996 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64_DEFAULT 0x00000000 8997 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST_DEFAULT 0x00000000 8998 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 8999 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE_DEFAULT 0x00000000 9000 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA_DEFAULT 0x00000000 9001 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 9002 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 9003 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 9004 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 9005 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 9006 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 9007 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 9008 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 9009 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 9010 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 9011 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 9012 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 9013 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 9014 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 9015 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 9016 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 9017 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 9018 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 9019 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 9020 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 9021 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP_DEFAULT 0x00000000 9022 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 9023 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 9024 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP_DEFAULT 0x00000000 9025 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 9026 9027 9028 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp 9029 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID_DEFAULT 0x00000000 9030 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID_DEFAULT 0x00000000 9031 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_COMMAND_DEFAULT 0x00000000 9032 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_STATUS_DEFAULT 0x00000000 9033 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID_DEFAULT 0x00000000 9034 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE_DEFAULT 0x00000000 9035 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS_DEFAULT 0x00000000 9036 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS_DEFAULT 0x00000000 9037 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE_DEFAULT 0x00000000 9038 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LATENCY_DEFAULT 0x00000000 9039 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_HEADER_DEFAULT 0x00000000 9040 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BIST_DEFAULT 0x00000000 9041 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1_DEFAULT 0x00000000 9042 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2_DEFAULT 0x00000000 9043 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3_DEFAULT 0x00000000 9044 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4_DEFAULT 0x00000000 9045 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5_DEFAULT 0x00000000 9046 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6_DEFAULT 0x00000000 9047 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 9048 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID_DEFAULT 0x73101002 9049 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR_DEFAULT 0x00000000 9050 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR_DEFAULT 0x00000048 9051 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE_DEFAULT 0x00000000 9052 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN_DEFAULT 0x00000000 9053 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT_DEFAULT 0x00000000 9054 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY_DEFAULT 0x00000000 9055 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 9056 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_DEFAULT 0x00000002 9057 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP_DEFAULT 0x00000000 9058 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL_DEFAULT 0x00000000 9059 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS_DEFAULT 0x00000000 9060 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP_DEFAULT 0x00000d04 9061 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL_DEFAULT 0x00000000 9062 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS_DEFAULT 0x00000000 9063 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2_DEFAULT 0x00010000 9064 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2_DEFAULT 0x00000000 9065 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2_DEFAULT 0x00000000 9066 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2_DEFAULT 0x0000001e 9067 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2_DEFAULT 0x00000000 9068 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2_DEFAULT 0x00000000 9069 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST_DEFAULT 0x0000c000 9070 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL_DEFAULT 0x00000082 9071 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 9072 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 9073 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_DEFAULT 0x00000000 9074 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_DEFAULT 0x00000000 9075 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 9076 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64_DEFAULT 0x00000000 9077 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_DEFAULT 0x00000000 9078 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64_DEFAULT 0x00000000 9079 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST_DEFAULT 0x00000000 9080 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 9081 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE_DEFAULT 0x00000000 9082 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA_DEFAULT 0x00000000 9083 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 9084 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 9085 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 9086 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 9087 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 9088 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 9089 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 9090 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 9091 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 9092 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 9093 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 9094 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 9095 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 9096 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 9097 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 9098 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 9099 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 9100 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 9101 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 9102 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 9103 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP_DEFAULT 0x00000000 9104 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 9105 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 9106 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP_DEFAULT 0x00000000 9107 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 9108 9109 9110 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp 9111 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID_DEFAULT 0x00000000 9112 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID_DEFAULT 0x00000000 9113 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_COMMAND_DEFAULT 0x00000000 9114 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_STATUS_DEFAULT 0x00000000 9115 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID_DEFAULT 0x00000000 9116 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE_DEFAULT 0x00000000 9117 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS_DEFAULT 0x00000000 9118 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS_DEFAULT 0x00000000 9119 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE_DEFAULT 0x00000000 9120 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LATENCY_DEFAULT 0x00000000 9121 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_HEADER_DEFAULT 0x00000000 9122 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BIST_DEFAULT 0x00000000 9123 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1_DEFAULT 0x00000000 9124 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2_DEFAULT 0x00000000 9125 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3_DEFAULT 0x00000000 9126 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4_DEFAULT 0x00000000 9127 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5_DEFAULT 0x00000000 9128 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6_DEFAULT 0x00000000 9129 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 9130 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID_DEFAULT 0x73101002 9131 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR_DEFAULT 0x00000000 9132 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR_DEFAULT 0x00000048 9133 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE_DEFAULT 0x00000000 9134 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN_DEFAULT 0x00000000 9135 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT_DEFAULT 0x00000000 9136 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY_DEFAULT 0x00000000 9137 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 9138 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_DEFAULT 0x00000002 9139 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP_DEFAULT 0x00000000 9140 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL_DEFAULT 0x00000000 9141 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS_DEFAULT 0x00000000 9142 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP_DEFAULT 0x00000d04 9143 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL_DEFAULT 0x00000000 9144 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS_DEFAULT 0x00000000 9145 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2_DEFAULT 0x00010000 9146 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2_DEFAULT 0x00000000 9147 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2_DEFAULT 0x00000000 9148 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2_DEFAULT 0x0000001e 9149 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2_DEFAULT 0x00000000 9150 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2_DEFAULT 0x00000000 9151 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST_DEFAULT 0x0000c000 9152 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL_DEFAULT 0x00000082 9153 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 9154 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 9155 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_DEFAULT 0x00000000 9156 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_DEFAULT 0x00000000 9157 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 9158 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64_DEFAULT 0x00000000 9159 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_DEFAULT 0x00000000 9160 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64_DEFAULT 0x00000000 9161 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST_DEFAULT 0x00000000 9162 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 9163 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE_DEFAULT 0x00000000 9164 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA_DEFAULT 0x00000000 9165 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 9166 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 9167 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 9168 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 9169 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 9170 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 9171 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 9172 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 9173 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 9174 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 9175 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 9176 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 9177 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 9178 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 9179 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 9180 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 9181 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 9182 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 9183 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 9184 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 9185 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP_DEFAULT 0x00000000 9186 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 9187 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 9188 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP_DEFAULT 0x00000000 9189 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 9190 9191 9192 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf16_bifcfgdecp 9193 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_VENDOR_ID_DEFAULT 0x00000000 9194 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_ID_DEFAULT 0x00000000 9195 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_COMMAND_DEFAULT 0x00000000 9196 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_STATUS_DEFAULT 0x00000000 9197 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_REVISION_ID_DEFAULT 0x00000000 9198 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PROG_INTERFACE_DEFAULT 0x00000000 9199 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_SUB_CLASS_DEFAULT 0x00000000 9200 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_CLASS_DEFAULT 0x00000000 9201 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_CACHE_LINE_DEFAULT 0x00000000 9202 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_LATENCY_DEFAULT 0x00000000 9203 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_HEADER_DEFAULT 0x00000000 9204 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_BIST_DEFAULT 0x00000000 9205 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_1_DEFAULT 0x00000000 9206 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_2_DEFAULT 0x00000000 9207 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_3_DEFAULT 0x00000000 9208 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_4_DEFAULT 0x00000000 9209 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_5_DEFAULT 0x00000000 9210 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_6_DEFAULT 0x00000000 9211 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 9212 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_ADAPTER_ID_DEFAULT 0x73101002 9213 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_ROM_BASE_ADDR_DEFAULT 0x00000000 9214 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_CAP_PTR_DEFAULT 0x00000048 9215 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_LINE_DEFAULT 0x00000000 9216 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_PIN_DEFAULT 0x00000000 9217 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MIN_GRANT_DEFAULT 0x00000000 9218 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MAX_LATENCY_DEFAULT 0x00000000 9219 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 9220 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP_DEFAULT 0x00000002 9221 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP_DEFAULT 0x00000000 9222 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL_DEFAULT 0x00000000 9223 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS_DEFAULT 0x00000000 9224 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP_DEFAULT 0x00000d04 9225 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL_DEFAULT 0x00000000 9226 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS_DEFAULT 0x00000000 9227 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2_DEFAULT 0x00010000 9228 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2_DEFAULT 0x00000000 9229 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS2_DEFAULT 0x00000000 9230 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2_DEFAULT 0x0000001e 9231 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2_DEFAULT 0x00000000 9232 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2_DEFAULT 0x00000000 9233 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_CAP_LIST_DEFAULT 0x0000c000 9234 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL_DEFAULT 0x00000082 9235 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 9236 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 9237 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA_DEFAULT 0x00000000 9238 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK_DEFAULT 0x00000000 9239 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 9240 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK_64_DEFAULT 0x00000000 9241 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING_DEFAULT 0x00000000 9242 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING_64_DEFAULT 0x00000000 9243 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSIX_CAP_LIST_DEFAULT 0x00000000 9244 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 9245 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSIX_TABLE_DEFAULT 0x00000000 9246 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSIX_PBA_DEFAULT 0x00000000 9247 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 9248 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 9249 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 9250 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 9251 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 9252 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 9253 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 9254 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 9255 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 9256 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 9257 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 9258 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 9259 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 9260 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 9261 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 9262 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 9263 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 9264 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 9265 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 9266 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 9267 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP_DEFAULT 0x00000000 9268 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 9269 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 9270 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP_DEFAULT 0x00000000 9271 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 9272 9273 9274 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf17_bifcfgdecp 9275 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_VENDOR_ID_DEFAULT 0x00000000 9276 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_ID_DEFAULT 0x00000000 9277 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_COMMAND_DEFAULT 0x00000000 9278 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_STATUS_DEFAULT 0x00000000 9279 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_REVISION_ID_DEFAULT 0x00000000 9280 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PROG_INTERFACE_DEFAULT 0x00000000 9281 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_SUB_CLASS_DEFAULT 0x00000000 9282 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_CLASS_DEFAULT 0x00000000 9283 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_CACHE_LINE_DEFAULT 0x00000000 9284 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_LATENCY_DEFAULT 0x00000000 9285 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_HEADER_DEFAULT 0x00000000 9286 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_BIST_DEFAULT 0x00000000 9287 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_1_DEFAULT 0x00000000 9288 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_2_DEFAULT 0x00000000 9289 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_3_DEFAULT 0x00000000 9290 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_4_DEFAULT 0x00000000 9291 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_5_DEFAULT 0x00000000 9292 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_6_DEFAULT 0x00000000 9293 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 9294 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_ADAPTER_ID_DEFAULT 0x73101002 9295 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_ROM_BASE_ADDR_DEFAULT 0x00000000 9296 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_CAP_PTR_DEFAULT 0x00000048 9297 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_LINE_DEFAULT 0x00000000 9298 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_PIN_DEFAULT 0x00000000 9299 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MIN_GRANT_DEFAULT 0x00000000 9300 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MAX_LATENCY_DEFAULT 0x00000000 9301 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 9302 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP_DEFAULT 0x00000002 9303 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP_DEFAULT 0x00000000 9304 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL_DEFAULT 0x00000000 9305 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS_DEFAULT 0x00000000 9306 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP_DEFAULT 0x00000d04 9307 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL_DEFAULT 0x00000000 9308 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS_DEFAULT 0x00000000 9309 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2_DEFAULT 0x00010000 9310 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2_DEFAULT 0x00000000 9311 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS2_DEFAULT 0x00000000 9312 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2_DEFAULT 0x0000001e 9313 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2_DEFAULT 0x00000000 9314 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2_DEFAULT 0x00000000 9315 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_CAP_LIST_DEFAULT 0x0000c000 9316 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL_DEFAULT 0x00000082 9317 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 9318 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 9319 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA_DEFAULT 0x00000000 9320 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK_DEFAULT 0x00000000 9321 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 9322 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK_64_DEFAULT 0x00000000 9323 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING_DEFAULT 0x00000000 9324 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING_64_DEFAULT 0x00000000 9325 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSIX_CAP_LIST_DEFAULT 0x00000000 9326 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 9327 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSIX_TABLE_DEFAULT 0x00000000 9328 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSIX_PBA_DEFAULT 0x00000000 9329 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 9330 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 9331 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 9332 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 9333 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 9334 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 9335 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 9336 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 9337 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 9338 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 9339 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 9340 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 9341 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 9342 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 9343 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 9344 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 9345 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 9346 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 9347 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 9348 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 9349 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP_DEFAULT 0x00000000 9350 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 9351 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 9352 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP_DEFAULT 0x00000000 9353 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 9354 9355 9356 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf18_bifcfgdecp 9357 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_VENDOR_ID_DEFAULT 0x00000000 9358 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_ID_DEFAULT 0x00000000 9359 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_COMMAND_DEFAULT 0x00000000 9360 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_STATUS_DEFAULT 0x00000000 9361 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_REVISION_ID_DEFAULT 0x00000000 9362 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PROG_INTERFACE_DEFAULT 0x00000000 9363 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_SUB_CLASS_DEFAULT 0x00000000 9364 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_CLASS_DEFAULT 0x00000000 9365 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_CACHE_LINE_DEFAULT 0x00000000 9366 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_LATENCY_DEFAULT 0x00000000 9367 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_HEADER_DEFAULT 0x00000000 9368 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_BIST_DEFAULT 0x00000000 9369 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_1_DEFAULT 0x00000000 9370 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_2_DEFAULT 0x00000000 9371 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_3_DEFAULT 0x00000000 9372 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_4_DEFAULT 0x00000000 9373 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_5_DEFAULT 0x00000000 9374 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_6_DEFAULT 0x00000000 9375 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 9376 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_ADAPTER_ID_DEFAULT 0x73101002 9377 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_ROM_BASE_ADDR_DEFAULT 0x00000000 9378 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_CAP_PTR_DEFAULT 0x00000048 9379 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_LINE_DEFAULT 0x00000000 9380 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_PIN_DEFAULT 0x00000000 9381 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MIN_GRANT_DEFAULT 0x00000000 9382 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MAX_LATENCY_DEFAULT 0x00000000 9383 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 9384 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP_DEFAULT 0x00000002 9385 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP_DEFAULT 0x00000000 9386 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL_DEFAULT 0x00000000 9387 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS_DEFAULT 0x00000000 9388 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP_DEFAULT 0x00000d04 9389 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL_DEFAULT 0x00000000 9390 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS_DEFAULT 0x00000000 9391 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2_DEFAULT 0x00010000 9392 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2_DEFAULT 0x00000000 9393 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS2_DEFAULT 0x00000000 9394 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2_DEFAULT 0x0000001e 9395 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2_DEFAULT 0x00000000 9396 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2_DEFAULT 0x00000000 9397 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_CAP_LIST_DEFAULT 0x0000c000 9398 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL_DEFAULT 0x00000082 9399 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 9400 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 9401 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA_DEFAULT 0x00000000 9402 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK_DEFAULT 0x00000000 9403 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 9404 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK_64_DEFAULT 0x00000000 9405 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING_DEFAULT 0x00000000 9406 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING_64_DEFAULT 0x00000000 9407 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSIX_CAP_LIST_DEFAULT 0x00000000 9408 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 9409 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSIX_TABLE_DEFAULT 0x00000000 9410 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSIX_PBA_DEFAULT 0x00000000 9411 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 9412 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 9413 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 9414 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 9415 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 9416 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 9417 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 9418 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 9419 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 9420 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 9421 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 9422 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 9423 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 9424 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 9425 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 9426 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 9427 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 9428 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 9429 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 9430 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 9431 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP_DEFAULT 0x00000000 9432 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 9433 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 9434 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP_DEFAULT 0x00000000 9435 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 9436 9437 9438 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf19_bifcfgdecp 9439 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_VENDOR_ID_DEFAULT 0x00000000 9440 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_ID_DEFAULT 0x00000000 9441 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_COMMAND_DEFAULT 0x00000000 9442 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_STATUS_DEFAULT 0x00000000 9443 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_REVISION_ID_DEFAULT 0x00000000 9444 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PROG_INTERFACE_DEFAULT 0x00000000 9445 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_SUB_CLASS_DEFAULT 0x00000000 9446 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_CLASS_DEFAULT 0x00000000 9447 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_CACHE_LINE_DEFAULT 0x00000000 9448 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_LATENCY_DEFAULT 0x00000000 9449 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_HEADER_DEFAULT 0x00000000 9450 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_BIST_DEFAULT 0x00000000 9451 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_1_DEFAULT 0x00000000 9452 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_2_DEFAULT 0x00000000 9453 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_3_DEFAULT 0x00000000 9454 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_4_DEFAULT 0x00000000 9455 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_5_DEFAULT 0x00000000 9456 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_6_DEFAULT 0x00000000 9457 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 9458 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_ADAPTER_ID_DEFAULT 0x73101002 9459 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_ROM_BASE_ADDR_DEFAULT 0x00000000 9460 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_CAP_PTR_DEFAULT 0x00000048 9461 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_LINE_DEFAULT 0x00000000 9462 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_PIN_DEFAULT 0x00000000 9463 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MIN_GRANT_DEFAULT 0x00000000 9464 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MAX_LATENCY_DEFAULT 0x00000000 9465 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 9466 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP_DEFAULT 0x00000002 9467 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP_DEFAULT 0x00000000 9468 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL_DEFAULT 0x00000000 9469 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS_DEFAULT 0x00000000 9470 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP_DEFAULT 0x00000d04 9471 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL_DEFAULT 0x00000000 9472 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS_DEFAULT 0x00000000 9473 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2_DEFAULT 0x00010000 9474 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2_DEFAULT 0x00000000 9475 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS2_DEFAULT 0x00000000 9476 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2_DEFAULT 0x0000001e 9477 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2_DEFAULT 0x00000000 9478 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2_DEFAULT 0x00000000 9479 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_CAP_LIST_DEFAULT 0x0000c000 9480 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL_DEFAULT 0x00000082 9481 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 9482 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 9483 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA_DEFAULT 0x00000000 9484 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK_DEFAULT 0x00000000 9485 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 9486 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK_64_DEFAULT 0x00000000 9487 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING_DEFAULT 0x00000000 9488 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING_64_DEFAULT 0x00000000 9489 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSIX_CAP_LIST_DEFAULT 0x00000000 9490 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 9491 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSIX_TABLE_DEFAULT 0x00000000 9492 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSIX_PBA_DEFAULT 0x00000000 9493 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 9494 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 9495 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 9496 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 9497 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 9498 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 9499 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 9500 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 9501 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 9502 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 9503 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 9504 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 9505 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 9506 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 9507 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 9508 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 9509 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 9510 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 9511 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 9512 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 9513 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP_DEFAULT 0x00000000 9514 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 9515 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 9516 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP_DEFAULT 0x00000000 9517 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 9518 9519 9520 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf20_bifcfgdecp 9521 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_VENDOR_ID_DEFAULT 0x00000000 9522 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_ID_DEFAULT 0x00000000 9523 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_COMMAND_DEFAULT 0x00000000 9524 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_STATUS_DEFAULT 0x00000000 9525 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_REVISION_ID_DEFAULT 0x00000000 9526 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PROG_INTERFACE_DEFAULT 0x00000000 9527 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_SUB_CLASS_DEFAULT 0x00000000 9528 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_CLASS_DEFAULT 0x00000000 9529 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_CACHE_LINE_DEFAULT 0x00000000 9530 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_LATENCY_DEFAULT 0x00000000 9531 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_HEADER_DEFAULT 0x00000000 9532 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_BIST_DEFAULT 0x00000000 9533 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_1_DEFAULT 0x00000000 9534 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_2_DEFAULT 0x00000000 9535 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_3_DEFAULT 0x00000000 9536 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_4_DEFAULT 0x00000000 9537 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_5_DEFAULT 0x00000000 9538 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_6_DEFAULT 0x00000000 9539 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 9540 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_ADAPTER_ID_DEFAULT 0x73101002 9541 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_ROM_BASE_ADDR_DEFAULT 0x00000000 9542 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_CAP_PTR_DEFAULT 0x00000048 9543 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_LINE_DEFAULT 0x00000000 9544 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_PIN_DEFAULT 0x00000000 9545 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MIN_GRANT_DEFAULT 0x00000000 9546 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MAX_LATENCY_DEFAULT 0x00000000 9547 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 9548 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP_DEFAULT 0x00000002 9549 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP_DEFAULT 0x00000000 9550 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL_DEFAULT 0x00000000 9551 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS_DEFAULT 0x00000000 9552 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP_DEFAULT 0x00000d04 9553 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL_DEFAULT 0x00000000 9554 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS_DEFAULT 0x00000000 9555 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2_DEFAULT 0x00010000 9556 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2_DEFAULT 0x00000000 9557 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS2_DEFAULT 0x00000000 9558 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2_DEFAULT 0x0000001e 9559 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2_DEFAULT 0x00000000 9560 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2_DEFAULT 0x00000000 9561 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_CAP_LIST_DEFAULT 0x0000c000 9562 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL_DEFAULT 0x00000082 9563 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 9564 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 9565 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA_DEFAULT 0x00000000 9566 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK_DEFAULT 0x00000000 9567 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 9568 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK_64_DEFAULT 0x00000000 9569 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING_DEFAULT 0x00000000 9570 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING_64_DEFAULT 0x00000000 9571 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSIX_CAP_LIST_DEFAULT 0x00000000 9572 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 9573 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSIX_TABLE_DEFAULT 0x00000000 9574 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSIX_PBA_DEFAULT 0x00000000 9575 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 9576 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 9577 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 9578 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 9579 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 9580 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 9581 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 9582 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 9583 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 9584 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 9585 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 9586 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 9587 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 9588 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 9589 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 9590 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 9591 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 9592 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 9593 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 9594 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 9595 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP_DEFAULT 0x00000000 9596 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 9597 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 9598 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP_DEFAULT 0x00000000 9599 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 9600 9601 9602 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf21_bifcfgdecp 9603 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_VENDOR_ID_DEFAULT 0x00000000 9604 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_ID_DEFAULT 0x00000000 9605 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_COMMAND_DEFAULT 0x00000000 9606 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_STATUS_DEFAULT 0x00000000 9607 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_REVISION_ID_DEFAULT 0x00000000 9608 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PROG_INTERFACE_DEFAULT 0x00000000 9609 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_SUB_CLASS_DEFAULT 0x00000000 9610 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_CLASS_DEFAULT 0x00000000 9611 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_CACHE_LINE_DEFAULT 0x00000000 9612 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_LATENCY_DEFAULT 0x00000000 9613 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_HEADER_DEFAULT 0x00000000 9614 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_BIST_DEFAULT 0x00000000 9615 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_1_DEFAULT 0x00000000 9616 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_2_DEFAULT 0x00000000 9617 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_3_DEFAULT 0x00000000 9618 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_4_DEFAULT 0x00000000 9619 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_5_DEFAULT 0x00000000 9620 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_6_DEFAULT 0x00000000 9621 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 9622 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_ADAPTER_ID_DEFAULT 0x73101002 9623 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_ROM_BASE_ADDR_DEFAULT 0x00000000 9624 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_CAP_PTR_DEFAULT 0x00000048 9625 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_LINE_DEFAULT 0x00000000 9626 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_PIN_DEFAULT 0x00000000 9627 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MIN_GRANT_DEFAULT 0x00000000 9628 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MAX_LATENCY_DEFAULT 0x00000000 9629 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 9630 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP_DEFAULT 0x00000002 9631 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP_DEFAULT 0x00000000 9632 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL_DEFAULT 0x00000000 9633 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS_DEFAULT 0x00000000 9634 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP_DEFAULT 0x00000d04 9635 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL_DEFAULT 0x00000000 9636 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS_DEFAULT 0x00000000 9637 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2_DEFAULT 0x00010000 9638 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2_DEFAULT 0x00000000 9639 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS2_DEFAULT 0x00000000 9640 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2_DEFAULT 0x0000001e 9641 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2_DEFAULT 0x00000000 9642 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2_DEFAULT 0x00000000 9643 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_CAP_LIST_DEFAULT 0x0000c000 9644 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL_DEFAULT 0x00000082 9645 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 9646 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 9647 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA_DEFAULT 0x00000000 9648 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK_DEFAULT 0x00000000 9649 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 9650 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK_64_DEFAULT 0x00000000 9651 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING_DEFAULT 0x00000000 9652 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING_64_DEFAULT 0x00000000 9653 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSIX_CAP_LIST_DEFAULT 0x00000000 9654 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 9655 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSIX_TABLE_DEFAULT 0x00000000 9656 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSIX_PBA_DEFAULT 0x00000000 9657 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 9658 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 9659 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 9660 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 9661 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 9662 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 9663 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 9664 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 9665 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 9666 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 9667 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 9668 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 9669 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 9670 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 9671 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 9672 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 9673 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 9674 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 9675 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 9676 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 9677 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP_DEFAULT 0x00000000 9678 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 9679 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 9680 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP_DEFAULT 0x00000000 9681 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 9682 9683 9684 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf22_bifcfgdecp 9685 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_VENDOR_ID_DEFAULT 0x00000000 9686 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_ID_DEFAULT 0x00000000 9687 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_COMMAND_DEFAULT 0x00000000 9688 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_STATUS_DEFAULT 0x00000000 9689 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_REVISION_ID_DEFAULT 0x00000000 9690 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PROG_INTERFACE_DEFAULT 0x00000000 9691 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_SUB_CLASS_DEFAULT 0x00000000 9692 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_CLASS_DEFAULT 0x00000000 9693 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_CACHE_LINE_DEFAULT 0x00000000 9694 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_LATENCY_DEFAULT 0x00000000 9695 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_HEADER_DEFAULT 0x00000000 9696 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_BIST_DEFAULT 0x00000000 9697 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_1_DEFAULT 0x00000000 9698 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_2_DEFAULT 0x00000000 9699 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_3_DEFAULT 0x00000000 9700 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_4_DEFAULT 0x00000000 9701 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_5_DEFAULT 0x00000000 9702 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_6_DEFAULT 0x00000000 9703 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 9704 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_ADAPTER_ID_DEFAULT 0x73101002 9705 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_ROM_BASE_ADDR_DEFAULT 0x00000000 9706 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_CAP_PTR_DEFAULT 0x00000048 9707 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_LINE_DEFAULT 0x00000000 9708 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_PIN_DEFAULT 0x00000000 9709 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MIN_GRANT_DEFAULT 0x00000000 9710 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MAX_LATENCY_DEFAULT 0x00000000 9711 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 9712 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP_DEFAULT 0x00000002 9713 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP_DEFAULT 0x00000000 9714 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL_DEFAULT 0x00000000 9715 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS_DEFAULT 0x00000000 9716 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP_DEFAULT 0x00000d04 9717 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL_DEFAULT 0x00000000 9718 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS_DEFAULT 0x00000000 9719 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2_DEFAULT 0x00010000 9720 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2_DEFAULT 0x00000000 9721 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS2_DEFAULT 0x00000000 9722 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2_DEFAULT 0x0000001e 9723 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2_DEFAULT 0x00000000 9724 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2_DEFAULT 0x00000000 9725 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_CAP_LIST_DEFAULT 0x0000c000 9726 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL_DEFAULT 0x00000082 9727 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 9728 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 9729 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA_DEFAULT 0x00000000 9730 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK_DEFAULT 0x00000000 9731 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 9732 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK_64_DEFAULT 0x00000000 9733 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING_DEFAULT 0x00000000 9734 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING_64_DEFAULT 0x00000000 9735 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSIX_CAP_LIST_DEFAULT 0x00000000 9736 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 9737 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSIX_TABLE_DEFAULT 0x00000000 9738 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSIX_PBA_DEFAULT 0x00000000 9739 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 9740 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 9741 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 9742 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 9743 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 9744 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 9745 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 9746 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 9747 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 9748 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 9749 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 9750 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 9751 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 9752 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 9753 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 9754 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 9755 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 9756 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 9757 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 9758 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 9759 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP_DEFAULT 0x00000000 9760 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 9761 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 9762 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP_DEFAULT 0x00000000 9763 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 9764 9765 9766 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf23_bifcfgdecp 9767 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_VENDOR_ID_DEFAULT 0x00000000 9768 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_ID_DEFAULT 0x00000000 9769 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_COMMAND_DEFAULT 0x00000000 9770 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_STATUS_DEFAULT 0x00000000 9771 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_REVISION_ID_DEFAULT 0x00000000 9772 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PROG_INTERFACE_DEFAULT 0x00000000 9773 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_SUB_CLASS_DEFAULT 0x00000000 9774 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_CLASS_DEFAULT 0x00000000 9775 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_CACHE_LINE_DEFAULT 0x00000000 9776 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_LATENCY_DEFAULT 0x00000000 9777 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_HEADER_DEFAULT 0x00000000 9778 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_BIST_DEFAULT 0x00000000 9779 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_1_DEFAULT 0x00000000 9780 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_2_DEFAULT 0x00000000 9781 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_3_DEFAULT 0x00000000 9782 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_4_DEFAULT 0x00000000 9783 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_5_DEFAULT 0x00000000 9784 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_6_DEFAULT 0x00000000 9785 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 9786 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_ADAPTER_ID_DEFAULT 0x73101002 9787 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_ROM_BASE_ADDR_DEFAULT 0x00000000 9788 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_CAP_PTR_DEFAULT 0x00000048 9789 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_LINE_DEFAULT 0x00000000 9790 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_PIN_DEFAULT 0x00000000 9791 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MIN_GRANT_DEFAULT 0x00000000 9792 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MAX_LATENCY_DEFAULT 0x00000000 9793 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 9794 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP_DEFAULT 0x00000002 9795 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP_DEFAULT 0x00000000 9796 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL_DEFAULT 0x00000000 9797 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS_DEFAULT 0x00000000 9798 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP_DEFAULT 0x00000d04 9799 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL_DEFAULT 0x00000000 9800 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS_DEFAULT 0x00000000 9801 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2_DEFAULT 0x00010000 9802 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2_DEFAULT 0x00000000 9803 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS2_DEFAULT 0x00000000 9804 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2_DEFAULT 0x0000001e 9805 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2_DEFAULT 0x00000000 9806 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2_DEFAULT 0x00000000 9807 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_CAP_LIST_DEFAULT 0x0000c000 9808 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL_DEFAULT 0x00000082 9809 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 9810 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 9811 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA_DEFAULT 0x00000000 9812 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK_DEFAULT 0x00000000 9813 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 9814 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK_64_DEFAULT 0x00000000 9815 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING_DEFAULT 0x00000000 9816 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING_64_DEFAULT 0x00000000 9817 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSIX_CAP_LIST_DEFAULT 0x00000000 9818 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 9819 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSIX_TABLE_DEFAULT 0x00000000 9820 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSIX_PBA_DEFAULT 0x00000000 9821 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 9822 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 9823 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 9824 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 9825 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 9826 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 9827 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 9828 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 9829 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 9830 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 9831 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 9832 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 9833 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 9834 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 9835 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 9836 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 9837 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 9838 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 9839 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 9840 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 9841 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP_DEFAULT 0x00000000 9842 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 9843 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 9844 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP_DEFAULT 0x00000000 9845 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 9846 9847 9848 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf24_bifcfgdecp 9849 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_VENDOR_ID_DEFAULT 0x00000000 9850 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_ID_DEFAULT 0x00000000 9851 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_COMMAND_DEFAULT 0x00000000 9852 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_STATUS_DEFAULT 0x00000000 9853 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_REVISION_ID_DEFAULT 0x00000000 9854 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PROG_INTERFACE_DEFAULT 0x00000000 9855 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_SUB_CLASS_DEFAULT 0x00000000 9856 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_CLASS_DEFAULT 0x00000000 9857 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_CACHE_LINE_DEFAULT 0x00000000 9858 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_LATENCY_DEFAULT 0x00000000 9859 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_HEADER_DEFAULT 0x00000000 9860 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_BIST_DEFAULT 0x00000000 9861 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_1_DEFAULT 0x00000000 9862 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_2_DEFAULT 0x00000000 9863 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_3_DEFAULT 0x00000000 9864 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_4_DEFAULT 0x00000000 9865 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_5_DEFAULT 0x00000000 9866 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_6_DEFAULT 0x00000000 9867 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 9868 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_ADAPTER_ID_DEFAULT 0x73101002 9869 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_ROM_BASE_ADDR_DEFAULT 0x00000000 9870 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_CAP_PTR_DEFAULT 0x00000048 9871 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_LINE_DEFAULT 0x00000000 9872 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_PIN_DEFAULT 0x00000000 9873 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MIN_GRANT_DEFAULT 0x00000000 9874 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MAX_LATENCY_DEFAULT 0x00000000 9875 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 9876 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP_DEFAULT 0x00000002 9877 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP_DEFAULT 0x00000000 9878 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL_DEFAULT 0x00000000 9879 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS_DEFAULT 0x00000000 9880 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP_DEFAULT 0x00000d04 9881 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL_DEFAULT 0x00000000 9882 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS_DEFAULT 0x00000000 9883 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2_DEFAULT 0x00010000 9884 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2_DEFAULT 0x00000000 9885 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS2_DEFAULT 0x00000000 9886 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2_DEFAULT 0x0000001e 9887 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2_DEFAULT 0x00000000 9888 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2_DEFAULT 0x00000000 9889 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_CAP_LIST_DEFAULT 0x0000c000 9890 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL_DEFAULT 0x00000082 9891 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 9892 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 9893 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA_DEFAULT 0x00000000 9894 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK_DEFAULT 0x00000000 9895 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 9896 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK_64_DEFAULT 0x00000000 9897 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING_DEFAULT 0x00000000 9898 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING_64_DEFAULT 0x00000000 9899 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSIX_CAP_LIST_DEFAULT 0x00000000 9900 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 9901 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSIX_TABLE_DEFAULT 0x00000000 9902 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSIX_PBA_DEFAULT 0x00000000 9903 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 9904 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 9905 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 9906 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 9907 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 9908 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 9909 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 9910 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 9911 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 9912 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 9913 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 9914 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 9915 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 9916 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 9917 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 9918 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 9919 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 9920 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 9921 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 9922 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 9923 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP_DEFAULT 0x00000000 9924 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 9925 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 9926 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP_DEFAULT 0x00000000 9927 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 9928 9929 9930 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf25_bifcfgdecp 9931 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_VENDOR_ID_DEFAULT 0x00000000 9932 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_ID_DEFAULT 0x00000000 9933 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_COMMAND_DEFAULT 0x00000000 9934 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_STATUS_DEFAULT 0x00000000 9935 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_REVISION_ID_DEFAULT 0x00000000 9936 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PROG_INTERFACE_DEFAULT 0x00000000 9937 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_SUB_CLASS_DEFAULT 0x00000000 9938 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_CLASS_DEFAULT 0x00000000 9939 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_CACHE_LINE_DEFAULT 0x00000000 9940 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_LATENCY_DEFAULT 0x00000000 9941 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_HEADER_DEFAULT 0x00000000 9942 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_BIST_DEFAULT 0x00000000 9943 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_1_DEFAULT 0x00000000 9944 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_2_DEFAULT 0x00000000 9945 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_3_DEFAULT 0x00000000 9946 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_4_DEFAULT 0x00000000 9947 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_5_DEFAULT 0x00000000 9948 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_6_DEFAULT 0x00000000 9949 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 9950 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_ADAPTER_ID_DEFAULT 0x73101002 9951 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_ROM_BASE_ADDR_DEFAULT 0x00000000 9952 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_CAP_PTR_DEFAULT 0x00000048 9953 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_LINE_DEFAULT 0x00000000 9954 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_PIN_DEFAULT 0x00000000 9955 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MIN_GRANT_DEFAULT 0x00000000 9956 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MAX_LATENCY_DEFAULT 0x00000000 9957 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 9958 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP_DEFAULT 0x00000002 9959 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP_DEFAULT 0x00000000 9960 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL_DEFAULT 0x00000000 9961 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS_DEFAULT 0x00000000 9962 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP_DEFAULT 0x00000d04 9963 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL_DEFAULT 0x00000000 9964 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS_DEFAULT 0x00000000 9965 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2_DEFAULT 0x00010000 9966 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2_DEFAULT 0x00000000 9967 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS2_DEFAULT 0x00000000 9968 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2_DEFAULT 0x0000001e 9969 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2_DEFAULT 0x00000000 9970 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2_DEFAULT 0x00000000 9971 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_CAP_LIST_DEFAULT 0x0000c000 9972 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL_DEFAULT 0x00000082 9973 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 9974 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 9975 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA_DEFAULT 0x00000000 9976 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK_DEFAULT 0x00000000 9977 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 9978 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK_64_DEFAULT 0x00000000 9979 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING_DEFAULT 0x00000000 9980 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING_64_DEFAULT 0x00000000 9981 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSIX_CAP_LIST_DEFAULT 0x00000000 9982 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 9983 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSIX_TABLE_DEFAULT 0x00000000 9984 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSIX_PBA_DEFAULT 0x00000000 9985 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 9986 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 9987 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 9988 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 9989 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 9990 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 9991 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 9992 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 9993 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 9994 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 9995 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 9996 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 9997 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 9998 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 9999 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 10000 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 10001 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 10002 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 10003 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 10004 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 10005 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP_DEFAULT 0x00000000 10006 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 10007 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 10008 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP_DEFAULT 0x00000000 10009 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 10010 10011 10012 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf26_bifcfgdecp 10013 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_VENDOR_ID_DEFAULT 0x00000000 10014 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_ID_DEFAULT 0x00000000 10015 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_COMMAND_DEFAULT 0x00000000 10016 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_STATUS_DEFAULT 0x00000000 10017 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_REVISION_ID_DEFAULT 0x00000000 10018 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PROG_INTERFACE_DEFAULT 0x00000000 10019 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_SUB_CLASS_DEFAULT 0x00000000 10020 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_CLASS_DEFAULT 0x00000000 10021 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_CACHE_LINE_DEFAULT 0x00000000 10022 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_LATENCY_DEFAULT 0x00000000 10023 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_HEADER_DEFAULT 0x00000000 10024 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_BIST_DEFAULT 0x00000000 10025 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_1_DEFAULT 0x00000000 10026 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_2_DEFAULT 0x00000000 10027 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_3_DEFAULT 0x00000000 10028 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_4_DEFAULT 0x00000000 10029 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_5_DEFAULT 0x00000000 10030 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_6_DEFAULT 0x00000000 10031 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 10032 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_ADAPTER_ID_DEFAULT 0x73101002 10033 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_ROM_BASE_ADDR_DEFAULT 0x00000000 10034 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_CAP_PTR_DEFAULT 0x00000048 10035 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_LINE_DEFAULT 0x00000000 10036 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_PIN_DEFAULT 0x00000000 10037 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MIN_GRANT_DEFAULT 0x00000000 10038 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MAX_LATENCY_DEFAULT 0x00000000 10039 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 10040 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP_DEFAULT 0x00000002 10041 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP_DEFAULT 0x00000000 10042 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL_DEFAULT 0x00000000 10043 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS_DEFAULT 0x00000000 10044 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP_DEFAULT 0x00000d04 10045 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL_DEFAULT 0x00000000 10046 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS_DEFAULT 0x00000000 10047 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2_DEFAULT 0x00010000 10048 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2_DEFAULT 0x00000000 10049 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS2_DEFAULT 0x00000000 10050 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2_DEFAULT 0x0000001e 10051 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2_DEFAULT 0x00000000 10052 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2_DEFAULT 0x00000000 10053 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_CAP_LIST_DEFAULT 0x0000c000 10054 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL_DEFAULT 0x00000082 10055 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 10056 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 10057 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA_DEFAULT 0x00000000 10058 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK_DEFAULT 0x00000000 10059 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 10060 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK_64_DEFAULT 0x00000000 10061 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING_DEFAULT 0x00000000 10062 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING_64_DEFAULT 0x00000000 10063 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSIX_CAP_LIST_DEFAULT 0x00000000 10064 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 10065 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSIX_TABLE_DEFAULT 0x00000000 10066 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSIX_PBA_DEFAULT 0x00000000 10067 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 10068 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 10069 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 10070 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 10071 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 10072 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 10073 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 10074 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 10075 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 10076 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 10077 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 10078 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 10079 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 10080 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 10081 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 10082 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 10083 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 10084 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 10085 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 10086 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 10087 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP_DEFAULT 0x00000000 10088 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 10089 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 10090 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP_DEFAULT 0x00000000 10091 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 10092 10093 10094 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf27_bifcfgdecp 10095 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_VENDOR_ID_DEFAULT 0x00000000 10096 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_ID_DEFAULT 0x00000000 10097 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_COMMAND_DEFAULT 0x00000000 10098 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_STATUS_DEFAULT 0x00000000 10099 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_REVISION_ID_DEFAULT 0x00000000 10100 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PROG_INTERFACE_DEFAULT 0x00000000 10101 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_SUB_CLASS_DEFAULT 0x00000000 10102 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_CLASS_DEFAULT 0x00000000 10103 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_CACHE_LINE_DEFAULT 0x00000000 10104 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_LATENCY_DEFAULT 0x00000000 10105 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_HEADER_DEFAULT 0x00000000 10106 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_BIST_DEFAULT 0x00000000 10107 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_1_DEFAULT 0x00000000 10108 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_2_DEFAULT 0x00000000 10109 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_3_DEFAULT 0x00000000 10110 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_4_DEFAULT 0x00000000 10111 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_5_DEFAULT 0x00000000 10112 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_6_DEFAULT 0x00000000 10113 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 10114 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_ADAPTER_ID_DEFAULT 0x73101002 10115 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_ROM_BASE_ADDR_DEFAULT 0x00000000 10116 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_CAP_PTR_DEFAULT 0x00000048 10117 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_LINE_DEFAULT 0x00000000 10118 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_PIN_DEFAULT 0x00000000 10119 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MIN_GRANT_DEFAULT 0x00000000 10120 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MAX_LATENCY_DEFAULT 0x00000000 10121 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 10122 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP_DEFAULT 0x00000002 10123 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP_DEFAULT 0x00000000 10124 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL_DEFAULT 0x00000000 10125 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS_DEFAULT 0x00000000 10126 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP_DEFAULT 0x00000d04 10127 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL_DEFAULT 0x00000000 10128 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS_DEFAULT 0x00000000 10129 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2_DEFAULT 0x00010000 10130 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2_DEFAULT 0x00000000 10131 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS2_DEFAULT 0x00000000 10132 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2_DEFAULT 0x0000001e 10133 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2_DEFAULT 0x00000000 10134 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2_DEFAULT 0x00000000 10135 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_CAP_LIST_DEFAULT 0x0000c000 10136 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL_DEFAULT 0x00000082 10137 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 10138 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 10139 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA_DEFAULT 0x00000000 10140 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK_DEFAULT 0x00000000 10141 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 10142 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK_64_DEFAULT 0x00000000 10143 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING_DEFAULT 0x00000000 10144 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING_64_DEFAULT 0x00000000 10145 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSIX_CAP_LIST_DEFAULT 0x00000000 10146 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 10147 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSIX_TABLE_DEFAULT 0x00000000 10148 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSIX_PBA_DEFAULT 0x00000000 10149 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 10150 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 10151 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 10152 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 10153 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 10154 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 10155 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 10156 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 10157 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 10158 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 10159 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 10160 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 10161 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 10162 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 10163 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 10164 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 10165 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 10166 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 10167 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 10168 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 10169 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP_DEFAULT 0x00000000 10170 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 10171 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 10172 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP_DEFAULT 0x00000000 10173 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 10174 10175 10176 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf28_bifcfgdecp 10177 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_VENDOR_ID_DEFAULT 0x00000000 10178 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_ID_DEFAULT 0x00000000 10179 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_COMMAND_DEFAULT 0x00000000 10180 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_STATUS_DEFAULT 0x00000000 10181 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_REVISION_ID_DEFAULT 0x00000000 10182 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PROG_INTERFACE_DEFAULT 0x00000000 10183 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_SUB_CLASS_DEFAULT 0x00000000 10184 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_CLASS_DEFAULT 0x00000000 10185 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_CACHE_LINE_DEFAULT 0x00000000 10186 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_LATENCY_DEFAULT 0x00000000 10187 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_HEADER_DEFAULT 0x00000000 10188 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_BIST_DEFAULT 0x00000000 10189 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_1_DEFAULT 0x00000000 10190 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_2_DEFAULT 0x00000000 10191 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_3_DEFAULT 0x00000000 10192 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_4_DEFAULT 0x00000000 10193 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_5_DEFAULT 0x00000000 10194 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_6_DEFAULT 0x00000000 10195 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 10196 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_ADAPTER_ID_DEFAULT 0x73101002 10197 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_ROM_BASE_ADDR_DEFAULT 0x00000000 10198 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_CAP_PTR_DEFAULT 0x00000048 10199 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_LINE_DEFAULT 0x00000000 10200 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_PIN_DEFAULT 0x00000000 10201 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MIN_GRANT_DEFAULT 0x00000000 10202 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MAX_LATENCY_DEFAULT 0x00000000 10203 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 10204 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP_DEFAULT 0x00000002 10205 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP_DEFAULT 0x00000000 10206 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL_DEFAULT 0x00000000 10207 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS_DEFAULT 0x00000000 10208 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP_DEFAULT 0x00000d04 10209 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL_DEFAULT 0x00000000 10210 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS_DEFAULT 0x00000000 10211 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2_DEFAULT 0x00010000 10212 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2_DEFAULT 0x00000000 10213 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS2_DEFAULT 0x00000000 10214 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2_DEFAULT 0x0000001e 10215 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2_DEFAULT 0x00000000 10216 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2_DEFAULT 0x00000000 10217 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_CAP_LIST_DEFAULT 0x0000c000 10218 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL_DEFAULT 0x00000082 10219 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 10220 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 10221 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA_DEFAULT 0x00000000 10222 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK_DEFAULT 0x00000000 10223 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 10224 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK_64_DEFAULT 0x00000000 10225 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING_DEFAULT 0x00000000 10226 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING_64_DEFAULT 0x00000000 10227 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSIX_CAP_LIST_DEFAULT 0x00000000 10228 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 10229 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSIX_TABLE_DEFAULT 0x00000000 10230 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSIX_PBA_DEFAULT 0x00000000 10231 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 10232 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 10233 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 10234 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 10235 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 10236 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 10237 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 10238 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 10239 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 10240 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 10241 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 10242 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 10243 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 10244 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 10245 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 10246 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 10247 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 10248 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 10249 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 10250 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 10251 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP_DEFAULT 0x00000000 10252 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 10253 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 10254 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP_DEFAULT 0x00000000 10255 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 10256 10257 10258 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf29_bifcfgdecp 10259 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_VENDOR_ID_DEFAULT 0x00000000 10260 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_ID_DEFAULT 0x00000000 10261 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_COMMAND_DEFAULT 0x00000000 10262 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_STATUS_DEFAULT 0x00000000 10263 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_REVISION_ID_DEFAULT 0x00000000 10264 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PROG_INTERFACE_DEFAULT 0x00000000 10265 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_SUB_CLASS_DEFAULT 0x00000000 10266 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_CLASS_DEFAULT 0x00000000 10267 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_CACHE_LINE_DEFAULT 0x00000000 10268 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_LATENCY_DEFAULT 0x00000000 10269 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_HEADER_DEFAULT 0x00000000 10270 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_BIST_DEFAULT 0x00000000 10271 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_1_DEFAULT 0x00000000 10272 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_2_DEFAULT 0x00000000 10273 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_3_DEFAULT 0x00000000 10274 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_4_DEFAULT 0x00000000 10275 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_5_DEFAULT 0x00000000 10276 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_6_DEFAULT 0x00000000 10277 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 10278 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_ADAPTER_ID_DEFAULT 0x73101002 10279 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_ROM_BASE_ADDR_DEFAULT 0x00000000 10280 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_CAP_PTR_DEFAULT 0x00000048 10281 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_LINE_DEFAULT 0x00000000 10282 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_PIN_DEFAULT 0x00000000 10283 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MIN_GRANT_DEFAULT 0x00000000 10284 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MAX_LATENCY_DEFAULT 0x00000000 10285 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 10286 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP_DEFAULT 0x00000002 10287 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP_DEFAULT 0x00000000 10288 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL_DEFAULT 0x00000000 10289 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS_DEFAULT 0x00000000 10290 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP_DEFAULT 0x00000d04 10291 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL_DEFAULT 0x00000000 10292 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS_DEFAULT 0x00000000 10293 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2_DEFAULT 0x00010000 10294 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2_DEFAULT 0x00000000 10295 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS2_DEFAULT 0x00000000 10296 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2_DEFAULT 0x0000001e 10297 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2_DEFAULT 0x00000000 10298 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2_DEFAULT 0x00000000 10299 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_CAP_LIST_DEFAULT 0x0000c000 10300 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL_DEFAULT 0x00000082 10301 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 10302 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 10303 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA_DEFAULT 0x00000000 10304 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK_DEFAULT 0x00000000 10305 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 10306 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK_64_DEFAULT 0x00000000 10307 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING_DEFAULT 0x00000000 10308 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING_64_DEFAULT 0x00000000 10309 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSIX_CAP_LIST_DEFAULT 0x00000000 10310 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 10311 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSIX_TABLE_DEFAULT 0x00000000 10312 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSIX_PBA_DEFAULT 0x00000000 10313 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 10314 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 10315 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 10316 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 10317 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 10318 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 10319 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 10320 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 10321 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 10322 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 10323 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 10324 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 10325 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 10326 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 10327 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 10328 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 10329 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 10330 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 10331 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 10332 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 10333 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP_DEFAULT 0x00000000 10334 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 10335 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 10336 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP_DEFAULT 0x00000000 10337 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 10338 10339 10340 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf30_bifcfgdecp 10341 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_VENDOR_ID_DEFAULT 0x00000000 10342 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_ID_DEFAULT 0x00000000 10343 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_COMMAND_DEFAULT 0x00000000 10344 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_STATUS_DEFAULT 0x00000000 10345 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_REVISION_ID_DEFAULT 0x00000000 10346 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PROG_INTERFACE_DEFAULT 0x00000000 10347 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_SUB_CLASS_DEFAULT 0x00000000 10348 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_CLASS_DEFAULT 0x00000000 10349 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_CACHE_LINE_DEFAULT 0x00000000 10350 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_LATENCY_DEFAULT 0x00000000 10351 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_HEADER_DEFAULT 0x00000000 10352 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_BIST_DEFAULT 0x00000000 10353 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_1_DEFAULT 0x00000000 10354 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_2_DEFAULT 0x00000000 10355 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_3_DEFAULT 0x00000000 10356 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_4_DEFAULT 0x00000000 10357 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_5_DEFAULT 0x00000000 10358 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_6_DEFAULT 0x00000000 10359 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_CARDBUS_CIS_PTR_DEFAULT 0x00000000 10360 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_ADAPTER_ID_DEFAULT 0x73101002 10361 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_ROM_BASE_ADDR_DEFAULT 0x00000000 10362 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_CAP_PTR_DEFAULT 0x00000048 10363 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_LINE_DEFAULT 0x00000000 10364 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_PIN_DEFAULT 0x00000000 10365 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MIN_GRANT_DEFAULT 0x00000000 10366 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MAX_LATENCY_DEFAULT 0x00000000 10367 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 10368 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP_DEFAULT 0x00000002 10369 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP_DEFAULT 0x00000000 10370 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL_DEFAULT 0x00000000 10371 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS_DEFAULT 0x00000000 10372 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP_DEFAULT 0x00000d04 10373 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL_DEFAULT 0x00000000 10374 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS_DEFAULT 0x00000000 10375 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2_DEFAULT 0x00010000 10376 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2_DEFAULT 0x00000000 10377 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS2_DEFAULT 0x00000000 10378 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2_DEFAULT 0x0000001e 10379 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2_DEFAULT 0x00000000 10380 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2_DEFAULT 0x00000000 10381 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_CAP_LIST_DEFAULT 0x0000c000 10382 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL_DEFAULT 0x00000082 10383 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 10384 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 10385 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA_DEFAULT 0x00000000 10386 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK_DEFAULT 0x00000000 10387 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 10388 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK_64_DEFAULT 0x00000000 10389 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING_DEFAULT 0x00000000 10390 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING_64_DEFAULT 0x00000000 10391 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSIX_CAP_LIST_DEFAULT 0x00000000 10392 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 10393 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSIX_TABLE_DEFAULT 0x00000000 10394 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSIX_PBA_DEFAULT 0x00000000 10395 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 10396 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 10397 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 10398 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 10399 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 10400 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 10401 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 10402 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 10403 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 10404 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 10405 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 10406 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 10407 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 10408 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 10409 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 10410 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 10411 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 10412 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 10413 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 10414 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 10415 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP_DEFAULT 0x00000000 10416 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 10417 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 10418 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP_DEFAULT 0x00000000 10419 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 10420 10421 10422 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC 10423 #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_DEFAULT 0x00000000 10424 #define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA_DEFAULT 0x00000000 10425 #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_DEFAULT 0x00000000 10426 10427 10428 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 10429 #define mmRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_DEFAULT 0x00000000 10430 #define mmRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 10431 #define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 10432 #define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 10433 #define mmRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 10434 10435 10436 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 10437 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_DEFAULT 0x00000000 10438 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 10439 #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 10440 #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 10441 #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 10442 #define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 10443 #define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 10444 #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 10445 #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 10446 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_DEFAULT 0x00000000 10447 #define mmBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 10448 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 10449 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 10450 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 10451 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 10452 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 10453 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 10454 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 10455 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 10456 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_DEFAULT 0x00000000 10457 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_DEFAULT 0x00000000 10458 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 10459 10460 10461 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 10462 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 10463 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 10464 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 10465 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 10466 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 10467 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 10468 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 10469 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 10470 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 10471 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 10472 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 10473 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 10474 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 10475 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 10476 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 10477 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 10478 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_DEFAULT 0x00000000 10479 10480 10481 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC 10482 #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_DEFAULT 0x00000000 10483 #define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA_DEFAULT 0x00000000 10484 #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_DEFAULT 0x00000000 10485 10486 10487 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 10488 #define mmRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_DEFAULT 0x00000000 10489 #define mmRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 10490 #define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 10491 #define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 10492 #define mmRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 10493 10494 10495 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 10496 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_DEFAULT 0x00000000 10497 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 10498 #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 10499 #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 10500 #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 10501 #define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 10502 #define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 10503 #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 10504 #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 10505 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_DEFAULT 0x00000000 10506 #define mmBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 10507 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 10508 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 10509 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 10510 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 10511 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 10512 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 10513 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 10514 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 10515 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_DEFAULT 0x00000000 10516 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_DEFAULT 0x00000000 10517 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 10518 10519 10520 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 10521 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 10522 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 10523 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 10524 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 10525 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 10526 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 10527 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 10528 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 10529 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 10530 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 10531 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 10532 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 10533 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 10534 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 10535 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 10536 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 10537 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_DEFAULT 0x00000000 10538 10539 10540 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC 10541 #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_DEFAULT 0x00000000 10542 #define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA_DEFAULT 0x00000000 10543 #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_DEFAULT 0x00000000 10544 10545 10546 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 10547 #define mmRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_DEFAULT 0x00000000 10548 #define mmRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 10549 #define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 10550 #define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 10551 #define mmRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 10552 10553 10554 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 10555 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_DEFAULT 0x00000000 10556 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 10557 #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 10558 #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 10559 #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 10560 #define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 10561 #define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 10562 #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 10563 #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 10564 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_DEFAULT 0x00000000 10565 #define mmBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 10566 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 10567 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 10568 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 10569 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 10570 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 10571 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 10572 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 10573 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 10574 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_DEFAULT 0x00000000 10575 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_DEFAULT 0x00000000 10576 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 10577 10578 10579 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 10580 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 10581 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 10582 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 10583 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 10584 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 10585 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 10586 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 10587 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 10588 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 10589 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 10590 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 10591 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 10592 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 10593 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 10594 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 10595 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 10596 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_DEFAULT 0x00000000 10597 10598 10599 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC 10600 #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_DEFAULT 0x00000000 10601 #define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA_DEFAULT 0x00000000 10602 #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_DEFAULT 0x00000000 10603 10604 10605 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 10606 #define mmRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_DEFAULT 0x00000000 10607 #define mmRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 10608 #define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 10609 #define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 10610 #define mmRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 10611 10612 10613 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 10614 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_DEFAULT 0x00000000 10615 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 10616 #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 10617 #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 10618 #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 10619 #define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 10620 #define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 10621 #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 10622 #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 10623 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_DEFAULT 0x00000000 10624 #define mmBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 10625 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 10626 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 10627 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 10628 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 10629 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 10630 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 10631 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 10632 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 10633 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_DEFAULT 0x00000000 10634 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_DEFAULT 0x00000000 10635 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 10636 10637 10638 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 10639 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 10640 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 10641 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 10642 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 10643 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 10644 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 10645 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 10646 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 10647 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 10648 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 10649 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 10650 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 10651 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 10652 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 10653 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 10654 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 10655 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_DEFAULT 0x00000000 10656 10657 10658 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC 10659 #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_DEFAULT 0x00000000 10660 #define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA_DEFAULT 0x00000000 10661 #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_DEFAULT 0x00000000 10662 10663 10664 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 10665 #define mmRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_DEFAULT 0x00000000 10666 #define mmRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 10667 #define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 10668 #define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 10669 #define mmRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 10670 10671 10672 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 10673 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_DEFAULT 0x00000000 10674 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 10675 #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 10676 #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 10677 #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 10678 #define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 10679 #define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 10680 #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 10681 #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 10682 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_DEFAULT 0x00000000 10683 #define mmBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 10684 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 10685 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 10686 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 10687 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 10688 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 10689 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 10690 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 10691 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 10692 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_DEFAULT 0x00000000 10693 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_DEFAULT 0x00000000 10694 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 10695 10696 10697 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 10698 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 10699 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 10700 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 10701 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 10702 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 10703 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 10704 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 10705 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 10706 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 10707 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 10708 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 10709 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 10710 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 10711 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 10712 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 10713 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 10714 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_DEFAULT 0x00000000 10715 10716 10717 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC 10718 #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_DEFAULT 0x00000000 10719 #define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA_DEFAULT 0x00000000 10720 #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_DEFAULT 0x00000000 10721 10722 10723 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 10724 #define mmRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_DEFAULT 0x00000000 10725 #define mmRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 10726 #define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 10727 #define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 10728 #define mmRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 10729 10730 10731 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 10732 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_DEFAULT 0x00000000 10733 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 10734 #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 10735 #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 10736 #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 10737 #define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 10738 #define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 10739 #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 10740 #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 10741 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_DEFAULT 0x00000000 10742 #define mmBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 10743 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 10744 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 10745 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 10746 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 10747 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 10748 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 10749 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 10750 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 10751 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_DEFAULT 0x00000000 10752 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_DEFAULT 0x00000000 10753 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 10754 10755 10756 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 10757 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 10758 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 10759 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 10760 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 10761 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 10762 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 10763 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 10764 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 10765 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 10766 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 10767 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 10768 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 10769 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 10770 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 10771 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 10772 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 10773 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_DEFAULT 0x00000000 10774 10775 10776 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC 10777 #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_DEFAULT 0x00000000 10778 #define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA_DEFAULT 0x00000000 10779 #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_DEFAULT 0x00000000 10780 10781 10782 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 10783 #define mmRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_DEFAULT 0x00000000 10784 #define mmRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 10785 #define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 10786 #define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 10787 #define mmRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 10788 10789 10790 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 10791 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_DEFAULT 0x00000000 10792 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 10793 #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 10794 #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 10795 #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 10796 #define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 10797 #define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 10798 #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 10799 #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 10800 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_DEFAULT 0x00000000 10801 #define mmBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 10802 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 10803 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 10804 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 10805 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 10806 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 10807 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 10808 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 10809 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 10810 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_DEFAULT 0x00000000 10811 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_DEFAULT 0x00000000 10812 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 10813 10814 10815 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 10816 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 10817 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 10818 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 10819 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 10820 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 10821 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 10822 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 10823 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 10824 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 10825 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 10826 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 10827 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 10828 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 10829 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 10830 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 10831 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 10832 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_DEFAULT 0x00000000 10833 10834 10835 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC 10836 #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_DEFAULT 0x00000000 10837 #define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA_DEFAULT 0x00000000 10838 #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_DEFAULT 0x00000000 10839 10840 10841 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 10842 #define mmRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_DEFAULT 0x00000000 10843 #define mmRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 10844 #define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 10845 #define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 10846 #define mmRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 10847 10848 10849 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 10850 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_DEFAULT 0x00000000 10851 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 10852 #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 10853 #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 10854 #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 10855 #define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 10856 #define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 10857 #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 10858 #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 10859 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_DEFAULT 0x00000000 10860 #define mmBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 10861 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 10862 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 10863 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 10864 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 10865 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 10866 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 10867 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 10868 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 10869 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_DEFAULT 0x00000000 10870 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_DEFAULT 0x00000000 10871 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 10872 10873 10874 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 10875 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 10876 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 10877 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 10878 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 10879 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 10880 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 10881 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 10882 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 10883 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 10884 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 10885 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 10886 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 10887 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 10888 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 10889 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 10890 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 10891 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_DEFAULT 0x00000000 10892 10893 10894 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_SYSPFVFDEC 10895 #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_DEFAULT 0x00000000 10896 #define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA_DEFAULT 0x00000000 10897 #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI_DEFAULT 0x00000000 10898 10899 10900 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFPFVFDEC1 10901 #define mmRCC_DEV0_EPF0_VF8_RCC_ERR_LOG_DEFAULT 0x00000000 10902 #define mmRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 10903 #define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 10904 #define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 10905 #define mmRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 10906 10907 10908 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1 10909 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS_DEFAULT 0x00000000 10910 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 10911 #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 10912 #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 10913 #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 10914 #define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 10915 #define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 10916 #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 10917 #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 10918 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING_DEFAULT 0x00000000 10919 #define mmBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 10920 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 10921 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 10922 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 10923 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 10924 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 10925 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 10926 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 10927 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 10928 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL_DEFAULT 0x00000000 10929 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL_DEFAULT 0x00000000 10930 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 10931 10932 10933 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFDEC2 10934 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 10935 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 10936 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 10937 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 10938 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 10939 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 10940 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 10941 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 10942 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 10943 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 10944 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 10945 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 10946 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 10947 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 10948 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 10949 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 10950 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_PBA_DEFAULT 0x00000000 10951 10952 10953 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_SYSPFVFDEC 10954 #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_DEFAULT 0x00000000 10955 #define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA_DEFAULT 0x00000000 10956 #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI_DEFAULT 0x00000000 10957 10958 10959 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFPFVFDEC1 10960 #define mmRCC_DEV0_EPF0_VF9_RCC_ERR_LOG_DEFAULT 0x00000000 10961 #define mmRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 10962 #define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 10963 #define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 10964 #define mmRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 10965 10966 10967 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1 10968 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS_DEFAULT 0x00000000 10969 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 10970 #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 10971 #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 10972 #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 10973 #define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 10974 #define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 10975 #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 10976 #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 10977 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING_DEFAULT 0x00000000 10978 #define mmBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 10979 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 10980 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 10981 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 10982 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 10983 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 10984 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 10985 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 10986 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 10987 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL_DEFAULT 0x00000000 10988 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL_DEFAULT 0x00000000 10989 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 10990 10991 10992 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFDEC2 10993 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 10994 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 10995 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 10996 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 10997 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 10998 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 10999 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 11000 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 11001 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 11002 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 11003 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 11004 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 11005 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 11006 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 11007 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 11008 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 11009 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_PBA_DEFAULT 0x00000000 11010 11011 11012 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_SYSPFVFDEC 11013 #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_DEFAULT 0x00000000 11014 #define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA_DEFAULT 0x00000000 11015 #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI_DEFAULT 0x00000000 11016 11017 11018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFPFVFDEC1 11019 #define mmRCC_DEV0_EPF0_VF10_RCC_ERR_LOG_DEFAULT 0x00000000 11020 #define mmRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 11021 #define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 11022 #define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 11023 #define mmRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 11024 11025 11026 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1 11027 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS_DEFAULT 0x00000000 11028 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 11029 #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 11030 #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 11031 #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 11032 #define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11033 #define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11034 #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 11035 #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 11036 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING_DEFAULT 0x00000000 11037 #define mmBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 11038 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 11039 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 11040 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 11041 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 11042 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 11043 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 11044 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 11045 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 11046 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL_DEFAULT 0x00000000 11047 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL_DEFAULT 0x00000000 11048 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 11049 11050 11051 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFDEC2 11052 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 11053 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 11054 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 11055 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 11056 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 11057 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 11058 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 11059 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 11060 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 11061 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 11062 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 11063 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 11064 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 11065 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 11066 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 11067 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 11068 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_PBA_DEFAULT 0x00000000 11069 11070 11071 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_SYSPFVFDEC 11072 #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_DEFAULT 0x00000000 11073 #define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA_DEFAULT 0x00000000 11074 #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI_DEFAULT 0x00000000 11075 11076 11077 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFPFVFDEC1 11078 #define mmRCC_DEV0_EPF0_VF11_RCC_ERR_LOG_DEFAULT 0x00000000 11079 #define mmRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 11080 #define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 11081 #define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 11082 #define mmRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 11083 11084 11085 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1 11086 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS_DEFAULT 0x00000000 11087 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 11088 #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 11089 #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 11090 #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 11091 #define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11092 #define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11093 #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 11094 #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 11095 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING_DEFAULT 0x00000000 11096 #define mmBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 11097 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 11098 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 11099 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 11100 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 11101 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 11102 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 11103 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 11104 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 11105 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL_DEFAULT 0x00000000 11106 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL_DEFAULT 0x00000000 11107 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 11108 11109 11110 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFDEC2 11111 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 11112 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 11113 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 11114 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 11115 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 11116 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 11117 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 11118 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 11119 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 11120 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 11121 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 11122 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 11123 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 11124 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 11125 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 11126 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 11127 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_PBA_DEFAULT 0x00000000 11128 11129 11130 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_SYSPFVFDEC 11131 #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_DEFAULT 0x00000000 11132 #define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA_DEFAULT 0x00000000 11133 #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI_DEFAULT 0x00000000 11134 11135 11136 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFPFVFDEC1 11137 #define mmRCC_DEV0_EPF0_VF12_RCC_ERR_LOG_DEFAULT 0x00000000 11138 #define mmRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 11139 #define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 11140 #define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 11141 #define mmRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 11142 11143 11144 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1 11145 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS_DEFAULT 0x00000000 11146 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 11147 #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 11148 #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 11149 #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 11150 #define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11151 #define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11152 #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 11153 #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 11154 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING_DEFAULT 0x00000000 11155 #define mmBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 11156 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 11157 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 11158 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 11159 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 11160 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 11161 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 11162 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 11163 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 11164 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL_DEFAULT 0x00000000 11165 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL_DEFAULT 0x00000000 11166 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 11167 11168 11169 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFDEC2 11170 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 11171 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 11172 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 11173 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 11174 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 11175 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 11176 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 11177 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 11178 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 11179 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 11180 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 11181 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 11182 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 11183 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 11184 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 11185 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 11186 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_PBA_DEFAULT 0x00000000 11187 11188 11189 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_SYSPFVFDEC 11190 #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_DEFAULT 0x00000000 11191 #define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA_DEFAULT 0x00000000 11192 #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI_DEFAULT 0x00000000 11193 11194 11195 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFPFVFDEC1 11196 #define mmRCC_DEV0_EPF0_VF13_RCC_ERR_LOG_DEFAULT 0x00000000 11197 #define mmRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 11198 #define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 11199 #define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 11200 #define mmRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 11201 11202 11203 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1 11204 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS_DEFAULT 0x00000000 11205 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 11206 #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 11207 #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 11208 #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 11209 #define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11210 #define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11211 #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 11212 #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 11213 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING_DEFAULT 0x00000000 11214 #define mmBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 11215 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 11216 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 11217 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 11218 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 11219 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 11220 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 11221 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 11222 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 11223 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL_DEFAULT 0x00000000 11224 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL_DEFAULT 0x00000000 11225 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 11226 11227 11228 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFDEC2 11229 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 11230 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 11231 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 11232 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 11233 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 11234 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 11235 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 11236 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 11237 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 11238 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 11239 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 11240 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 11241 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 11242 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 11243 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 11244 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 11245 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_PBA_DEFAULT 0x00000000 11246 11247 11248 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_SYSPFVFDEC 11249 #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_DEFAULT 0x00000000 11250 #define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA_DEFAULT 0x00000000 11251 #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI_DEFAULT 0x00000000 11252 11253 11254 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFPFVFDEC1 11255 #define mmRCC_DEV0_EPF0_VF14_RCC_ERR_LOG_DEFAULT 0x00000000 11256 #define mmRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 11257 #define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 11258 #define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 11259 #define mmRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 11260 11261 11262 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1 11263 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS_DEFAULT 0x00000000 11264 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 11265 #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 11266 #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 11267 #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 11268 #define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11269 #define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11270 #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 11271 #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 11272 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING_DEFAULT 0x00000000 11273 #define mmBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 11274 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 11275 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 11276 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 11277 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 11278 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 11279 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 11280 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 11281 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 11282 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL_DEFAULT 0x00000000 11283 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL_DEFAULT 0x00000000 11284 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 11285 11286 11287 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFDEC2 11288 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 11289 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 11290 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 11291 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 11292 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 11293 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 11294 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 11295 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 11296 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 11297 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 11298 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 11299 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 11300 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 11301 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 11302 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 11303 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 11304 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_PBA_DEFAULT 0x00000000 11305 11306 11307 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_SYSPFVFDEC 11308 #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_DEFAULT 0x00000000 11309 #define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA_DEFAULT 0x00000000 11310 #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI_DEFAULT 0x00000000 11311 11312 11313 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFPFVFDEC1 11314 #define mmRCC_DEV0_EPF0_VF15_RCC_ERR_LOG_DEFAULT 0x00000000 11315 #define mmRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 11316 #define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 11317 #define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 11318 #define mmRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 11319 11320 11321 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1 11322 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS_DEFAULT 0x00000000 11323 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 11324 #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 11325 #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 11326 #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 11327 #define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11328 #define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11329 #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 11330 #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 11331 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING_DEFAULT 0x00000000 11332 #define mmBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 11333 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 11334 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 11335 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 11336 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 11337 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 11338 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 11339 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 11340 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 11341 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL_DEFAULT 0x00000000 11342 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL_DEFAULT 0x00000000 11343 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 11344 11345 11346 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFDEC2 11347 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 11348 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 11349 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 11350 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 11351 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 11352 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 11353 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 11354 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 11355 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 11356 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 11357 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 11358 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 11359 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 11360 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 11361 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 11362 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 11363 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_PBA_DEFAULT 0x00000000 11364 11365 11366 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_SYSPFVFDEC 11367 #define mmBIF_BX_DEV0_EPF0_VF16_MM_INDEX_DEFAULT 0x00000000 11368 #define mmBIF_BX_DEV0_EPF0_VF16_MM_DATA_DEFAULT 0x00000000 11369 #define mmBIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI_DEFAULT 0x00000000 11370 11371 11372 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFPFVFDEC1 11373 #define mmRCC_DEV0_EPF0_VF16_RCC_ERR_LOG_DEFAULT 0x00000000 11374 #define mmRCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 11375 #define mmRCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 11376 #define mmRCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 11377 #define mmRCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 11378 11379 11380 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_BIFPFVFDEC1 11381 #define mmBIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS_DEFAULT 0x00000000 11382 #define mmBIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 11383 #define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 11384 #define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 11385 #define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 11386 #define mmBIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11387 #define mmBIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11388 #define mmBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 11389 #define mmBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 11390 #define mmBIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING_DEFAULT 0x00000000 11391 #define mmBIF_BX_DEV0_EPF0_VF16_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 11392 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 11393 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 11394 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 11395 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 11396 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 11397 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 11398 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 11399 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 11400 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL_DEFAULT 0x00000000 11401 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL_DEFAULT 0x00000000 11402 #define mmBIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 11403 11404 11405 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFDEC2 11406 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 11407 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 11408 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 11409 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 11410 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 11411 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 11412 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 11413 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 11414 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 11415 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 11416 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 11417 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 11418 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 11419 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 11420 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 11421 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 11422 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_PBA_DEFAULT 0x00000000 11423 11424 11425 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_SYSPFVFDEC 11426 #define mmBIF_BX_DEV0_EPF0_VF17_MM_INDEX_DEFAULT 0x00000000 11427 #define mmBIF_BX_DEV0_EPF0_VF17_MM_DATA_DEFAULT 0x00000000 11428 #define mmBIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI_DEFAULT 0x00000000 11429 11430 11431 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFPFVFDEC1 11432 #define mmRCC_DEV0_EPF0_VF17_RCC_ERR_LOG_DEFAULT 0x00000000 11433 #define mmRCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 11434 #define mmRCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 11435 #define mmRCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 11436 #define mmRCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 11437 11438 11439 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_BIFPFVFDEC1 11440 #define mmBIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS_DEFAULT 0x00000000 11441 #define mmBIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 11442 #define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 11443 #define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 11444 #define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 11445 #define mmBIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11446 #define mmBIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11447 #define mmBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 11448 #define mmBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 11449 #define mmBIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING_DEFAULT 0x00000000 11450 #define mmBIF_BX_DEV0_EPF0_VF17_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 11451 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 11452 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 11453 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 11454 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 11455 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 11456 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 11457 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 11458 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 11459 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL_DEFAULT 0x00000000 11460 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL_DEFAULT 0x00000000 11461 #define mmBIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 11462 11463 11464 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFDEC2 11465 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 11466 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 11467 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 11468 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 11469 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 11470 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 11471 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 11472 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 11473 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 11474 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 11475 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 11476 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 11477 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 11478 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 11479 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 11480 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 11481 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_PBA_DEFAULT 0x00000000 11482 11483 11484 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_SYSPFVFDEC 11485 #define mmBIF_BX_DEV0_EPF0_VF18_MM_INDEX_DEFAULT 0x00000000 11486 #define mmBIF_BX_DEV0_EPF0_VF18_MM_DATA_DEFAULT 0x00000000 11487 #define mmBIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI_DEFAULT 0x00000000 11488 11489 11490 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFPFVFDEC1 11491 #define mmRCC_DEV0_EPF0_VF18_RCC_ERR_LOG_DEFAULT 0x00000000 11492 #define mmRCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 11493 #define mmRCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 11494 #define mmRCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 11495 #define mmRCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 11496 11497 11498 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_BIFPFVFDEC1 11499 #define mmBIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS_DEFAULT 0x00000000 11500 #define mmBIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 11501 #define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 11502 #define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 11503 #define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 11504 #define mmBIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11505 #define mmBIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11506 #define mmBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 11507 #define mmBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 11508 #define mmBIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING_DEFAULT 0x00000000 11509 #define mmBIF_BX_DEV0_EPF0_VF18_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 11510 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 11511 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 11512 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 11513 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 11514 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 11515 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 11516 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 11517 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 11518 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL_DEFAULT 0x00000000 11519 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL_DEFAULT 0x00000000 11520 #define mmBIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 11521 11522 11523 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFDEC2 11524 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 11525 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 11526 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 11527 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 11528 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 11529 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 11530 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 11531 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 11532 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 11533 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 11534 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 11535 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 11536 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 11537 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 11538 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 11539 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 11540 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_PBA_DEFAULT 0x00000000 11541 11542 11543 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_SYSPFVFDEC 11544 #define mmBIF_BX_DEV0_EPF0_VF19_MM_INDEX_DEFAULT 0x00000000 11545 #define mmBIF_BX_DEV0_EPF0_VF19_MM_DATA_DEFAULT 0x00000000 11546 #define mmBIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI_DEFAULT 0x00000000 11547 11548 11549 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFPFVFDEC1 11550 #define mmRCC_DEV0_EPF0_VF19_RCC_ERR_LOG_DEFAULT 0x00000000 11551 #define mmRCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 11552 #define mmRCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 11553 #define mmRCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 11554 #define mmRCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 11555 11556 11557 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_BIFPFVFDEC1 11558 #define mmBIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS_DEFAULT 0x00000000 11559 #define mmBIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 11560 #define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 11561 #define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 11562 #define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 11563 #define mmBIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11564 #define mmBIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11565 #define mmBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 11566 #define mmBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 11567 #define mmBIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING_DEFAULT 0x00000000 11568 #define mmBIF_BX_DEV0_EPF0_VF19_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 11569 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 11570 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 11571 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 11572 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 11573 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 11574 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 11575 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 11576 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 11577 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL_DEFAULT 0x00000000 11578 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL_DEFAULT 0x00000000 11579 #define mmBIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 11580 11581 11582 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFDEC2 11583 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 11584 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 11585 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 11586 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 11587 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 11588 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 11589 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 11590 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 11591 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 11592 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 11593 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 11594 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 11595 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 11596 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 11597 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 11598 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 11599 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_PBA_DEFAULT 0x00000000 11600 11601 11602 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_SYSPFVFDEC 11603 #define mmBIF_BX_DEV0_EPF0_VF20_MM_INDEX_DEFAULT 0x00000000 11604 #define mmBIF_BX_DEV0_EPF0_VF20_MM_DATA_DEFAULT 0x00000000 11605 #define mmBIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI_DEFAULT 0x00000000 11606 11607 11608 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFPFVFDEC1 11609 #define mmRCC_DEV0_EPF0_VF20_RCC_ERR_LOG_DEFAULT 0x00000000 11610 #define mmRCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 11611 #define mmRCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 11612 #define mmRCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 11613 #define mmRCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 11614 11615 11616 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_BIFPFVFDEC1 11617 #define mmBIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS_DEFAULT 0x00000000 11618 #define mmBIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 11619 #define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 11620 #define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 11621 #define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 11622 #define mmBIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11623 #define mmBIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11624 #define mmBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 11625 #define mmBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 11626 #define mmBIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING_DEFAULT 0x00000000 11627 #define mmBIF_BX_DEV0_EPF0_VF20_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 11628 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 11629 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 11630 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 11631 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 11632 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 11633 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 11634 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 11635 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 11636 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL_DEFAULT 0x00000000 11637 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL_DEFAULT 0x00000000 11638 #define mmBIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 11639 11640 11641 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFDEC2 11642 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 11643 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 11644 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 11645 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 11646 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 11647 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 11648 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 11649 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 11650 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 11651 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 11652 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 11653 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 11654 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 11655 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 11656 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 11657 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 11658 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_PBA_DEFAULT 0x00000000 11659 11660 11661 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_SYSPFVFDEC 11662 #define mmBIF_BX_DEV0_EPF0_VF21_MM_INDEX_DEFAULT 0x00000000 11663 #define mmBIF_BX_DEV0_EPF0_VF21_MM_DATA_DEFAULT 0x00000000 11664 #define mmBIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI_DEFAULT 0x00000000 11665 11666 11667 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFPFVFDEC1 11668 #define mmRCC_DEV0_EPF0_VF21_RCC_ERR_LOG_DEFAULT 0x00000000 11669 #define mmRCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 11670 #define mmRCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 11671 #define mmRCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 11672 #define mmRCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 11673 11674 11675 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_BIFPFVFDEC1 11676 #define mmBIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS_DEFAULT 0x00000000 11677 #define mmBIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 11678 #define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 11679 #define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 11680 #define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 11681 #define mmBIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11682 #define mmBIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11683 #define mmBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 11684 #define mmBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 11685 #define mmBIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING_DEFAULT 0x00000000 11686 #define mmBIF_BX_DEV0_EPF0_VF21_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 11687 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 11688 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 11689 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 11690 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 11691 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 11692 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 11693 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 11694 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 11695 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL_DEFAULT 0x00000000 11696 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL_DEFAULT 0x00000000 11697 #define mmBIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 11698 11699 11700 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFDEC2 11701 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 11702 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 11703 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 11704 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 11705 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 11706 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 11707 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 11708 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 11709 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 11710 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 11711 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 11712 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 11713 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 11714 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 11715 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 11716 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 11717 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_PBA_DEFAULT 0x00000000 11718 11719 11720 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_SYSPFVFDEC 11721 #define mmBIF_BX_DEV0_EPF0_VF22_MM_INDEX_DEFAULT 0x00000000 11722 #define mmBIF_BX_DEV0_EPF0_VF22_MM_DATA_DEFAULT 0x00000000 11723 #define mmBIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI_DEFAULT 0x00000000 11724 11725 11726 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFPFVFDEC1 11727 #define mmRCC_DEV0_EPF0_VF22_RCC_ERR_LOG_DEFAULT 0x00000000 11728 #define mmRCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 11729 #define mmRCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 11730 #define mmRCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 11731 #define mmRCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 11732 11733 11734 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_BIFPFVFDEC1 11735 #define mmBIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS_DEFAULT 0x00000000 11736 #define mmBIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 11737 #define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 11738 #define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 11739 #define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 11740 #define mmBIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11741 #define mmBIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11742 #define mmBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 11743 #define mmBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 11744 #define mmBIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING_DEFAULT 0x00000000 11745 #define mmBIF_BX_DEV0_EPF0_VF22_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 11746 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 11747 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 11748 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 11749 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 11750 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 11751 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 11752 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 11753 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 11754 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL_DEFAULT 0x00000000 11755 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL_DEFAULT 0x00000000 11756 #define mmBIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 11757 11758 11759 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFDEC2 11760 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 11761 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 11762 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 11763 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 11764 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 11765 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 11766 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 11767 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 11768 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 11769 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 11770 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 11771 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 11772 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 11773 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 11774 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 11775 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 11776 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_PBA_DEFAULT 0x00000000 11777 11778 11779 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_SYSPFVFDEC 11780 #define mmBIF_BX_DEV0_EPF0_VF23_MM_INDEX_DEFAULT 0x00000000 11781 #define mmBIF_BX_DEV0_EPF0_VF23_MM_DATA_DEFAULT 0x00000000 11782 #define mmBIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI_DEFAULT 0x00000000 11783 11784 11785 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFPFVFDEC1 11786 #define mmRCC_DEV0_EPF0_VF23_RCC_ERR_LOG_DEFAULT 0x00000000 11787 #define mmRCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 11788 #define mmRCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 11789 #define mmRCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 11790 #define mmRCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 11791 11792 11793 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_BIFPFVFDEC1 11794 #define mmBIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS_DEFAULT 0x00000000 11795 #define mmBIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 11796 #define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 11797 #define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 11798 #define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 11799 #define mmBIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11800 #define mmBIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11801 #define mmBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 11802 #define mmBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 11803 #define mmBIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING_DEFAULT 0x00000000 11804 #define mmBIF_BX_DEV0_EPF0_VF23_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 11805 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 11806 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 11807 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 11808 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 11809 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 11810 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 11811 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 11812 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 11813 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL_DEFAULT 0x00000000 11814 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL_DEFAULT 0x00000000 11815 #define mmBIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 11816 11817 11818 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFDEC2 11819 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 11820 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 11821 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 11822 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 11823 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 11824 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 11825 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 11826 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 11827 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 11828 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 11829 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 11830 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 11831 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 11832 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 11833 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 11834 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 11835 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_PBA_DEFAULT 0x00000000 11836 11837 11838 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_SYSPFVFDEC 11839 #define mmBIF_BX_DEV0_EPF0_VF24_MM_INDEX_DEFAULT 0x00000000 11840 #define mmBIF_BX_DEV0_EPF0_VF24_MM_DATA_DEFAULT 0x00000000 11841 #define mmBIF_BX_DEV0_EPF0_VF24_MM_INDEX_HI_DEFAULT 0x00000000 11842 11843 11844 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFPFVFDEC1 11845 #define mmRCC_DEV0_EPF0_VF24_RCC_ERR_LOG_DEFAULT 0x00000000 11846 #define mmRCC_DEV0_EPF0_VF24_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 11847 #define mmRCC_DEV0_EPF0_VF24_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 11848 #define mmRCC_DEV0_EPF0_VF24_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 11849 #define mmRCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 11850 11851 11852 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_BIFPFVFDEC1 11853 #define mmBIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS_DEFAULT 0x00000000 11854 #define mmBIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 11855 #define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 11856 #define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 11857 #define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 11858 #define mmBIF_BX_DEV0_EPF0_VF24_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11859 #define mmBIF_BX_DEV0_EPF0_VF24_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11860 #define mmBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 11861 #define mmBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 11862 #define mmBIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING_DEFAULT 0x00000000 11863 #define mmBIF_BX_DEV0_EPF0_VF24_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 11864 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 11865 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 11866 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 11867 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 11868 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 11869 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 11870 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 11871 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 11872 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL_DEFAULT 0x00000000 11873 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL_DEFAULT 0x00000000 11874 #define mmBIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 11875 11876 11877 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFDEC2 11878 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 11879 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 11880 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 11881 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 11882 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 11883 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 11884 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 11885 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 11886 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 11887 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 11888 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 11889 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 11890 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 11891 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 11892 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 11893 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 11894 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_PBA_DEFAULT 0x00000000 11895 11896 11897 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_SYSPFVFDEC 11898 #define mmBIF_BX_DEV0_EPF0_VF25_MM_INDEX_DEFAULT 0x00000000 11899 #define mmBIF_BX_DEV0_EPF0_VF25_MM_DATA_DEFAULT 0x00000000 11900 #define mmBIF_BX_DEV0_EPF0_VF25_MM_INDEX_HI_DEFAULT 0x00000000 11901 11902 11903 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFPFVFDEC1 11904 #define mmRCC_DEV0_EPF0_VF25_RCC_ERR_LOG_DEFAULT 0x00000000 11905 #define mmRCC_DEV0_EPF0_VF25_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 11906 #define mmRCC_DEV0_EPF0_VF25_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 11907 #define mmRCC_DEV0_EPF0_VF25_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 11908 #define mmRCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 11909 11910 11911 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_BIFPFVFDEC1 11912 #define mmBIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS_DEFAULT 0x00000000 11913 #define mmBIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 11914 #define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 11915 #define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 11916 #define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 11917 #define mmBIF_BX_DEV0_EPF0_VF25_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11918 #define mmBIF_BX_DEV0_EPF0_VF25_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11919 #define mmBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 11920 #define mmBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 11921 #define mmBIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING_DEFAULT 0x00000000 11922 #define mmBIF_BX_DEV0_EPF0_VF25_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 11923 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 11924 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 11925 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 11926 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 11927 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 11928 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 11929 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 11930 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 11931 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL_DEFAULT 0x00000000 11932 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL_DEFAULT 0x00000000 11933 #define mmBIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 11934 11935 11936 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFDEC2 11937 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 11938 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 11939 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 11940 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 11941 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 11942 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 11943 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 11944 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 11945 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 11946 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 11947 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 11948 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 11949 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 11950 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 11951 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 11952 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 11953 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_PBA_DEFAULT 0x00000000 11954 11955 11956 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_SYSPFVFDEC 11957 #define mmBIF_BX_DEV0_EPF0_VF26_MM_INDEX_DEFAULT 0x00000000 11958 #define mmBIF_BX_DEV0_EPF0_VF26_MM_DATA_DEFAULT 0x00000000 11959 #define mmBIF_BX_DEV0_EPF0_VF26_MM_INDEX_HI_DEFAULT 0x00000000 11960 11961 11962 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFPFVFDEC1 11963 #define mmRCC_DEV0_EPF0_VF26_RCC_ERR_LOG_DEFAULT 0x00000000 11964 #define mmRCC_DEV0_EPF0_VF26_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 11965 #define mmRCC_DEV0_EPF0_VF26_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 11966 #define mmRCC_DEV0_EPF0_VF26_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 11967 #define mmRCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 11968 11969 11970 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_BIFPFVFDEC1 11971 #define mmBIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS_DEFAULT 0x00000000 11972 #define mmBIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 11973 #define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 11974 #define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 11975 #define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 11976 #define mmBIF_BX_DEV0_EPF0_VF26_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11977 #define mmBIF_BX_DEV0_EPF0_VF26_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 11978 #define mmBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 11979 #define mmBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 11980 #define mmBIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING_DEFAULT 0x00000000 11981 #define mmBIF_BX_DEV0_EPF0_VF26_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 11982 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 11983 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 11984 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 11985 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 11986 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 11987 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 11988 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 11989 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 11990 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL_DEFAULT 0x00000000 11991 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL_DEFAULT 0x00000000 11992 #define mmBIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 11993 11994 11995 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFDEC2 11996 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 11997 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 11998 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 11999 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 12000 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 12001 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 12002 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 12003 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 12004 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 12005 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 12006 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 12007 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 12008 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 12009 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 12010 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 12011 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 12012 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_PBA_DEFAULT 0x00000000 12013 12014 12015 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_SYSPFVFDEC 12016 #define mmBIF_BX_DEV0_EPF0_VF27_MM_INDEX_DEFAULT 0x00000000 12017 #define mmBIF_BX_DEV0_EPF0_VF27_MM_DATA_DEFAULT 0x00000000 12018 #define mmBIF_BX_DEV0_EPF0_VF27_MM_INDEX_HI_DEFAULT 0x00000000 12019 12020 12021 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFPFVFDEC1 12022 #define mmRCC_DEV0_EPF0_VF27_RCC_ERR_LOG_DEFAULT 0x00000000 12023 #define mmRCC_DEV0_EPF0_VF27_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 12024 #define mmRCC_DEV0_EPF0_VF27_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 12025 #define mmRCC_DEV0_EPF0_VF27_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 12026 #define mmRCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 12027 12028 12029 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_BIFPFVFDEC1 12030 #define mmBIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS_DEFAULT 0x00000000 12031 #define mmBIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 12032 #define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 12033 #define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 12034 #define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 12035 #define mmBIF_BX_DEV0_EPF0_VF27_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12036 #define mmBIF_BX_DEV0_EPF0_VF27_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12037 #define mmBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 12038 #define mmBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 12039 #define mmBIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING_DEFAULT 0x00000000 12040 #define mmBIF_BX_DEV0_EPF0_VF27_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 12041 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 12042 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 12043 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 12044 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 12045 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 12046 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 12047 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 12048 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 12049 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL_DEFAULT 0x00000000 12050 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL_DEFAULT 0x00000000 12051 #define mmBIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 12052 12053 12054 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFDEC2 12055 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 12056 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 12057 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 12058 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 12059 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 12060 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 12061 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 12062 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 12063 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 12064 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 12065 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 12066 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 12067 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 12068 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 12069 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 12070 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 12071 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_PBA_DEFAULT 0x00000000 12072 12073 12074 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_SYSPFVFDEC 12075 #define mmBIF_BX_DEV0_EPF0_VF28_MM_INDEX_DEFAULT 0x00000000 12076 #define mmBIF_BX_DEV0_EPF0_VF28_MM_DATA_DEFAULT 0x00000000 12077 #define mmBIF_BX_DEV0_EPF0_VF28_MM_INDEX_HI_DEFAULT 0x00000000 12078 12079 12080 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFPFVFDEC1 12081 #define mmRCC_DEV0_EPF0_VF28_RCC_ERR_LOG_DEFAULT 0x00000000 12082 #define mmRCC_DEV0_EPF0_VF28_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 12083 #define mmRCC_DEV0_EPF0_VF28_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 12084 #define mmRCC_DEV0_EPF0_VF28_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 12085 #define mmRCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 12086 12087 12088 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_BIFPFVFDEC1 12089 #define mmBIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS_DEFAULT 0x00000000 12090 #define mmBIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 12091 #define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 12092 #define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 12093 #define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 12094 #define mmBIF_BX_DEV0_EPF0_VF28_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12095 #define mmBIF_BX_DEV0_EPF0_VF28_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12096 #define mmBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 12097 #define mmBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 12098 #define mmBIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING_DEFAULT 0x00000000 12099 #define mmBIF_BX_DEV0_EPF0_VF28_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 12100 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 12101 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 12102 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 12103 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 12104 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 12105 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 12106 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 12107 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 12108 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL_DEFAULT 0x00000000 12109 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL_DEFAULT 0x00000000 12110 #define mmBIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 12111 12112 12113 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFDEC2 12114 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 12115 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 12116 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 12117 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 12118 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 12119 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 12120 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 12121 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 12122 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 12123 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 12124 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 12125 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 12126 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 12127 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 12128 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 12129 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 12130 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_PBA_DEFAULT 0x00000000 12131 12132 12133 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_SYSPFVFDEC 12134 #define mmBIF_BX_DEV0_EPF0_VF29_MM_INDEX_DEFAULT 0x00000000 12135 #define mmBIF_BX_DEV0_EPF0_VF29_MM_DATA_DEFAULT 0x00000000 12136 #define mmBIF_BX_DEV0_EPF0_VF29_MM_INDEX_HI_DEFAULT 0x00000000 12137 12138 12139 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFPFVFDEC1 12140 #define mmRCC_DEV0_EPF0_VF29_RCC_ERR_LOG_DEFAULT 0x00000000 12141 #define mmRCC_DEV0_EPF0_VF29_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 12142 #define mmRCC_DEV0_EPF0_VF29_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 12143 #define mmRCC_DEV0_EPF0_VF29_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 12144 #define mmRCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 12145 12146 12147 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_BIFPFVFDEC1 12148 #define mmBIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS_DEFAULT 0x00000000 12149 #define mmBIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 12150 #define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 12151 #define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 12152 #define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 12153 #define mmBIF_BX_DEV0_EPF0_VF29_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12154 #define mmBIF_BX_DEV0_EPF0_VF29_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12155 #define mmBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 12156 #define mmBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 12157 #define mmBIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING_DEFAULT 0x00000000 12158 #define mmBIF_BX_DEV0_EPF0_VF29_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 12159 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 12160 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 12161 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 12162 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 12163 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 12164 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 12165 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 12166 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 12167 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL_DEFAULT 0x00000000 12168 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL_DEFAULT 0x00000000 12169 #define mmBIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 12170 12171 12172 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFDEC2 12173 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 12174 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 12175 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 12176 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 12177 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 12178 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 12179 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 12180 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 12181 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 12182 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 12183 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 12184 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 12185 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 12186 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 12187 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 12188 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 12189 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_PBA_DEFAULT 0x00000000 12190 12191 12192 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_SYSPFVFDEC 12193 #define mmBIF_BX_DEV0_EPF0_VF30_MM_INDEX_DEFAULT 0x00000000 12194 #define mmBIF_BX_DEV0_EPF0_VF30_MM_DATA_DEFAULT 0x00000000 12195 #define mmBIF_BX_DEV0_EPF0_VF30_MM_INDEX_HI_DEFAULT 0x00000000 12196 12197 12198 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFPFVFDEC1 12199 #define mmRCC_DEV0_EPF0_VF30_RCC_ERR_LOG_DEFAULT 0x00000000 12200 #define mmRCC_DEV0_EPF0_VF30_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 12201 #define mmRCC_DEV0_EPF0_VF30_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 12202 #define mmRCC_DEV0_EPF0_VF30_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 12203 #define mmRCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 12204 12205 12206 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_BIFPFVFDEC1 12207 #define mmBIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS_DEFAULT 0x00000000 12208 #define mmBIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 12209 #define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 12210 #define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 12211 #define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 12212 #define mmBIF_BX_DEV0_EPF0_VF30_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12213 #define mmBIF_BX_DEV0_EPF0_VF30_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12214 #define mmBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 12215 #define mmBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 12216 #define mmBIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING_DEFAULT 0x00000000 12217 #define mmBIF_BX_DEV0_EPF0_VF30_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 12218 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 12219 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 12220 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 12221 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 12222 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 12223 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 12224 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 12225 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 12226 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL_DEFAULT 0x00000000 12227 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL_DEFAULT 0x00000000 12228 #define mmBIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 12229 12230 12231 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFDEC2 12232 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 12233 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 12234 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 12235 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 12236 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 12237 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 12238 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 12239 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 12240 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 12241 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 12242 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 12243 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 12244 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 12245 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 12246 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 12247 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 12248 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_PBA_DEFAULT 0x00000000 12249 12250 12251 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC 12252 #define cfgBIF_BX_DEV0_EPF0_VF0_MM_INDEX_DEFAULT 0x00000000 12253 #define cfgBIF_BX_DEV0_EPF0_VF0_MM_DATA_DEFAULT 0x00000000 12254 #define cfgBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_DEFAULT 0x00000000 12255 12256 12257 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 12258 #define cfgRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_DEFAULT 0x00000000 12259 #define cfgRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 12260 #define cfgRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 12261 #define cfgRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 12262 #define cfgRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 12263 12264 12265 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 12266 #define cfgBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_DEFAULT 0x00000000 12267 #define cfgBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 12268 #define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 12269 #define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 12270 #define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 12271 #define cfgBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12272 #define cfgBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12273 #define cfgBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 12274 #define cfgBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 12275 #define cfgBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_DEFAULT 0x00000000 12276 #define cfgBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 12277 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 12278 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 12279 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 12280 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 12281 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 12282 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 12283 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 12284 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 12285 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_DEFAULT 0x00000000 12286 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_DEFAULT 0x00000000 12287 #define cfgBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 12288 12289 12290 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 12291 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 12292 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 12293 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 12294 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 12295 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 12296 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 12297 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 12298 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 12299 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 12300 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 12301 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 12302 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 12303 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 12304 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 12305 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 12306 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 12307 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_DEFAULT 0x00000000 12308 12309 12310 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC 12311 #define cfgBIF_BX_DEV0_EPF0_VF1_MM_INDEX_DEFAULT 0x00000000 12312 #define cfgBIF_BX_DEV0_EPF0_VF1_MM_DATA_DEFAULT 0x00000000 12313 #define cfgBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_DEFAULT 0x00000000 12314 12315 12316 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 12317 #define cfgRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_DEFAULT 0x00000000 12318 #define cfgRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 12319 #define cfgRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 12320 #define cfgRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 12321 #define cfgRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 12322 12323 12324 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 12325 #define cfgBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_DEFAULT 0x00000000 12326 #define cfgBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 12327 #define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 12328 #define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 12329 #define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 12330 #define cfgBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12331 #define cfgBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12332 #define cfgBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 12333 #define cfgBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 12334 #define cfgBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_DEFAULT 0x00000000 12335 #define cfgBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 12336 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 12337 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 12338 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 12339 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 12340 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 12341 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 12342 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 12343 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 12344 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_DEFAULT 0x00000000 12345 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_DEFAULT 0x00000000 12346 #define cfgBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 12347 12348 12349 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 12350 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 12351 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 12352 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 12353 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 12354 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 12355 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 12356 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 12357 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 12358 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 12359 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 12360 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 12361 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 12362 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 12363 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 12364 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 12365 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 12366 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_DEFAULT 0x00000000 12367 12368 12369 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC 12370 #define cfgBIF_BX_DEV0_EPF0_VF2_MM_INDEX_DEFAULT 0x00000000 12371 #define cfgBIF_BX_DEV0_EPF0_VF2_MM_DATA_DEFAULT 0x00000000 12372 #define cfgBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_DEFAULT 0x00000000 12373 12374 12375 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 12376 #define cfgRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_DEFAULT 0x00000000 12377 #define cfgRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 12378 #define cfgRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 12379 #define cfgRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 12380 #define cfgRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 12381 12382 12383 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 12384 #define cfgBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_DEFAULT 0x00000000 12385 #define cfgBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 12386 #define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 12387 #define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 12388 #define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 12389 #define cfgBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12390 #define cfgBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12391 #define cfgBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 12392 #define cfgBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 12393 #define cfgBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_DEFAULT 0x00000000 12394 #define cfgBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 12395 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 12396 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 12397 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 12398 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 12399 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 12400 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 12401 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 12402 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 12403 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_DEFAULT 0x00000000 12404 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_DEFAULT 0x00000000 12405 #define cfgBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 12406 12407 12408 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 12409 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 12410 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 12411 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 12412 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 12413 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 12414 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 12415 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 12416 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 12417 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 12418 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 12419 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 12420 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 12421 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 12422 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 12423 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 12424 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 12425 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_DEFAULT 0x00000000 12426 12427 12428 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC 12429 #define cfgBIF_BX_DEV0_EPF0_VF3_MM_INDEX_DEFAULT 0x00000000 12430 #define cfgBIF_BX_DEV0_EPF0_VF3_MM_DATA_DEFAULT 0x00000000 12431 #define cfgBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_DEFAULT 0x00000000 12432 12433 12434 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 12435 #define cfgRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_DEFAULT 0x00000000 12436 #define cfgRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 12437 #define cfgRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 12438 #define cfgRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 12439 #define cfgRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 12440 12441 12442 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 12443 #define cfgBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_DEFAULT 0x00000000 12444 #define cfgBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 12445 #define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 12446 #define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 12447 #define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 12448 #define cfgBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12449 #define cfgBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12450 #define cfgBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 12451 #define cfgBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 12452 #define cfgBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_DEFAULT 0x00000000 12453 #define cfgBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 12454 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 12455 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 12456 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 12457 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 12458 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 12459 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 12460 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 12461 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 12462 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_DEFAULT 0x00000000 12463 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_DEFAULT 0x00000000 12464 #define cfgBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 12465 12466 12467 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 12468 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 12469 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 12470 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 12471 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 12472 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 12473 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 12474 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 12475 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 12476 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 12477 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 12478 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 12479 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 12480 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 12481 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 12482 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 12483 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 12484 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_DEFAULT 0x00000000 12485 12486 12487 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC 12488 #define cfgBIF_BX_DEV0_EPF0_VF4_MM_INDEX_DEFAULT 0x00000000 12489 #define cfgBIF_BX_DEV0_EPF0_VF4_MM_DATA_DEFAULT 0x00000000 12490 #define cfgBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_DEFAULT 0x00000000 12491 12492 12493 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 12494 #define cfgRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_DEFAULT 0x00000000 12495 #define cfgRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 12496 #define cfgRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 12497 #define cfgRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 12498 #define cfgRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 12499 12500 12501 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 12502 #define cfgBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_DEFAULT 0x00000000 12503 #define cfgBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 12504 #define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 12505 #define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 12506 #define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 12507 #define cfgBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12508 #define cfgBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12509 #define cfgBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 12510 #define cfgBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 12511 #define cfgBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_DEFAULT 0x00000000 12512 #define cfgBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 12513 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 12514 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 12515 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 12516 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 12517 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 12518 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 12519 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 12520 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 12521 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_DEFAULT 0x00000000 12522 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_DEFAULT 0x00000000 12523 #define cfgBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 12524 12525 12526 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 12527 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 12528 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 12529 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 12530 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 12531 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 12532 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 12533 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 12534 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 12535 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 12536 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 12537 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 12538 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 12539 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 12540 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 12541 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 12542 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 12543 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_DEFAULT 0x00000000 12544 12545 12546 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC 12547 #define cfgBIF_BX_DEV0_EPF0_VF5_MM_INDEX_DEFAULT 0x00000000 12548 #define cfgBIF_BX_DEV0_EPF0_VF5_MM_DATA_DEFAULT 0x00000000 12549 #define cfgBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_DEFAULT 0x00000000 12550 12551 12552 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 12553 #define cfgRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_DEFAULT 0x00000000 12554 #define cfgRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 12555 #define cfgRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 12556 #define cfgRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 12557 #define cfgRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 12558 12559 12560 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 12561 #define cfgBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_DEFAULT 0x00000000 12562 #define cfgBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 12563 #define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 12564 #define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 12565 #define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 12566 #define cfgBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12567 #define cfgBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12568 #define cfgBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 12569 #define cfgBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 12570 #define cfgBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_DEFAULT 0x00000000 12571 #define cfgBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 12572 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 12573 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 12574 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 12575 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 12576 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 12577 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 12578 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 12579 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 12580 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_DEFAULT 0x00000000 12581 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_DEFAULT 0x00000000 12582 #define cfgBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 12583 12584 12585 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 12586 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 12587 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 12588 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 12589 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 12590 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 12591 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 12592 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 12593 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 12594 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 12595 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 12596 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 12597 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 12598 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 12599 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 12600 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 12601 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 12602 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_DEFAULT 0x00000000 12603 12604 12605 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC 12606 #define cfgBIF_BX_DEV0_EPF0_VF6_MM_INDEX_DEFAULT 0x00000000 12607 #define cfgBIF_BX_DEV0_EPF0_VF6_MM_DATA_DEFAULT 0x00000000 12608 #define cfgBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_DEFAULT 0x00000000 12609 12610 12611 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 12612 #define cfgRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_DEFAULT 0x00000000 12613 #define cfgRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 12614 #define cfgRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 12615 #define cfgRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 12616 #define cfgRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 12617 12618 12619 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 12620 #define cfgBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_DEFAULT 0x00000000 12621 #define cfgBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 12622 #define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 12623 #define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 12624 #define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 12625 #define cfgBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12626 #define cfgBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12627 #define cfgBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 12628 #define cfgBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 12629 #define cfgBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_DEFAULT 0x00000000 12630 #define cfgBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 12631 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 12632 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 12633 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 12634 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 12635 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 12636 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 12637 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 12638 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 12639 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_DEFAULT 0x00000000 12640 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_DEFAULT 0x00000000 12641 #define cfgBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 12642 12643 12644 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 12645 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 12646 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 12647 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 12648 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 12649 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 12650 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 12651 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 12652 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 12653 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 12654 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 12655 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 12656 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 12657 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 12658 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 12659 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 12660 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 12661 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_DEFAULT 0x00000000 12662 12663 12664 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC 12665 #define cfgBIF_BX_DEV0_EPF0_VF7_MM_INDEX_DEFAULT 0x00000000 12666 #define cfgBIF_BX_DEV0_EPF0_VF7_MM_DATA_DEFAULT 0x00000000 12667 #define cfgBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_DEFAULT 0x00000000 12668 12669 12670 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 12671 #define cfgRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_DEFAULT 0x00000000 12672 #define cfgRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 12673 #define cfgRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 12674 #define cfgRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 12675 #define cfgRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 12676 12677 12678 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 12679 #define cfgBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_DEFAULT 0x00000000 12680 #define cfgBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 12681 #define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 12682 #define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 12683 #define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 12684 #define cfgBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12685 #define cfgBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12686 #define cfgBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 12687 #define cfgBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 12688 #define cfgBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_DEFAULT 0x00000000 12689 #define cfgBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 12690 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 12691 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 12692 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 12693 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 12694 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 12695 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 12696 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 12697 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 12698 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_DEFAULT 0x00000000 12699 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_DEFAULT 0x00000000 12700 #define cfgBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 12701 12702 12703 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 12704 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 12705 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 12706 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 12707 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 12708 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 12709 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 12710 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 12711 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 12712 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 12713 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 12714 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 12715 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 12716 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 12717 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 12718 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 12719 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 12720 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_DEFAULT 0x00000000 12721 12722 12723 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_SYSPFVFDEC 12724 #define cfgBIF_BX_DEV0_EPF0_VF8_MM_INDEX_DEFAULT 0x00000000 12725 #define cfgBIF_BX_DEV0_EPF0_VF8_MM_DATA_DEFAULT 0x00000000 12726 #define cfgBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI_DEFAULT 0x00000000 12727 12728 12729 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFPFVFDEC1 12730 #define cfgRCC_DEV0_EPF0_VF8_RCC_ERR_LOG_DEFAULT 0x00000000 12731 #define cfgRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 12732 #define cfgRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 12733 #define cfgRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 12734 #define cfgRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 12735 12736 12737 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1 12738 #define cfgBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS_DEFAULT 0x00000000 12739 #define cfgBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 12740 #define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 12741 #define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 12742 #define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 12743 #define cfgBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12744 #define cfgBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12745 #define cfgBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 12746 #define cfgBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 12747 #define cfgBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING_DEFAULT 0x00000000 12748 #define cfgBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 12749 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 12750 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 12751 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 12752 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 12753 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 12754 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 12755 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 12756 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 12757 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL_DEFAULT 0x00000000 12758 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL_DEFAULT 0x00000000 12759 #define cfgBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 12760 12761 12762 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFDEC2 12763 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 12764 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 12765 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 12766 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 12767 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 12768 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 12769 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 12770 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 12771 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 12772 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 12773 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 12774 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 12775 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 12776 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 12777 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 12778 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 12779 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_PBA_DEFAULT 0x00000000 12780 12781 12782 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_SYSPFVFDEC 12783 #define cfgBIF_BX_DEV0_EPF0_VF9_MM_INDEX_DEFAULT 0x00000000 12784 #define cfgBIF_BX_DEV0_EPF0_VF9_MM_DATA_DEFAULT 0x00000000 12785 #define cfgBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI_DEFAULT 0x00000000 12786 12787 12788 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFPFVFDEC1 12789 #define cfgRCC_DEV0_EPF0_VF9_RCC_ERR_LOG_DEFAULT 0x00000000 12790 #define cfgRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 12791 #define cfgRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 12792 #define cfgRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 12793 #define cfgRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 12794 12795 12796 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1 12797 #define cfgBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS_DEFAULT 0x00000000 12798 #define cfgBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 12799 #define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 12800 #define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 12801 #define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 12802 #define cfgBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12803 #define cfgBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12804 #define cfgBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 12805 #define cfgBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 12806 #define cfgBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING_DEFAULT 0x00000000 12807 #define cfgBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 12808 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 12809 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 12810 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 12811 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 12812 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 12813 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 12814 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 12815 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 12816 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL_DEFAULT 0x00000000 12817 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL_DEFAULT 0x00000000 12818 #define cfgBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 12819 12820 12821 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFDEC2 12822 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 12823 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 12824 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 12825 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 12826 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 12827 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 12828 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 12829 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 12830 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 12831 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 12832 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 12833 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 12834 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 12835 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 12836 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 12837 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 12838 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_PBA_DEFAULT 0x00000000 12839 12840 12841 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_SYSPFVFDEC 12842 #define cfgBIF_BX_DEV0_EPF0_VF10_MM_INDEX_DEFAULT 0x00000000 12843 #define cfgBIF_BX_DEV0_EPF0_VF10_MM_DATA_DEFAULT 0x00000000 12844 #define cfgBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI_DEFAULT 0x00000000 12845 12846 12847 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFPFVFDEC1 12848 #define cfgRCC_DEV0_EPF0_VF10_RCC_ERR_LOG_DEFAULT 0x00000000 12849 #define cfgRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 12850 #define cfgRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 12851 #define cfgRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 12852 #define cfgRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 12853 12854 12855 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1 12856 #define cfgBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS_DEFAULT 0x00000000 12857 #define cfgBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 12858 #define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 12859 #define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 12860 #define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 12861 #define cfgBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12862 #define cfgBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12863 #define cfgBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 12864 #define cfgBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 12865 #define cfgBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING_DEFAULT 0x00000000 12866 #define cfgBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 12867 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 12868 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 12869 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 12870 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 12871 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 12872 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 12873 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 12874 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 12875 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL_DEFAULT 0x00000000 12876 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL_DEFAULT 0x00000000 12877 #define cfgBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 12878 12879 12880 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFDEC2 12881 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 12882 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 12883 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 12884 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 12885 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 12886 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 12887 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 12888 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 12889 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 12890 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 12891 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 12892 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 12893 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 12894 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 12895 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 12896 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 12897 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_PBA_DEFAULT 0x00000000 12898 12899 12900 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_SYSPFVFDEC 12901 #define cfgBIF_BX_DEV0_EPF0_VF11_MM_INDEX_DEFAULT 0x00000000 12902 #define cfgBIF_BX_DEV0_EPF0_VF11_MM_DATA_DEFAULT 0x00000000 12903 #define cfgBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI_DEFAULT 0x00000000 12904 12905 12906 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFPFVFDEC1 12907 #define cfgRCC_DEV0_EPF0_VF11_RCC_ERR_LOG_DEFAULT 0x00000000 12908 #define cfgRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 12909 #define cfgRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 12910 #define cfgRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 12911 #define cfgRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 12912 12913 12914 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1 12915 #define cfgBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS_DEFAULT 0x00000000 12916 #define cfgBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 12917 #define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 12918 #define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 12919 #define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 12920 #define cfgBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12921 #define cfgBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12922 #define cfgBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 12923 #define cfgBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 12924 #define cfgBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING_DEFAULT 0x00000000 12925 #define cfgBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 12926 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 12927 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 12928 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 12929 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 12930 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 12931 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 12932 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 12933 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 12934 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL_DEFAULT 0x00000000 12935 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL_DEFAULT 0x00000000 12936 #define cfgBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 12937 12938 12939 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFDEC2 12940 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 12941 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 12942 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 12943 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 12944 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 12945 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 12946 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 12947 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 12948 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 12949 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 12950 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 12951 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 12952 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 12953 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 12954 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 12955 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 12956 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_PBA_DEFAULT 0x00000000 12957 12958 12959 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_SYSPFVFDEC 12960 #define cfgBIF_BX_DEV0_EPF0_VF12_MM_INDEX_DEFAULT 0x00000000 12961 #define cfgBIF_BX_DEV0_EPF0_VF12_MM_DATA_DEFAULT 0x00000000 12962 #define cfgBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI_DEFAULT 0x00000000 12963 12964 12965 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFPFVFDEC1 12966 #define cfgRCC_DEV0_EPF0_VF12_RCC_ERR_LOG_DEFAULT 0x00000000 12967 #define cfgRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 12968 #define cfgRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 12969 #define cfgRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 12970 #define cfgRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 12971 12972 12973 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1 12974 #define cfgBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS_DEFAULT 0x00000000 12975 #define cfgBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 12976 #define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 12977 #define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 12978 #define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 12979 #define cfgBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12980 #define cfgBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 12981 #define cfgBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 12982 #define cfgBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 12983 #define cfgBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING_DEFAULT 0x00000000 12984 #define cfgBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 12985 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 12986 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 12987 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 12988 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 12989 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 12990 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 12991 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 12992 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 12993 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL_DEFAULT 0x00000000 12994 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL_DEFAULT 0x00000000 12995 #define cfgBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 12996 12997 12998 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFDEC2 12999 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 13000 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 13001 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 13002 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 13003 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 13004 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 13005 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 13006 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 13007 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 13008 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 13009 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 13010 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 13011 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 13012 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 13013 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 13014 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 13015 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_PBA_DEFAULT 0x00000000 13016 13017 13018 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_SYSPFVFDEC 13019 #define cfgBIF_BX_DEV0_EPF0_VF13_MM_INDEX_DEFAULT 0x00000000 13020 #define cfgBIF_BX_DEV0_EPF0_VF13_MM_DATA_DEFAULT 0x00000000 13021 #define cfgBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI_DEFAULT 0x00000000 13022 13023 13024 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFPFVFDEC1 13025 #define cfgRCC_DEV0_EPF0_VF13_RCC_ERR_LOG_DEFAULT 0x00000000 13026 #define cfgRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 13027 #define cfgRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 13028 #define cfgRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 13029 #define cfgRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 13030 13031 13032 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1 13033 #define cfgBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS_DEFAULT 0x00000000 13034 #define cfgBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 13035 #define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 13036 #define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 13037 #define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 13038 #define cfgBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13039 #define cfgBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13040 #define cfgBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 13041 #define cfgBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 13042 #define cfgBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING_DEFAULT 0x00000000 13043 #define cfgBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 13044 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 13045 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 13046 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 13047 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 13048 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 13049 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 13050 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 13051 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 13052 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL_DEFAULT 0x00000000 13053 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL_DEFAULT 0x00000000 13054 #define cfgBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 13055 13056 13057 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFDEC2 13058 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 13059 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 13060 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 13061 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 13062 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 13063 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 13064 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 13065 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 13066 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 13067 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 13068 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 13069 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 13070 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 13071 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 13072 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 13073 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 13074 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_PBA_DEFAULT 0x00000000 13075 13076 13077 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_SYSPFVFDEC 13078 #define cfgBIF_BX_DEV0_EPF0_VF14_MM_INDEX_DEFAULT 0x00000000 13079 #define cfgBIF_BX_DEV0_EPF0_VF14_MM_DATA_DEFAULT 0x00000000 13080 #define cfgBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI_DEFAULT 0x00000000 13081 13082 13083 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFPFVFDEC1 13084 #define cfgRCC_DEV0_EPF0_VF14_RCC_ERR_LOG_DEFAULT 0x00000000 13085 #define cfgRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 13086 #define cfgRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 13087 #define cfgRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 13088 #define cfgRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 13089 13090 13091 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1 13092 #define cfgBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS_DEFAULT 0x00000000 13093 #define cfgBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 13094 #define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 13095 #define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 13096 #define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 13097 #define cfgBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13098 #define cfgBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13099 #define cfgBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 13100 #define cfgBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 13101 #define cfgBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING_DEFAULT 0x00000000 13102 #define cfgBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 13103 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 13104 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 13105 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 13106 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 13107 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 13108 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 13109 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 13110 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 13111 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL_DEFAULT 0x00000000 13112 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL_DEFAULT 0x00000000 13113 #define cfgBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 13114 13115 13116 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFDEC2 13117 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 13118 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 13119 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 13120 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 13121 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 13122 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 13123 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 13124 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 13125 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 13126 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 13127 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 13128 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 13129 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 13130 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 13131 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 13132 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 13133 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_PBA_DEFAULT 0x00000000 13134 13135 13136 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_SYSPFVFDEC 13137 #define cfgBIF_BX_DEV0_EPF0_VF15_MM_INDEX_DEFAULT 0x00000000 13138 #define cfgBIF_BX_DEV0_EPF0_VF15_MM_DATA_DEFAULT 0x00000000 13139 #define cfgBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI_DEFAULT 0x00000000 13140 13141 13142 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFPFVFDEC1 13143 #define cfgRCC_DEV0_EPF0_VF15_RCC_ERR_LOG_DEFAULT 0x00000000 13144 #define cfgRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 13145 #define cfgRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 13146 #define cfgRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 13147 #define cfgRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 13148 13149 13150 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1 13151 #define cfgBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS_DEFAULT 0x00000000 13152 #define cfgBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 13153 #define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 13154 #define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 13155 #define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 13156 #define cfgBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13157 #define cfgBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13158 #define cfgBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 13159 #define cfgBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 13160 #define cfgBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING_DEFAULT 0x00000000 13161 #define cfgBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 13162 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 13163 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 13164 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 13165 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 13166 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 13167 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 13168 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 13169 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 13170 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL_DEFAULT 0x00000000 13171 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL_DEFAULT 0x00000000 13172 #define cfgBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 13173 13174 13175 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFDEC2 13176 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 13177 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 13178 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 13179 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 13180 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 13181 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 13182 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 13183 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 13184 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 13185 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 13186 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 13187 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 13188 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 13189 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 13190 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 13191 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 13192 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_PBA_DEFAULT 0x00000000 13193 13194 13195 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_SYSPFVFDEC 13196 #define cfgBIF_BX_DEV0_EPF0_VF16_MM_INDEX_DEFAULT 0x00000000 13197 #define cfgBIF_BX_DEV0_EPF0_VF16_MM_DATA_DEFAULT 0x00000000 13198 #define cfgBIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI_DEFAULT 0x00000000 13199 13200 13201 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFPFVFDEC1 13202 #define cfgRCC_DEV0_EPF0_VF16_RCC_ERR_LOG_DEFAULT 0x00000000 13203 #define cfgRCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 13204 #define cfgRCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 13205 #define cfgRCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 13206 #define cfgRCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 13207 13208 13209 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_BIFPFVFDEC1 13210 #define cfgBIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS_DEFAULT 0x00000000 13211 #define cfgBIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 13212 #define cfgBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 13213 #define cfgBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 13214 #define cfgBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 13215 #define cfgBIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13216 #define cfgBIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13217 #define cfgBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 13218 #define cfgBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 13219 #define cfgBIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING_DEFAULT 0x00000000 13220 #define cfgBIF_BX_DEV0_EPF0_VF16_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 13221 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 13222 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 13223 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 13224 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 13225 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 13226 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 13227 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 13228 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 13229 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL_DEFAULT 0x00000000 13230 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL_DEFAULT 0x00000000 13231 #define cfgBIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 13232 13233 13234 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFDEC2 13235 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 13236 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 13237 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 13238 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 13239 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 13240 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 13241 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 13242 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 13243 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 13244 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 13245 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 13246 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 13247 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 13248 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 13249 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 13250 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 13251 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_PBA_DEFAULT 0x00000000 13252 13253 13254 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_SYSPFVFDEC 13255 #define cfgBIF_BX_DEV0_EPF0_VF17_MM_INDEX_DEFAULT 0x00000000 13256 #define cfgBIF_BX_DEV0_EPF0_VF17_MM_DATA_DEFAULT 0x00000000 13257 #define cfgBIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI_DEFAULT 0x00000000 13258 13259 13260 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFPFVFDEC1 13261 #define cfgRCC_DEV0_EPF0_VF17_RCC_ERR_LOG_DEFAULT 0x00000000 13262 #define cfgRCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 13263 #define cfgRCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 13264 #define cfgRCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 13265 #define cfgRCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 13266 13267 13268 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_BIFPFVFDEC1 13269 #define cfgBIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS_DEFAULT 0x00000000 13270 #define cfgBIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 13271 #define cfgBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 13272 #define cfgBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 13273 #define cfgBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 13274 #define cfgBIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13275 #define cfgBIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13276 #define cfgBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 13277 #define cfgBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 13278 #define cfgBIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING_DEFAULT 0x00000000 13279 #define cfgBIF_BX_DEV0_EPF0_VF17_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 13280 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 13281 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 13282 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 13283 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 13284 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 13285 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 13286 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 13287 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 13288 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL_DEFAULT 0x00000000 13289 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL_DEFAULT 0x00000000 13290 #define cfgBIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 13291 13292 13293 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFDEC2 13294 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 13295 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 13296 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 13297 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 13298 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 13299 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 13300 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 13301 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 13302 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 13303 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 13304 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 13305 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 13306 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 13307 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 13308 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 13309 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 13310 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_PBA_DEFAULT 0x00000000 13311 13312 13313 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_SYSPFVFDEC 13314 #define cfgBIF_BX_DEV0_EPF0_VF18_MM_INDEX_DEFAULT 0x00000000 13315 #define cfgBIF_BX_DEV0_EPF0_VF18_MM_DATA_DEFAULT 0x00000000 13316 #define cfgBIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI_DEFAULT 0x00000000 13317 13318 13319 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFPFVFDEC1 13320 #define cfgRCC_DEV0_EPF0_VF18_RCC_ERR_LOG_DEFAULT 0x00000000 13321 #define cfgRCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 13322 #define cfgRCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 13323 #define cfgRCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 13324 #define cfgRCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 13325 13326 13327 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_BIFPFVFDEC1 13328 #define cfgBIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS_DEFAULT 0x00000000 13329 #define cfgBIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 13330 #define cfgBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 13331 #define cfgBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 13332 #define cfgBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 13333 #define cfgBIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13334 #define cfgBIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13335 #define cfgBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 13336 #define cfgBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 13337 #define cfgBIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING_DEFAULT 0x00000000 13338 #define cfgBIF_BX_DEV0_EPF0_VF18_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 13339 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 13340 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 13341 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 13342 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 13343 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 13344 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 13345 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 13346 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 13347 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL_DEFAULT 0x00000000 13348 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL_DEFAULT 0x00000000 13349 #define cfgBIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 13350 13351 13352 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFDEC2 13353 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 13354 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 13355 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 13356 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 13357 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 13358 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 13359 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 13360 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 13361 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 13362 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 13363 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 13364 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 13365 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 13366 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 13367 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 13368 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 13369 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_PBA_DEFAULT 0x00000000 13370 13371 13372 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_SYSPFVFDEC 13373 #define cfgBIF_BX_DEV0_EPF0_VF19_MM_INDEX_DEFAULT 0x00000000 13374 #define cfgBIF_BX_DEV0_EPF0_VF19_MM_DATA_DEFAULT 0x00000000 13375 #define cfgBIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI_DEFAULT 0x00000000 13376 13377 13378 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFPFVFDEC1 13379 #define cfgRCC_DEV0_EPF0_VF19_RCC_ERR_LOG_DEFAULT 0x00000000 13380 #define cfgRCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 13381 #define cfgRCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 13382 #define cfgRCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 13383 #define cfgRCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 13384 13385 13386 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_BIFPFVFDEC1 13387 #define cfgBIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS_DEFAULT 0x00000000 13388 #define cfgBIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 13389 #define cfgBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 13390 #define cfgBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 13391 #define cfgBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 13392 #define cfgBIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13393 #define cfgBIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13394 #define cfgBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 13395 #define cfgBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 13396 #define cfgBIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING_DEFAULT 0x00000000 13397 #define cfgBIF_BX_DEV0_EPF0_VF19_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 13398 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 13399 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 13400 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 13401 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 13402 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 13403 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 13404 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 13405 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 13406 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL_DEFAULT 0x00000000 13407 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL_DEFAULT 0x00000000 13408 #define cfgBIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 13409 13410 13411 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFDEC2 13412 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 13413 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 13414 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 13415 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 13416 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 13417 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 13418 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 13419 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 13420 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 13421 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 13422 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 13423 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 13424 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 13425 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 13426 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 13427 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 13428 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_PBA_DEFAULT 0x00000000 13429 13430 13431 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_SYSPFVFDEC 13432 #define cfgBIF_BX_DEV0_EPF0_VF20_MM_INDEX_DEFAULT 0x00000000 13433 #define cfgBIF_BX_DEV0_EPF0_VF20_MM_DATA_DEFAULT 0x00000000 13434 #define cfgBIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI_DEFAULT 0x00000000 13435 13436 13437 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFPFVFDEC1 13438 #define cfgRCC_DEV0_EPF0_VF20_RCC_ERR_LOG_DEFAULT 0x00000000 13439 #define cfgRCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 13440 #define cfgRCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 13441 #define cfgRCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 13442 #define cfgRCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 13443 13444 13445 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_BIFPFVFDEC1 13446 #define cfgBIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS_DEFAULT 0x00000000 13447 #define cfgBIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 13448 #define cfgBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 13449 #define cfgBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 13450 #define cfgBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 13451 #define cfgBIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13452 #define cfgBIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13453 #define cfgBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 13454 #define cfgBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 13455 #define cfgBIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING_DEFAULT 0x00000000 13456 #define cfgBIF_BX_DEV0_EPF0_VF20_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 13457 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 13458 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 13459 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 13460 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 13461 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 13462 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 13463 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 13464 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 13465 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL_DEFAULT 0x00000000 13466 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL_DEFAULT 0x00000000 13467 #define cfgBIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 13468 13469 13470 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFDEC2 13471 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 13472 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 13473 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 13474 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 13475 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 13476 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 13477 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 13478 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 13479 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 13480 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 13481 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 13482 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 13483 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 13484 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 13485 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 13486 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 13487 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_PBA_DEFAULT 0x00000000 13488 13489 13490 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_SYSPFVFDEC 13491 #define cfgBIF_BX_DEV0_EPF0_VF21_MM_INDEX_DEFAULT 0x00000000 13492 #define cfgBIF_BX_DEV0_EPF0_VF21_MM_DATA_DEFAULT 0x00000000 13493 #define cfgBIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI_DEFAULT 0x00000000 13494 13495 13496 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFPFVFDEC1 13497 #define cfgRCC_DEV0_EPF0_VF21_RCC_ERR_LOG_DEFAULT 0x00000000 13498 #define cfgRCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 13499 #define cfgRCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 13500 #define cfgRCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 13501 #define cfgRCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 13502 13503 13504 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_BIFPFVFDEC1 13505 #define cfgBIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS_DEFAULT 0x00000000 13506 #define cfgBIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 13507 #define cfgBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 13508 #define cfgBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 13509 #define cfgBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 13510 #define cfgBIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13511 #define cfgBIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13512 #define cfgBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 13513 #define cfgBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 13514 #define cfgBIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING_DEFAULT 0x00000000 13515 #define cfgBIF_BX_DEV0_EPF0_VF21_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 13516 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 13517 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 13518 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 13519 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 13520 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 13521 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 13522 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 13523 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 13524 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL_DEFAULT 0x00000000 13525 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL_DEFAULT 0x00000000 13526 #define cfgBIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 13527 13528 13529 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFDEC2 13530 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 13531 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 13532 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 13533 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 13534 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 13535 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 13536 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 13537 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 13538 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 13539 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 13540 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 13541 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 13542 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 13543 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 13544 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 13545 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 13546 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_PBA_DEFAULT 0x00000000 13547 13548 13549 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_SYSPFVFDEC 13550 #define cfgBIF_BX_DEV0_EPF0_VF22_MM_INDEX_DEFAULT 0x00000000 13551 #define cfgBIF_BX_DEV0_EPF0_VF22_MM_DATA_DEFAULT 0x00000000 13552 #define cfgBIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI_DEFAULT 0x00000000 13553 13554 13555 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFPFVFDEC1 13556 #define cfgRCC_DEV0_EPF0_VF22_RCC_ERR_LOG_DEFAULT 0x00000000 13557 #define cfgRCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 13558 #define cfgRCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 13559 #define cfgRCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 13560 #define cfgRCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 13561 13562 13563 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_BIFPFVFDEC1 13564 #define cfgBIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS_DEFAULT 0x00000000 13565 #define cfgBIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 13566 #define cfgBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 13567 #define cfgBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 13568 #define cfgBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 13569 #define cfgBIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13570 #define cfgBIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13571 #define cfgBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 13572 #define cfgBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 13573 #define cfgBIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING_DEFAULT 0x00000000 13574 #define cfgBIF_BX_DEV0_EPF0_VF22_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 13575 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 13576 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 13577 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 13578 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 13579 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 13580 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 13581 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 13582 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 13583 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL_DEFAULT 0x00000000 13584 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL_DEFAULT 0x00000000 13585 #define cfgBIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 13586 13587 13588 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFDEC2 13589 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 13590 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 13591 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 13592 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 13593 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 13594 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 13595 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 13596 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 13597 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 13598 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 13599 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 13600 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 13601 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 13602 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 13603 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 13604 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 13605 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_PBA_DEFAULT 0x00000000 13606 13607 13608 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_SYSPFVFDEC 13609 #define cfgBIF_BX_DEV0_EPF0_VF23_MM_INDEX_DEFAULT 0x00000000 13610 #define cfgBIF_BX_DEV0_EPF0_VF23_MM_DATA_DEFAULT 0x00000000 13611 #define cfgBIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI_DEFAULT 0x00000000 13612 13613 13614 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFPFVFDEC1 13615 #define cfgRCC_DEV0_EPF0_VF23_RCC_ERR_LOG_DEFAULT 0x00000000 13616 #define cfgRCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 13617 #define cfgRCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 13618 #define cfgRCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 13619 #define cfgRCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 13620 13621 13622 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_BIFPFVFDEC1 13623 #define cfgBIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS_DEFAULT 0x00000000 13624 #define cfgBIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 13625 #define cfgBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 13626 #define cfgBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 13627 #define cfgBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 13628 #define cfgBIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13629 #define cfgBIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13630 #define cfgBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 13631 #define cfgBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 13632 #define cfgBIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING_DEFAULT 0x00000000 13633 #define cfgBIF_BX_DEV0_EPF0_VF23_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 13634 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 13635 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 13636 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 13637 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 13638 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 13639 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 13640 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 13641 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 13642 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL_DEFAULT 0x00000000 13643 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL_DEFAULT 0x00000000 13644 #define cfgBIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 13645 13646 13647 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFDEC2 13648 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 13649 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 13650 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 13651 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 13652 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 13653 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 13654 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 13655 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 13656 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 13657 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 13658 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 13659 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 13660 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 13661 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 13662 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 13663 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 13664 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_PBA_DEFAULT 0x00000000 13665 13666 13667 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_SYSPFVFDEC 13668 #define cfgBIF_BX_DEV0_EPF0_VF24_MM_INDEX_DEFAULT 0x00000000 13669 #define cfgBIF_BX_DEV0_EPF0_VF24_MM_DATA_DEFAULT 0x00000000 13670 #define cfgBIF_BX_DEV0_EPF0_VF24_MM_INDEX_HI_DEFAULT 0x00000000 13671 13672 13673 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFPFVFDEC1 13674 #define cfgRCC_DEV0_EPF0_VF24_RCC_ERR_LOG_DEFAULT 0x00000000 13675 #define cfgRCC_DEV0_EPF0_VF24_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 13676 #define cfgRCC_DEV0_EPF0_VF24_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 13677 #define cfgRCC_DEV0_EPF0_VF24_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 13678 #define cfgRCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 13679 13680 13681 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_BIFPFVFDEC1 13682 #define cfgBIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS_DEFAULT 0x00000000 13683 #define cfgBIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 13684 #define cfgBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 13685 #define cfgBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 13686 #define cfgBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 13687 #define cfgBIF_BX_DEV0_EPF0_VF24_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13688 #define cfgBIF_BX_DEV0_EPF0_VF24_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13689 #define cfgBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 13690 #define cfgBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 13691 #define cfgBIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING_DEFAULT 0x00000000 13692 #define cfgBIF_BX_DEV0_EPF0_VF24_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 13693 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 13694 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 13695 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 13696 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 13697 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 13698 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 13699 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 13700 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 13701 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL_DEFAULT 0x00000000 13702 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL_DEFAULT 0x00000000 13703 #define cfgBIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 13704 13705 13706 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFDEC2 13707 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 13708 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 13709 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 13710 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 13711 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 13712 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 13713 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 13714 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 13715 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 13716 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 13717 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 13718 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 13719 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 13720 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 13721 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 13722 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 13723 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_PBA_DEFAULT 0x00000000 13724 13725 13726 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_SYSPFVFDEC 13727 #define cfgBIF_BX_DEV0_EPF0_VF25_MM_INDEX_DEFAULT 0x00000000 13728 #define cfgBIF_BX_DEV0_EPF0_VF25_MM_DATA_DEFAULT 0x00000000 13729 #define cfgBIF_BX_DEV0_EPF0_VF25_MM_INDEX_HI_DEFAULT 0x00000000 13730 13731 13732 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFPFVFDEC1 13733 #define cfgRCC_DEV0_EPF0_VF25_RCC_ERR_LOG_DEFAULT 0x00000000 13734 #define cfgRCC_DEV0_EPF0_VF25_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 13735 #define cfgRCC_DEV0_EPF0_VF25_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 13736 #define cfgRCC_DEV0_EPF0_VF25_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 13737 #define cfgRCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 13738 13739 13740 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_BIFPFVFDEC1 13741 #define cfgBIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS_DEFAULT 0x00000000 13742 #define cfgBIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 13743 #define cfgBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 13744 #define cfgBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 13745 #define cfgBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 13746 #define cfgBIF_BX_DEV0_EPF0_VF25_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13747 #define cfgBIF_BX_DEV0_EPF0_VF25_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13748 #define cfgBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 13749 #define cfgBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 13750 #define cfgBIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING_DEFAULT 0x00000000 13751 #define cfgBIF_BX_DEV0_EPF0_VF25_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 13752 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 13753 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 13754 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 13755 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 13756 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 13757 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 13758 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 13759 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 13760 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL_DEFAULT 0x00000000 13761 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL_DEFAULT 0x00000000 13762 #define cfgBIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 13763 13764 13765 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFDEC2 13766 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 13767 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 13768 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 13769 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 13770 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 13771 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 13772 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 13773 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 13774 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 13775 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 13776 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 13777 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 13778 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 13779 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 13780 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 13781 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 13782 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_PBA_DEFAULT 0x00000000 13783 13784 13785 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_SYSPFVFDEC 13786 #define cfgBIF_BX_DEV0_EPF0_VF26_MM_INDEX_DEFAULT 0x00000000 13787 #define cfgBIF_BX_DEV0_EPF0_VF26_MM_DATA_DEFAULT 0x00000000 13788 #define cfgBIF_BX_DEV0_EPF0_VF26_MM_INDEX_HI_DEFAULT 0x00000000 13789 13790 13791 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFPFVFDEC1 13792 #define cfgRCC_DEV0_EPF0_VF26_RCC_ERR_LOG_DEFAULT 0x00000000 13793 #define cfgRCC_DEV0_EPF0_VF26_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 13794 #define cfgRCC_DEV0_EPF0_VF26_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 13795 #define cfgRCC_DEV0_EPF0_VF26_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 13796 #define cfgRCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 13797 13798 13799 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_BIFPFVFDEC1 13800 #define cfgBIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS_DEFAULT 0x00000000 13801 #define cfgBIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 13802 #define cfgBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 13803 #define cfgBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 13804 #define cfgBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 13805 #define cfgBIF_BX_DEV0_EPF0_VF26_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13806 #define cfgBIF_BX_DEV0_EPF0_VF26_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13807 #define cfgBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 13808 #define cfgBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 13809 #define cfgBIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING_DEFAULT 0x00000000 13810 #define cfgBIF_BX_DEV0_EPF0_VF26_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 13811 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 13812 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 13813 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 13814 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 13815 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 13816 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 13817 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 13818 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 13819 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL_DEFAULT 0x00000000 13820 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL_DEFAULT 0x00000000 13821 #define cfgBIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 13822 13823 13824 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFDEC2 13825 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 13826 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 13827 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 13828 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 13829 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 13830 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 13831 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 13832 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 13833 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 13834 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 13835 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 13836 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 13837 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 13838 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 13839 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 13840 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 13841 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_PBA_DEFAULT 0x00000000 13842 13843 13844 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_SYSPFVFDEC 13845 #define cfgBIF_BX_DEV0_EPF0_VF27_MM_INDEX_DEFAULT 0x00000000 13846 #define cfgBIF_BX_DEV0_EPF0_VF27_MM_DATA_DEFAULT 0x00000000 13847 #define cfgBIF_BX_DEV0_EPF0_VF27_MM_INDEX_HI_DEFAULT 0x00000000 13848 13849 13850 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFPFVFDEC1 13851 #define cfgRCC_DEV0_EPF0_VF27_RCC_ERR_LOG_DEFAULT 0x00000000 13852 #define cfgRCC_DEV0_EPF0_VF27_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 13853 #define cfgRCC_DEV0_EPF0_VF27_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 13854 #define cfgRCC_DEV0_EPF0_VF27_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 13855 #define cfgRCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 13856 13857 13858 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_BIFPFVFDEC1 13859 #define cfgBIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS_DEFAULT 0x00000000 13860 #define cfgBIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 13861 #define cfgBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 13862 #define cfgBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 13863 #define cfgBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 13864 #define cfgBIF_BX_DEV0_EPF0_VF27_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13865 #define cfgBIF_BX_DEV0_EPF0_VF27_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13866 #define cfgBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 13867 #define cfgBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 13868 #define cfgBIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING_DEFAULT 0x00000000 13869 #define cfgBIF_BX_DEV0_EPF0_VF27_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 13870 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 13871 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 13872 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 13873 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 13874 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 13875 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 13876 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 13877 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 13878 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL_DEFAULT 0x00000000 13879 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL_DEFAULT 0x00000000 13880 #define cfgBIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 13881 13882 13883 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFDEC2 13884 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 13885 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 13886 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 13887 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 13888 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 13889 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 13890 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 13891 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 13892 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 13893 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 13894 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 13895 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 13896 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 13897 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 13898 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 13899 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 13900 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_PBA_DEFAULT 0x00000000 13901 13902 13903 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_SYSPFVFDEC 13904 #define cfgBIF_BX_DEV0_EPF0_VF28_MM_INDEX_DEFAULT 0x00000000 13905 #define cfgBIF_BX_DEV0_EPF0_VF28_MM_DATA_DEFAULT 0x00000000 13906 #define cfgBIF_BX_DEV0_EPF0_VF28_MM_INDEX_HI_DEFAULT 0x00000000 13907 13908 13909 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFPFVFDEC1 13910 #define cfgRCC_DEV0_EPF0_VF28_RCC_ERR_LOG_DEFAULT 0x00000000 13911 #define cfgRCC_DEV0_EPF0_VF28_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 13912 #define cfgRCC_DEV0_EPF0_VF28_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 13913 #define cfgRCC_DEV0_EPF0_VF28_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 13914 #define cfgRCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 13915 13916 13917 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_BIFPFVFDEC1 13918 #define cfgBIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS_DEFAULT 0x00000000 13919 #define cfgBIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 13920 #define cfgBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 13921 #define cfgBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 13922 #define cfgBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 13923 #define cfgBIF_BX_DEV0_EPF0_VF28_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13924 #define cfgBIF_BX_DEV0_EPF0_VF28_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13925 #define cfgBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 13926 #define cfgBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 13927 #define cfgBIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING_DEFAULT 0x00000000 13928 #define cfgBIF_BX_DEV0_EPF0_VF28_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 13929 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 13930 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 13931 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 13932 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 13933 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 13934 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 13935 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 13936 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 13937 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL_DEFAULT 0x00000000 13938 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL_DEFAULT 0x00000000 13939 #define cfgBIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 13940 13941 13942 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFDEC2 13943 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 13944 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 13945 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 13946 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 13947 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 13948 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 13949 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 13950 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 13951 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 13952 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 13953 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 13954 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 13955 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 13956 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 13957 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 13958 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 13959 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_PBA_DEFAULT 0x00000000 13960 13961 13962 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_SYSPFVFDEC 13963 #define cfgBIF_BX_DEV0_EPF0_VF29_MM_INDEX_DEFAULT 0x00000000 13964 #define cfgBIF_BX_DEV0_EPF0_VF29_MM_DATA_DEFAULT 0x00000000 13965 #define cfgBIF_BX_DEV0_EPF0_VF29_MM_INDEX_HI_DEFAULT 0x00000000 13966 13967 13968 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFPFVFDEC1 13969 #define cfgRCC_DEV0_EPF0_VF29_RCC_ERR_LOG_DEFAULT 0x00000000 13970 #define cfgRCC_DEV0_EPF0_VF29_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 13971 #define cfgRCC_DEV0_EPF0_VF29_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 13972 #define cfgRCC_DEV0_EPF0_VF29_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 13973 #define cfgRCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 13974 13975 13976 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_BIFPFVFDEC1 13977 #define cfgBIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS_DEFAULT 0x00000000 13978 #define cfgBIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 13979 #define cfgBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 13980 #define cfgBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 13981 #define cfgBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 13982 #define cfgBIF_BX_DEV0_EPF0_VF29_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13983 #define cfgBIF_BX_DEV0_EPF0_VF29_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 13984 #define cfgBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 13985 #define cfgBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 13986 #define cfgBIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING_DEFAULT 0x00000000 13987 #define cfgBIF_BX_DEV0_EPF0_VF29_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 13988 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 13989 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 13990 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 13991 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 13992 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 13993 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 13994 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 13995 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 13996 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL_DEFAULT 0x00000000 13997 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL_DEFAULT 0x00000000 13998 #define cfgBIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 13999 14000 14001 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFDEC2 14002 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 14003 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 14004 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 14005 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 14006 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 14007 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 14008 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 14009 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 14010 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 14011 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 14012 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 14013 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 14014 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 14015 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 14016 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 14017 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 14018 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_PBA_DEFAULT 0x00000000 14019 14020 14021 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_SYSPFVFDEC 14022 #define cfgBIF_BX_DEV0_EPF0_VF30_MM_INDEX_DEFAULT 0x00000000 14023 #define cfgBIF_BX_DEV0_EPF0_VF30_MM_DATA_DEFAULT 0x00000000 14024 #define cfgBIF_BX_DEV0_EPF0_VF30_MM_INDEX_HI_DEFAULT 0x00000000 14025 14026 14027 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFPFVFDEC1 14028 #define cfgRCC_DEV0_EPF0_VF30_RCC_ERR_LOG_DEFAULT 0x00000000 14029 #define cfgRCC_DEV0_EPF0_VF30_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 14030 #define cfgRCC_DEV0_EPF0_VF30_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 14031 #define cfgRCC_DEV0_EPF0_VF30_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 14032 #define cfgRCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 14033 14034 14035 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_BIFPFVFDEC1 14036 #define cfgBIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS_DEFAULT 0x00000000 14037 #define cfgBIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 14038 #define cfgBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 14039 #define cfgBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 14040 #define cfgBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 14041 #define cfgBIF_BX_DEV0_EPF0_VF30_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 14042 #define cfgBIF_BX_DEV0_EPF0_VF30_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 14043 #define cfgBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 14044 #define cfgBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 14045 #define cfgBIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING_DEFAULT 0x00000000 14046 #define cfgBIF_BX_DEV0_EPF0_VF30_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 14047 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 14048 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 14049 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 14050 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 14051 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 14052 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 14053 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 14054 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 14055 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL_DEFAULT 0x00000000 14056 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL_DEFAULT 0x00000000 14057 #define cfgBIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 14058 14059 14060 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFDEC2 14061 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 14062 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 14063 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 14064 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 14065 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 14066 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 14067 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 14068 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 14069 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 14070 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 14071 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 14072 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 14073 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 14074 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 14075 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 14076 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 14077 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_PBA_DEFAULT 0x00000000 14078 14079 14080 // addressBlock: nbio_pcie0_pswuscfg0_cfgdecp 14081 #define cfgPSWUSCFG0_1_VENDOR_ID_DEFAULT 0x00000000 14082 #define cfgPSWUSCFG0_1_DEVICE_ID_DEFAULT 0x00000000 14083 #define cfgPSWUSCFG0_1_COMMAND_DEFAULT 0x00000000 14084 #define cfgPSWUSCFG0_1_STATUS_DEFAULT 0x00000000 14085 #define cfgPSWUSCFG0_1_REVISION_ID_DEFAULT 0x00000000 14086 #define cfgPSWUSCFG0_1_PROG_INTERFACE_DEFAULT 0x00000000 14087 #define cfgPSWUSCFG0_1_SUB_CLASS_DEFAULT 0x00000000 14088 #define cfgPSWUSCFG0_1_BASE_CLASS_DEFAULT 0x00000000 14089 #define cfgPSWUSCFG0_1_CACHE_LINE_DEFAULT 0x00000000 14090 #define cfgPSWUSCFG0_1_LATENCY_DEFAULT 0x00000000 14091 #define cfgPSWUSCFG0_1_HEADER_DEFAULT 0x00000000 14092 #define cfgPSWUSCFG0_1_BIST_DEFAULT 0x00000000 14093 #define cfgPSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 14094 #define cfgPSWUSCFG0_1_IO_BASE_LIMIT_DEFAULT 0x00000000 14095 #define cfgPSWUSCFG0_1_SECONDARY_STATUS_DEFAULT 0x00000000 14096 #define cfgPSWUSCFG0_1_MEM_BASE_LIMIT_DEFAULT 0x00000000 14097 #define cfgPSWUSCFG0_1_PREF_BASE_LIMIT_DEFAULT 0x00000000 14098 #define cfgPSWUSCFG0_1_PREF_BASE_UPPER_DEFAULT 0x00000000 14099 #define cfgPSWUSCFG0_1_PREF_LIMIT_UPPER_DEFAULT 0x00000000 14100 #define cfgPSWUSCFG0_1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 14101 #define cfgPSWUSCFG0_1_CAP_PTR_DEFAULT 0x00000000 14102 #define cfgPSWUSCFG0_1_ROM_BASE_ADDR_DEFAULT 0x00000000 14103 #define cfgPSWUSCFG0_1_INTERRUPT_LINE_DEFAULT 0x000000ff 14104 #define cfgPSWUSCFG0_1_INTERRUPT_PIN_DEFAULT 0x00000000 14105 #define cfgPSWUSCFG0_1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 14106 #define cfgPSWUSCFG0_1_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 14107 #define cfgPSWUSCFG0_1_VENDOR_CAP_LIST_DEFAULT 0x00000000 14108 #define cfgPSWUSCFG0_1_ADAPTER_ID_W_DEFAULT 0x00000000 14109 #define cfgPSWUSCFG0_1_PMI_CAP_LIST_DEFAULT 0x00000000 14110 #define cfgPSWUSCFG0_1_PMI_CAP_DEFAULT 0x00000000 14111 #define cfgPSWUSCFG0_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 14112 #define cfgPSWUSCFG0_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 14113 #define cfgPSWUSCFG0_1_PCIE_CAP_DEFAULT 0x00000002 14114 #define cfgPSWUSCFG0_1_DEVICE_CAP_DEFAULT 0x00000000 14115 #define cfgPSWUSCFG0_1_DEVICE_CNTL_DEFAULT 0x00002910 14116 #define cfgPSWUSCFG0_1_DEVICE_STATUS_DEFAULT 0x00000000 14117 #define cfgPSWUSCFG0_1_LINK_CAP_DEFAULT 0x00011c04 14118 #define cfgPSWUSCFG0_1_LINK_CNTL_DEFAULT 0x00000000 14119 #define cfgPSWUSCFG0_1_LINK_STATUS_DEFAULT 0x00000001 14120 #define cfgPSWUSCFG0_1_DEVICE_CAP2_DEFAULT 0x00000000 14121 #define cfgPSWUSCFG0_1_DEVICE_CNTL2_DEFAULT 0x00000000 14122 #define cfgPSWUSCFG0_1_DEVICE_STATUS2_DEFAULT 0x00000000 14123 #define cfgPSWUSCFG0_1_LINK_CAP2_DEFAULT 0x0000001e 14124 #define cfgPSWUSCFG0_1_LINK_CNTL2_DEFAULT 0x00000004 14125 #define cfgPSWUSCFG0_1_LINK_STATUS2_DEFAULT 0x00000000 14126 #define cfgPSWUSCFG0_1_MSI_CAP_LIST_DEFAULT 0x0000c000 14127 #define cfgPSWUSCFG0_1_MSI_MSG_CNTL_DEFAULT 0x00000000 14128 #define cfgPSWUSCFG0_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 14129 #define cfgPSWUSCFG0_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 14130 #define cfgPSWUSCFG0_1_MSI_MSG_DATA_DEFAULT 0x00000000 14131 #define cfgPSWUSCFG0_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 14132 #define cfgPSWUSCFG0_1_SSID_CAP_LIST_DEFAULT 0x0000c800 14133 #define cfgPSWUSCFG0_1_SSID_CAP_DEFAULT 0x00000000 14134 #define cfgPSWUSCFG0_1_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 14135 #define cfgPSWUSCFG0_1_MSI_MAP_CAP_DEFAULT 0x00000000 14136 #define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 14137 #define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 14138 #define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 14139 #define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 14140 #define cfgPSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 14141 #define cfgPSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 14142 #define cfgPSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 14143 #define cfgPSWUSCFG0_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 14144 #define cfgPSWUSCFG0_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 14145 #define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 14146 #define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe 14147 #define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 14148 #define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 14149 #define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 14150 #define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 14151 #define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 14152 #define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 14153 #define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 14154 #define cfgPSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 14155 #define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 14156 #define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x04400000 14157 #define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 14158 #define cfgPSWUSCFG0_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 14159 #define cfgPSWUSCFG0_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 14160 #define cfgPSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 14161 #define cfgPSWUSCFG0_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 14162 #define cfgPSWUSCFG0_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 14163 #define cfgPSWUSCFG0_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 14164 #define cfgPSWUSCFG0_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 14165 #define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 14166 #define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 14167 #define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 14168 #define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 14169 #define cfgPSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 14170 #define cfgPSWUSCFG0_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 14171 #define cfgPSWUSCFG0_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 14172 #define cfgPSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14173 #define cfgPSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14174 #define cfgPSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14175 #define cfgPSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14176 #define cfgPSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14177 #define cfgPSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14178 #define cfgPSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14179 #define cfgPSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14180 #define cfgPSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14181 #define cfgPSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14182 #define cfgPSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14183 #define cfgPSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14184 #define cfgPSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14185 #define cfgPSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14186 #define cfgPSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14187 #define cfgPSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14188 #define cfgPSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 14189 #define cfgPSWUSCFG0_1_PCIE_ACS_CAP_DEFAULT 0x00000000 14190 #define cfgPSWUSCFG0_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 14191 #define cfgPSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 14192 #define cfgPSWUSCFG0_1_PCIE_MC_CAP_DEFAULT 0x00000000 14193 #define cfgPSWUSCFG0_1_PCIE_MC_CNTL_DEFAULT 0x00000000 14194 #define cfgPSWUSCFG0_1_PCIE_MC_ADDR0_DEFAULT 0x00000000 14195 #define cfgPSWUSCFG0_1_PCIE_MC_ADDR1_DEFAULT 0x00000000 14196 #define cfgPSWUSCFG0_1_PCIE_MC_RCV0_DEFAULT 0x00000000 14197 #define cfgPSWUSCFG0_1_PCIE_MC_RCV1_DEFAULT 0x00000000 14198 #define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 14199 #define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 14200 #define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 14201 #define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 14202 #define cfgPSWUSCFG0_1_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 14203 #define cfgPSWUSCFG0_1_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 14204 #define cfgPSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 14205 #define cfgPSWUSCFG0_1_PCIE_LTR_CAP_DEFAULT 0x00000000 14206 #define cfgPSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x38000000 14207 #define cfgPSWUSCFG0_1_PCIE_ARI_CAP_DEFAULT 0x00000000 14208 #define cfgPSWUSCFG0_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 14209 #define cfgPSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x3c400000 14210 #define cfgPSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 14211 #define cfgPSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 14212 #define cfgPSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 14213 #define cfgPSWUSCFG0_1_PCIE_ESM_CAP_LIST_DEFAULT 0x40000000 14214 #define cfgPSWUSCFG0_1_PCIE_ESM_HEADER_1_DEFAULT 0x00000000 14215 #define cfgPSWUSCFG0_1_PCIE_ESM_HEADER_2_DEFAULT 0x00000000 14216 #define cfgPSWUSCFG0_1_PCIE_ESM_STATUS_DEFAULT 0x00000000 14217 #define cfgPSWUSCFG0_1_PCIE_ESM_CTRL_DEFAULT 0x00000000 14218 #define cfgPSWUSCFG0_1_PCIE_ESM_CAP_1_DEFAULT 0x00000000 14219 #define cfgPSWUSCFG0_1_PCIE_ESM_CAP_2_DEFAULT 0x00000000 14220 #define cfgPSWUSCFG0_1_PCIE_ESM_CAP_3_DEFAULT 0x00000000 14221 #define cfgPSWUSCFG0_1_PCIE_ESM_CAP_4_DEFAULT 0x00000000 14222 #define cfgPSWUSCFG0_1_PCIE_ESM_CAP_5_DEFAULT 0x00000000 14223 #define cfgPSWUSCFG0_1_PCIE_ESM_CAP_6_DEFAULT 0x00000000 14224 #define cfgPSWUSCFG0_1_PCIE_ESM_CAP_7_DEFAULT 0x00000000 14225 #define cfgPSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41000000 14226 #define cfgPSWUSCFG0_1_DATA_LINK_FEATURE_CAP_DEFAULT 0x80000001 14227 #define cfgPSWUSCFG0_1_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000 14228 #define cfgPSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44000000 14229 #define cfgPSWUSCFG0_1_LINK_CAP_16GT_DEFAULT 0x00000000 14230 #define cfgPSWUSCFG0_1_LINK_CNTL_16GT_DEFAULT 0x00000000 14231 #define cfgPSWUSCFG0_1_LINK_STATUS_16GT_DEFAULT 0x00000000 14232 #define cfgPSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 14233 #define cfgPSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 14234 #define cfgPSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 14235 #define cfgPSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 14236 #define cfgPSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 14237 #define cfgPSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 14238 #define cfgPSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 14239 #define cfgPSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 14240 #define cfgPSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 14241 #define cfgPSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 14242 #define cfgPSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 14243 #define cfgPSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 14244 #define cfgPSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 14245 #define cfgPSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 14246 #define cfgPSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 14247 #define cfgPSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 14248 #define cfgPSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 14249 #define cfgPSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 14250 #define cfgPSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000ff 14251 #define cfgPSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x00000000 14252 #define cfgPSWUSCFG0_1_MARGINING_PORT_CAP_DEFAULT 0x00000000 14253 #define cfgPSWUSCFG0_1_MARGINING_PORT_STATUS_DEFAULT 0x00000000 14254 #define cfgPSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14255 #define cfgPSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14256 #define cfgPSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14257 #define cfgPSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14258 #define cfgPSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14259 #define cfgPSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14260 #define cfgPSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14261 #define cfgPSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14262 #define cfgPSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14263 #define cfgPSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14264 #define cfgPSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14265 #define cfgPSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14266 #define cfgPSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14267 #define cfgPSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14268 #define cfgPSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14269 #define cfgPSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14270 #define cfgPSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14271 #define cfgPSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14272 #define cfgPSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14273 #define cfgPSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14274 #define cfgPSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14275 #define cfgPSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14276 #define cfgPSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14277 #define cfgPSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14278 #define cfgPSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14279 #define cfgPSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14280 #define cfgPSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14281 #define cfgPSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14282 #define cfgPSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14283 #define cfgPSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14284 #define cfgPSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14285 #define cfgPSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14286 #define cfgPSWUSCFG0_1_PCIE_CCIX_CAP_LIST_DEFAULT 0x00000000 14287 #define cfgPSWUSCFG0_1_PCIE_CCIX_HEADER_1_DEFAULT 0x00000000 14288 #define cfgPSWUSCFG0_1_PCIE_CCIX_HEADER_2_DEFAULT 0x00000000 14289 #define cfgPSWUSCFG0_1_PCIE_CCIX_CAP_DEFAULT 0x00000000 14290 #define cfgPSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP_DEFAULT 0x00000000 14291 #define cfgPSWUSCFG0_1_PCIE_CCIX_ESM_OPTL_CAP_DEFAULT 0x00000000 14292 #define cfgPSWUSCFG0_1_PCIE_CCIX_ESM_STATUS_DEFAULT 0x00000000 14293 #define cfgPSWUSCFG0_1_PCIE_CCIX_ESM_CNTL_DEFAULT 0x00000000 14294 #define cfgPSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 14295 #define cfgPSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 14296 #define cfgPSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 14297 #define cfgPSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 14298 #define cfgPSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 14299 #define cfgPSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 14300 #define cfgPSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 14301 #define cfgPSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 14302 #define cfgPSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 14303 #define cfgPSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 14304 #define cfgPSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 14305 #define cfgPSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 14306 #define cfgPSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 14307 #define cfgPSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 14308 #define cfgPSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 14309 #define cfgPSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT_DEFAULT 0x000000ff 14310 #define cfgPSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 14311 #define cfgPSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 14312 #define cfgPSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 14313 #define cfgPSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 14314 #define cfgPSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 14315 #define cfgPSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 14316 #define cfgPSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 14317 #define cfgPSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 14318 #define cfgPSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 14319 #define cfgPSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 14320 #define cfgPSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 14321 #define cfgPSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 14322 #define cfgPSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 14323 #define cfgPSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 14324 #define cfgPSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 14325 #define cfgPSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT_DEFAULT 0x000000ff 14326 #define cfgPSWUSCFG0_1_PCIE_CCIX_TRANS_CAP_DEFAULT 0x00000000 14327 #define cfgPSWUSCFG0_1_PCIE_CCIX_TRANS_CNTL_DEFAULT 0x00000000 14328 14329 14330 // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC:1 14331 #define cfgBIF_BX_PF0_MM_INDEX_DEFAULT 0x00000000 14332 #define cfgBIF_BX_PF0_MM_DATA_DEFAULT 0x00000000 14333 #define cfgBIF_BX_PF0_MM_INDEX_HI_DEFAULT 0x00000000 14334 14335 14336 // addressBlock: nbio_nbif0_bif_swus_SUMDEC 14337 #define cfgSUM_INDEX_DEFAULT 0x00000000 14338 #define cfgSUM_DATA_DEFAULT 0x00000000 14339 14340 14341 // addressBlock: nbio_nbif0_bif_cfg_dev0_swds_bifcfgdecp 14342 #define cfgBIF_CFG_DEV0_SWDS1_VENDOR_ID_DEFAULT 0x00001002 14343 #define cfgBIF_CFG_DEV0_SWDS1_DEVICE_ID_DEFAULT 0x00000000 14344 #define cfgBIF_CFG_DEV0_SWDS1_COMMAND_DEFAULT 0x00000000 14345 #define cfgBIF_CFG_DEV0_SWDS1_STATUS_DEFAULT 0x00000000 14346 #define cfgBIF_CFG_DEV0_SWDS1_REVISION_ID_DEFAULT 0x00000000 14347 #define cfgBIF_CFG_DEV0_SWDS1_PROG_INTERFACE_DEFAULT 0x00000000 14348 #define cfgBIF_CFG_DEV0_SWDS1_SUB_CLASS_DEFAULT 0x00000004 14349 #define cfgBIF_CFG_DEV0_SWDS1_BASE_CLASS_DEFAULT 0x00000006 14350 #define cfgBIF_CFG_DEV0_SWDS1_CACHE_LINE_DEFAULT 0x00000000 14351 #define cfgBIF_CFG_DEV0_SWDS1_LATENCY_DEFAULT 0x00000000 14352 #define cfgBIF_CFG_DEV0_SWDS1_HEADER_DEFAULT 0x00000000 14353 #define cfgBIF_CFG_DEV0_SWDS1_BIST_DEFAULT 0x00000000 14354 #define cfgBIF_CFG_DEV0_SWDS1_BASE_ADDR_1_DEFAULT 0x00000000 14355 #define cfgBIF_CFG_DEV0_SWDS1_BASE_ADDR_2_DEFAULT 0x00000000 14356 #define cfgBIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 14357 #define cfgBIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_DEFAULT 0x00000000 14358 #define cfgBIF_CFG_DEV0_SWDS1_SECONDARY_STATUS_DEFAULT 0x00000000 14359 #define cfgBIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT_DEFAULT 0x00000000 14360 #define cfgBIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT_DEFAULT 0x00000000 14361 #define cfgBIF_CFG_DEV0_SWDS1_PREF_BASE_UPPER_DEFAULT 0x00000000 14362 #define cfgBIF_CFG_DEV0_SWDS1_PREF_LIMIT_UPPER_DEFAULT 0x00000000 14363 #define cfgBIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 14364 #define cfgBIF_CFG_DEV0_SWDS1_CAP_PTR_DEFAULT 0x00000000 14365 #define cfgBIF_CFG_DEV0_SWDS1_ROM_BASE_ADDR_DEFAULT 0x00000000 14366 #define cfgBIF_CFG_DEV0_SWDS1_INTERRUPT_LINE_DEFAULT 0x000000ff 14367 #define cfgBIF_CFG_DEV0_SWDS1_INTERRUPT_PIN_DEFAULT 0x00000000 14368 #define cfgBIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 14369 #define cfgBIF_CFG_DEV0_SWDS1_PMI_CAP_LIST_DEFAULT 0x00000000 14370 #define cfgBIF_CFG_DEV0_SWDS1_PMI_CAP_DEFAULT 0x0000c800 14371 #define cfgBIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL_DEFAULT 0x00000000 14372 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST_DEFAULT 0x0000a000 14373 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_CAP_DEFAULT 0x00000062 14374 #define cfgBIF_CFG_DEV0_SWDS1_DEVICE_CAP_DEFAULT 0x00000000 14375 #define cfgBIF_CFG_DEV0_SWDS1_DEVICE_CNTL_DEFAULT 0x00002810 14376 #define cfgBIF_CFG_DEV0_SWDS1_DEVICE_STATUS_DEFAULT 0x00000000 14377 #define cfgBIF_CFG_DEV0_SWDS1_LINK_CAP_DEFAULT 0x00000d04 14378 #define cfgBIF_CFG_DEV0_SWDS1_LINK_CNTL_DEFAULT 0x00000000 14379 #define cfgBIF_CFG_DEV0_SWDS1_LINK_STATUS_DEFAULT 0x00002001 14380 #define cfgBIF_CFG_DEV0_SWDS1_SLOT_CAP_DEFAULT 0x00000000 14381 #define cfgBIF_CFG_DEV0_SWDS1_SLOT_CNTL_DEFAULT 0x00000000 14382 #define cfgBIF_CFG_DEV0_SWDS1_SLOT_STATUS_DEFAULT 0x00000000 14383 #define cfgBIF_CFG_DEV0_SWDS1_DEVICE_CAP2_DEFAULT 0x00010000 14384 #define cfgBIF_CFG_DEV0_SWDS1_DEVICE_CNTL2_DEFAULT 0x00000000 14385 #define cfgBIF_CFG_DEV0_SWDS1_DEVICE_STATUS2_DEFAULT 0x00000000 14386 #define cfgBIF_CFG_DEV0_SWDS1_LINK_CAP2_DEFAULT 0x0000001e 14387 #define cfgBIF_CFG_DEV0_SWDS1_LINK_CNTL2_DEFAULT 0x00000004 14388 #define cfgBIF_CFG_DEV0_SWDS1_LINK_STATUS2_DEFAULT 0x00000000 14389 #define cfgBIF_CFG_DEV0_SWDS1_SLOT_CAP2_DEFAULT 0x00000000 14390 #define cfgBIF_CFG_DEV0_SWDS1_SLOT_CNTL2_DEFAULT 0x00000000 14391 #define cfgBIF_CFG_DEV0_SWDS1_SLOT_STATUS2_DEFAULT 0x00000000 14392 #define cfgBIF_CFG_DEV0_SWDS1_MSI_CAP_LIST_DEFAULT 0x0000c000 14393 #define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL_DEFAULT 0x00000080 14394 #define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 14395 #define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 14396 #define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_DEFAULT 0x00000000 14397 #define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_64_DEFAULT 0x00000000 14398 #define cfgBIF_CFG_DEV0_SWDS1_SSID_CAP_LIST_DEFAULT 0x00000000 14399 #define cfgBIF_CFG_DEV0_SWDS1_SSID_CAP_DEFAULT 0x00000000 14400 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 14401 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 14402 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 14403 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 14404 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 14405 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 14406 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 14407 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 14408 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 14409 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 14410 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe 14411 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 14412 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 14413 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 14414 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 14415 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 14416 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 14417 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 14418 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 14419 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 14420 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 14421 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 14422 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 14423 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 14424 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 14425 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG0_DEFAULT 0x00000000 14426 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG1_DEFAULT 0x00000000 14427 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG2_DEFAULT 0x00000000 14428 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG3_DEFAULT 0x00000000 14429 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 14430 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 14431 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 14432 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 14433 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 14434 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 14435 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 14436 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14437 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14438 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14439 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14440 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14441 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14442 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14443 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14444 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14445 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14446 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14447 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14448 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14449 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14450 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14451 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f 14452 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 14453 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP_DEFAULT 0x00000000 14454 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL_DEFAULT 0x00000000 14455 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41000000 14456 #define cfgBIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_CAP_DEFAULT 0x00000001 14457 #define cfgBIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000 14458 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44000000 14459 #define cfgBIF_CFG_DEV0_SWDS1_LINK_CAP_16GT_DEFAULT 0x00000000 14460 #define cfgBIF_CFG_DEV0_SWDS1_LINK_CNTL_16GT_DEFAULT 0x00000000 14461 #define cfgBIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT_DEFAULT 0x00000000 14462 #define cfgBIF_CFG_DEV0_SWDS1_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 14463 #define cfgBIF_CFG_DEV0_SWDS1_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 14464 #define cfgBIF_CFG_DEV0_SWDS1_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 14465 #define cfgBIF_CFG_DEV0_SWDS1_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 14466 #define cfgBIF_CFG_DEV0_SWDS1_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 14467 #define cfgBIF_CFG_DEV0_SWDS1_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 14468 #define cfgBIF_CFG_DEV0_SWDS1_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 14469 #define cfgBIF_CFG_DEV0_SWDS1_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 14470 #define cfgBIF_CFG_DEV0_SWDS1_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 14471 #define cfgBIF_CFG_DEV0_SWDS1_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 14472 #define cfgBIF_CFG_DEV0_SWDS1_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 14473 #define cfgBIF_CFG_DEV0_SWDS1_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 14474 #define cfgBIF_CFG_DEV0_SWDS1_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 14475 #define cfgBIF_CFG_DEV0_SWDS1_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 14476 #define cfgBIF_CFG_DEV0_SWDS1_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 14477 #define cfgBIF_CFG_DEV0_SWDS1_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 14478 #define cfgBIF_CFG_DEV0_SWDS1_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 14479 #define cfgBIF_CFG_DEV0_SWDS1_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 14480 #define cfgBIF_CFG_DEV0_SWDS1_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x00000000 14481 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x4c000000 14482 #define cfgBIF_CFG_DEV0_SWDS1_MARGINING_PORT_CAP_DEFAULT 0x00000000 14483 #define cfgBIF_CFG_DEV0_SWDS1_MARGINING_PORT_STATUS_DEFAULT 0x00000000 14484 #define cfgBIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14485 #define cfgBIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14486 #define cfgBIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14487 #define cfgBIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14488 #define cfgBIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14489 #define cfgBIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14490 #define cfgBIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14491 #define cfgBIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14492 #define cfgBIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14493 #define cfgBIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14494 #define cfgBIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14495 #define cfgBIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14496 #define cfgBIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14497 #define cfgBIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14498 #define cfgBIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14499 #define cfgBIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14500 #define cfgBIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14501 #define cfgBIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14502 #define cfgBIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14503 #define cfgBIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14504 #define cfgBIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14505 #define cfgBIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14506 #define cfgBIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14507 #define cfgBIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14508 #define cfgBIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14509 #define cfgBIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14510 #define cfgBIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14511 #define cfgBIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14512 #define cfgBIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14513 #define cfgBIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14514 #define cfgBIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14515 #define cfgBIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14516 14517 14518 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp 14519 #define cfgBIF_CFG_DEV0_EPF0_1_VENDOR_ID_DEFAULT 0x00001002 14520 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_ID_DEFAULT 0x00007310 14521 #define cfgBIF_CFG_DEV0_EPF0_1_COMMAND_DEFAULT 0x00000000 14522 #define cfgBIF_CFG_DEV0_EPF0_1_STATUS_DEFAULT 0x00000000 14523 #define cfgBIF_CFG_DEV0_EPF0_1_REVISION_ID_DEFAULT 0x00000000 14524 #define cfgBIF_CFG_DEV0_EPF0_1_PROG_INTERFACE_DEFAULT 0x00000000 14525 #define cfgBIF_CFG_DEV0_EPF0_1_SUB_CLASS_DEFAULT 0x00000000 14526 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_CLASS_DEFAULT 0x00000000 14527 #define cfgBIF_CFG_DEV0_EPF0_1_CACHE_LINE_DEFAULT 0x00000000 14528 #define cfgBIF_CFG_DEV0_EPF0_1_LATENCY_DEFAULT 0x00000000 14529 #define cfgBIF_CFG_DEV0_EPF0_1_HEADER_DEFAULT 0x00000080 14530 #define cfgBIF_CFG_DEV0_EPF0_1_BIST_DEFAULT 0x00000000 14531 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_1_DEFAULT 0x00000000 14532 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_2_DEFAULT 0x00000000 14533 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_3_DEFAULT 0x00000000 14534 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_4_DEFAULT 0x00000000 14535 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_5_DEFAULT 0x00000000 14536 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_6_DEFAULT 0x00000000 14537 #define cfgBIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 14538 #define cfgBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_DEFAULT 0x73101002 14539 #define cfgBIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR_DEFAULT 0x00000000 14540 #define cfgBIF_CFG_DEV0_EPF0_1_CAP_PTR_DEFAULT 0x00000048 14541 #define cfgBIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE_DEFAULT 0x000000ff 14542 #define cfgBIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN_DEFAULT 0x00000001 14543 #define cfgBIF_CFG_DEV0_EPF0_1_MIN_GRANT_DEFAULT 0x00000000 14544 #define cfgBIF_CFG_DEV0_EPF0_1_MAX_LATENCY_DEFAULT 0x00000000 14545 #define cfgBIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST_DEFAULT 0x00000000 14546 #define cfgBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W_DEFAULT 0x73101002 14547 #define cfgBIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST_DEFAULT 0x00006400 14548 #define cfgBIF_CFG_DEV0_EPF0_1_PMI_CAP_DEFAULT 0x0000f000 14549 #define cfgBIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 14550 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 14551 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CAP_DEFAULT 0x00000012 14552 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CAP_DEFAULT 0x00000f81 14553 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL_DEFAULT 0x00002810 14554 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS_DEFAULT 0x00000000 14555 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP_DEFAULT 0x00000d04 14556 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL_DEFAULT 0x00000000 14557 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS_DEFAULT 0x00000001 14558 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CAP2_DEFAULT 0x00010000 14559 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2_DEFAULT 0x00000000 14560 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2_DEFAULT 0x00000000 14561 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP2_DEFAULT 0x0000001e 14562 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL2_DEFAULT 0x00000004 14563 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS2_DEFAULT 0x00000001 14564 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST_DEFAULT 0x0000c000 14565 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL_DEFAULT 0x00000084 14566 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 14567 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 14568 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_DEFAULT 0x00000000 14569 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MASK_DEFAULT 0x00000000 14570 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 14571 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MASK_64_DEFAULT 0x00000000 14572 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_PENDING_DEFAULT 0x00000000 14573 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_PENDING_64_DEFAULT 0x00000000 14574 #define cfgBIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST_DEFAULT 0x00000000 14575 #define cfgBIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 14576 #define cfgBIF_CFG_DEV0_EPF0_1_MSIX_TABLE_DEFAULT 0x00000000 14577 #define cfgBIF_CFG_DEV0_EPF0_1_MSIX_PBA_DEFAULT 0x00000000 14578 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 14579 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 14580 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 14581 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 14582 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 14583 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 14584 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 14585 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 14586 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 14587 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 14588 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe 14589 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 14590 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 14591 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 14592 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 14593 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 14594 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 14595 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 14596 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 14597 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 14598 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 14599 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 14600 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 14601 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 14602 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 14603 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 14604 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 14605 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 14606 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 14607 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 14608 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 14609 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 14610 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 14611 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 14612 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP_DEFAULT 0x00000000 14613 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020 14614 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP_DEFAULT 0x00000000 14615 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000 14616 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP_DEFAULT 0x00000000 14617 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000 14618 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP_DEFAULT 0x00000000 14619 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000 14620 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP_DEFAULT 0x00000000 14621 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 14622 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP_DEFAULT 0x00000000 14623 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000 14624 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 14625 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 14626 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 14627 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 14628 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 14629 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP_DEFAULT 0x00000000 14630 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 14631 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS_DEFAULT 0x00000100 14632 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL_DEFAULT 0x00000000 14633 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 14634 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 14635 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 14636 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 14637 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 14638 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 14639 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 14640 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 14641 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 14642 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 14643 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 14644 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 14645 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 14646 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 14647 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 14648 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 14649 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 14650 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 14651 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 14652 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 14653 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 14654 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 14655 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 14656 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 14657 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 14658 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 14659 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 14660 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 14661 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP_DEFAULT 0x00000000 14662 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 14663 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 14664 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP_DEFAULT 0x00000000 14665 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 14666 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000 14667 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 14668 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000100 14669 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000 14670 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 14671 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000 14672 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP_DEFAULT 0x00001000 14673 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL_DEFAULT 0x00000000 14674 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 14675 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP_DEFAULT 0x00000000 14676 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL_DEFAULT 0x00000000 14677 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0_DEFAULT 0x00000000 14678 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1_DEFAULT 0x00000000 14679 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0_DEFAULT 0x00000000 14680 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1_DEFAULT 0x00000000 14681 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 14682 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 14683 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 14684 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 14685 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 14686 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP_DEFAULT 0x00000000 14687 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 14688 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP_DEFAULT 0x00000000 14689 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 14690 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x37000000 14691 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP_DEFAULT 0x00000000 14692 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000 14693 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS_DEFAULT 0x00000000 14694 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000 14695 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000 14696 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000 14697 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000 14698 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000 14699 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000 14700 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000 14701 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000553 14702 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001 14703 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000 14704 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000 14705 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000 14706 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000 14707 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000 14708 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000 14709 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000 14710 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000 14711 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000 14712 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 14713 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41010025 14714 #define cfgBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP_DEFAULT 0x00000001 14715 #define cfgBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000 14716 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44010026 14717 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT_DEFAULT 0x00000000 14718 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT_DEFAULT 0x00000000 14719 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT_DEFAULT 0x00000000 14720 #define cfgBIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 14721 #define cfgBIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 14722 #define cfgBIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 14723 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 14724 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 14725 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 14726 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 14727 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 14728 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 14729 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 14730 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 14731 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 14732 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 14733 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 14734 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 14735 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 14736 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 14737 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 14738 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 14739 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x4c010027 14740 #define cfgBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP_DEFAULT 0x00000000 14741 #define cfgBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS_DEFAULT 0x00000000 14742 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14743 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14744 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14745 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14746 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14747 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14748 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14749 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14750 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14751 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14752 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14753 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14754 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14755 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14756 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14757 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14758 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14759 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14760 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14761 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14762 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14763 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14764 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14765 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14766 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14767 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14768 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14769 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14770 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14771 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14772 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 14773 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000 14774 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_DEFAULT 0x00000000 14775 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP_DEFAULT 0x00000000 14776 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL_DEFAULT 0x00000020 14777 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP_DEFAULT 0x00000000 14778 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL_DEFAULT 0x00000000 14779 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP_DEFAULT 0x00000000 14780 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL_DEFAULT 0x00000000 14781 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP_DEFAULT 0x00000000 14782 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL_DEFAULT 0x00000000 14783 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP_DEFAULT 0x00000000 14784 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL_DEFAULT 0x00000000 14785 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP_DEFAULT 0x00000000 14786 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL_DEFAULT 0x00000000 14787 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000 14788 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000 14789 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000 14790 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000 14791 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000 14792 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000 14793 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000 14794 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000 14795 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000 14796 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000 14797 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000 14798 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x0012000c 14799 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_DEFAULT 0x00000000 14800 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_DEFAULT 0x00000000 14801 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000 14802 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000 14803 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000 14804 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000 14805 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000 14806 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000 14807 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000 14808 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000 14809 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000 14810 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000 14811 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000 14812 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000 14813 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000 14814 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000 14815 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000 14816 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000 14817 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_DEFAULT 0x00000000 14818 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_DEFAULT 0x00000000 14819 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_DEFAULT 0x00000000 14820 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_DEFAULT 0x00000000 14821 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_DEFAULT 0x00000000 14822 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_DEFAULT 0x00000000 14823 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_DEFAULT 0x00000000 14824 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_DEFAULT 0x00000000 14825 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_DEFAULT 0x00000000 14826 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_DEFAULT 0x00000000 14827 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_DEFAULT 0x00000000 14828 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_DEFAULT 0x00000000 14829 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_DEFAULT 0x00000000 14830 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_DEFAULT 0x00000000 14831 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_DEFAULT 0x00000000 14832 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000 14833 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000 14834 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000 14835 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000 14836 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000 14837 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000 14838 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000 14839 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000 14840 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000 14841 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000 14842 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000 14843 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000 14844 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000 14845 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000 14846 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000 14847 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000 14848 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000 14849 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000 14850 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000 14851 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000 14852 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000 14853 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000 14854 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000 14855 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000 14856 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000 14857 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000 14858 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000 14859 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0_DEFAULT 0x00000000 14860 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1_DEFAULT 0x00000000 14861 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2_DEFAULT 0x00000000 14862 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3_DEFAULT 0x00000000 14863 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4_DEFAULT 0x00000000 14864 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5_DEFAULT 0x00000000 14865 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6_DEFAULT 0x00000000 14866 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7_DEFAULT 0x00000000 14867 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8_DEFAULT 0x00000000 14868 14869 14870 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp 14871 #define cfgBIF_CFG_DEV0_EPF1_1_VENDOR_ID_DEFAULT 0x00001002 14872 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_ID_DEFAULT 0x0000ab38 14873 #define cfgBIF_CFG_DEV0_EPF1_1_COMMAND_DEFAULT 0x00000000 14874 #define cfgBIF_CFG_DEV0_EPF1_1_STATUS_DEFAULT 0x00000000 14875 #define cfgBIF_CFG_DEV0_EPF1_1_REVISION_ID_DEFAULT 0x00000000 14876 #define cfgBIF_CFG_DEV0_EPF1_1_PROG_INTERFACE_DEFAULT 0x00000000 14877 #define cfgBIF_CFG_DEV0_EPF1_1_SUB_CLASS_DEFAULT 0x00000000 14878 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_CLASS_DEFAULT 0x00000000 14879 #define cfgBIF_CFG_DEV0_EPF1_1_CACHE_LINE_DEFAULT 0x00000000 14880 #define cfgBIF_CFG_DEV0_EPF1_1_LATENCY_DEFAULT 0x00000000 14881 #define cfgBIF_CFG_DEV0_EPF1_1_HEADER_DEFAULT 0x00000080 14882 #define cfgBIF_CFG_DEV0_EPF1_1_BIST_DEFAULT 0x00000000 14883 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_1_DEFAULT 0x00000000 14884 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_2_DEFAULT 0x00000000 14885 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_3_DEFAULT 0x00000000 14886 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_4_DEFAULT 0x00000000 14887 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_5_DEFAULT 0x00000000 14888 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_6_DEFAULT 0x00000000 14889 #define cfgBIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 14890 #define cfgBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_DEFAULT 0xab381002 14891 #define cfgBIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR_DEFAULT 0x00000000 14892 #define cfgBIF_CFG_DEV0_EPF1_1_CAP_PTR_DEFAULT 0x00000048 14893 #define cfgBIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE_DEFAULT 0x000000ff 14894 #define cfgBIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN_DEFAULT 0x00000002 14895 #define cfgBIF_CFG_DEV0_EPF1_1_MIN_GRANT_DEFAULT 0x00000000 14896 #define cfgBIF_CFG_DEV0_EPF1_1_MAX_LATENCY_DEFAULT 0x00000000 14897 #define cfgBIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST_DEFAULT 0x00000000 14898 #define cfgBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W_DEFAULT 0xab381002 14899 #define cfgBIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST_DEFAULT 0x00006400 14900 #define cfgBIF_CFG_DEV0_EPF1_1_PMI_CAP_DEFAULT 0x0000f000 14901 #define cfgBIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 14902 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 14903 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CAP_DEFAULT 0x00000012 14904 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CAP_DEFAULT 0x00000f81 14905 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL_DEFAULT 0x00002810 14906 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS_DEFAULT 0x00000000 14907 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP_DEFAULT 0x00000d04 14908 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL_DEFAULT 0x00000000 14909 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS_DEFAULT 0x00000001 14910 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CAP2_DEFAULT 0x00010000 14911 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2_DEFAULT 0x00000000 14912 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2_DEFAULT 0x00000000 14913 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP2_DEFAULT 0x0000001e 14914 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL2_DEFAULT 0x00000004 14915 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS2_DEFAULT 0x00000001 14916 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST_DEFAULT 0x0000c000 14917 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL_DEFAULT 0x00000080 14918 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 14919 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 14920 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_DEFAULT 0x00000000 14921 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MASK_DEFAULT 0x00000000 14922 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 14923 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MASK_64_DEFAULT 0x00000000 14924 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_PENDING_DEFAULT 0x00000000 14925 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_PENDING_64_DEFAULT 0x00000000 14926 #define cfgBIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST_DEFAULT 0x00000000 14927 #define cfgBIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 14928 #define cfgBIF_CFG_DEV0_EPF1_1_MSIX_TABLE_DEFAULT 0x00000000 14929 #define cfgBIF_CFG_DEV0_EPF1_1_MSIX_PBA_DEFAULT 0x00000000 14930 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 14931 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 14932 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 14933 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 14934 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 14935 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 14936 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 14937 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 14938 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 14939 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 14940 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe 14941 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 14942 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 14943 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 14944 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 14945 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 14946 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 14947 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 14948 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 14949 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 14950 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 14951 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 14952 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 14953 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 14954 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 14955 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 14956 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 14957 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 14958 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 14959 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 14960 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 14961 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 14962 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 14963 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 14964 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP_DEFAULT 0x00000000 14965 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020 14966 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP_DEFAULT 0x00000000 14967 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000 14968 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP_DEFAULT 0x00000000 14969 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000 14970 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP_DEFAULT 0x00000000 14971 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000 14972 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP_DEFAULT 0x00000000 14973 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 14974 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP_DEFAULT 0x00000000 14975 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000 14976 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 14977 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 14978 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 14979 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 14980 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 14981 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP_DEFAULT 0x00000000 14982 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 14983 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS_DEFAULT 0x00000100 14984 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL_DEFAULT 0x00000000 14985 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 14986 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 14987 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 14988 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 14989 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 14990 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 14991 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 14992 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 14993 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 14994 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 14995 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 14996 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 14997 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 14998 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 14999 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 15000 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 15001 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 15002 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 15003 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 15004 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 15005 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 15006 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 15007 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 15008 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 15009 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 15010 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 15011 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 15012 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 15013 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP_DEFAULT 0x00000000 15014 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 15015 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 15016 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP_DEFAULT 0x00000000 15017 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 15018 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000 15019 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 15020 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000100 15021 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000 15022 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 15023 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000 15024 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP_DEFAULT 0x00001000 15025 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL_DEFAULT 0x00000000 15026 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 15027 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP_DEFAULT 0x00000000 15028 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL_DEFAULT 0x00000000 15029 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0_DEFAULT 0x00000000 15030 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1_DEFAULT 0x00000000 15031 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0_DEFAULT 0x00000000 15032 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1_DEFAULT 0x00000000 15033 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 15034 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 15035 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 15036 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 15037 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 15038 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP_DEFAULT 0x00000000 15039 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 15040 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP_DEFAULT 0x00000000 15041 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 15042 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x37000000 15043 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP_DEFAULT 0x00000000 15044 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000 15045 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS_DEFAULT 0x00000000 15046 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000 15047 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000 15048 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000 15049 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000 15050 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000 15051 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000 15052 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000 15053 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000 15054 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001 15055 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000 15056 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000 15057 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000 15058 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000 15059 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000 15060 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000 15061 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000 15062 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000 15063 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000 15064 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 15065 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST_DEFAULT 0x41010025 15066 #define cfgBIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP_DEFAULT 0x00000001 15067 #define cfgBIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS_DEFAULT 0x00000000 15068 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST_DEFAULT 0x44010026 15069 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP_16GT_DEFAULT 0x00000000 15070 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL_16GT_DEFAULT 0x00000000 15071 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT_DEFAULT 0x00000000 15072 #define cfgBIF_CFG_DEV0_EPF1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 15073 #define cfgBIF_CFG_DEV0_EPF1_1_RTM1_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 15074 #define cfgBIF_CFG_DEV0_EPF1_1_RTM2_PARITY_MISMATCH_STATUS_16GT_DEFAULT 0x00000000 15075 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 15076 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 15077 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 15078 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 15079 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 15080 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 15081 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 15082 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 15083 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 15084 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 15085 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 15086 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 15087 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 15088 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 15089 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 15090 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT_DEFAULT 0x000000f0 15091 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST_DEFAULT 0x4c010027 15092 #define cfgBIF_CFG_DEV0_EPF1_1_MARGINING_PORT_CAP_DEFAULT 0x00000000 15093 #define cfgBIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS_DEFAULT 0x00000000 15094 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 15095 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS_DEFAULT 0x00000000 15096 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 15097 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS_DEFAULT 0x00000000 15098 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 15099 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS_DEFAULT 0x00000000 15100 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 15101 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS_DEFAULT 0x00000000 15102 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 15103 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS_DEFAULT 0x00000000 15104 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 15105 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS_DEFAULT 0x00000000 15106 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 15107 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS_DEFAULT 0x00000000 15108 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 15109 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS_DEFAULT 0x00000000 15110 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 15111 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS_DEFAULT 0x00000000 15112 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 15113 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS_DEFAULT 0x00000000 15114 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 15115 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS_DEFAULT 0x00000000 15116 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 15117 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS_DEFAULT 0x00000000 15118 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 15119 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS_DEFAULT 0x00000000 15120 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 15121 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS_DEFAULT 0x00000000 15122 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 15123 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS_DEFAULT 0x00000000 15124 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL_DEFAULT 0x00009c38 15125 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS_DEFAULT 0x00000000 15126 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_DEFAULT 0x00000000 15127 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP_DEFAULT 0x00000000 15128 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL_DEFAULT 0x00000020 15129 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP_DEFAULT 0x00000000 15130 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL_DEFAULT 0x00000000 15131 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP_DEFAULT 0x00000000 15132 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL_DEFAULT 0x00000000 15133 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP_DEFAULT 0x00000000 15134 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL_DEFAULT 0x00000000 15135 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP_DEFAULT 0x00000000 15136 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL_DEFAULT 0x00000000 15137 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP_DEFAULT 0x00000000 15138 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL_DEFAULT 0x00000000 15139 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000 15140 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000 15141 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000 15142 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000 15143 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000 15144 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000 15145 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000 15146 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000 15147 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000 15148 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000 15149 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000 15150 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x0012000c 15151 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_DEFAULT 0x00000000 15152 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_DEFAULT 0x00000000 15153 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000 15154 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000 15155 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000 15156 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000 15157 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000 15158 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000 15159 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000 15160 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000 15161 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000 15162 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000 15163 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000 15164 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000 15165 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000 15166 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000 15167 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000 15168 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000 15169 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_DEFAULT 0x00000000 15170 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_DEFAULT 0x00000000 15171 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_DEFAULT 0x00000000 15172 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_DEFAULT 0x00000000 15173 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_DEFAULT 0x00000000 15174 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_DEFAULT 0x00000000 15175 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_DEFAULT 0x00000000 15176 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_DEFAULT 0x00000000 15177 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_DEFAULT 0x00000000 15178 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_DEFAULT 0x00000000 15179 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_DEFAULT 0x00000000 15180 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_DEFAULT 0x00000000 15181 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_DEFAULT 0x00000000 15182 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_DEFAULT 0x00000000 15183 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_DEFAULT 0x00000000 15184 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000 15185 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000 15186 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000 15187 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000 15188 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000 15189 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000 15190 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000 15191 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000 15192 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000 15193 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000 15194 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000 15195 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000 15196 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000 15197 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000 15198 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000 15199 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000 15200 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000 15201 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000 15202 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000 15203 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000 15204 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000 15205 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000 15206 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000 15207 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000 15208 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000 15209 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000 15210 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000 15211 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0_DEFAULT 0x00000000 15212 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1_DEFAULT 0x00000000 15213 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2_DEFAULT 0x00000000 15214 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3_DEFAULT 0x00000000 15215 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4_DEFAULT 0x00000000 15216 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5_DEFAULT 0x00000000 15217 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6_DEFAULT 0x00000000 15218 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7_DEFAULT 0x00000000 15219 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8_DEFAULT 0x00000000 15220 15221 15222 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp 15223 #define cfgBIF_CFG_DEV0_EPF2_1_VENDOR_ID_DEFAULT 0x00001002 15224 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_ID_DEFAULT 0x00007316 15225 #define cfgBIF_CFG_DEV0_EPF2_1_COMMAND_DEFAULT 0x00000000 15226 #define cfgBIF_CFG_DEV0_EPF2_1_STATUS_DEFAULT 0x00000000 15227 #define cfgBIF_CFG_DEV0_EPF2_1_REVISION_ID_DEFAULT 0x00000000 15228 #define cfgBIF_CFG_DEV0_EPF2_1_PROG_INTERFACE_DEFAULT 0x00000030 15229 #define cfgBIF_CFG_DEV0_EPF2_1_SUB_CLASS_DEFAULT 0x00000003 15230 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_CLASS_DEFAULT 0x0000000c 15231 #define cfgBIF_CFG_DEV0_EPF2_1_CACHE_LINE_DEFAULT 0x00000000 15232 #define cfgBIF_CFG_DEV0_EPF2_1_LATENCY_DEFAULT 0x00000000 15233 #define cfgBIF_CFG_DEV0_EPF2_1_HEADER_DEFAULT 0x00000080 15234 #define cfgBIF_CFG_DEV0_EPF2_1_BIST_DEFAULT 0x00000000 15235 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_1_DEFAULT 0x00000000 15236 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_2_DEFAULT 0x00000000 15237 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_3_DEFAULT 0x00000000 15238 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_4_DEFAULT 0x00000000 15239 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_5_DEFAULT 0x00000000 15240 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_6_DEFAULT 0x00000000 15241 #define cfgBIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 15242 #define cfgBIF_CFG_DEV0_EPF2_1_ADAPTER_ID_DEFAULT 0x73161002 15243 #define cfgBIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR_DEFAULT 0x00000000 15244 #define cfgBIF_CFG_DEV0_EPF2_1_CAP_PTR_DEFAULT 0x00000048 15245 #define cfgBIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE_DEFAULT 0x00000000 15246 #define cfgBIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN_DEFAULT 0x00000003 15247 #define cfgBIF_CFG_DEV0_EPF2_1_MIN_GRANT_DEFAULT 0x00000000 15248 #define cfgBIF_CFG_DEV0_EPF2_1_MAX_LATENCY_DEFAULT 0x00000000 15249 #define cfgBIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST_DEFAULT 0x00000000 15250 #define cfgBIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W_DEFAULT 0x73161002 15251 #define cfgBIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST_DEFAULT 0x00006400 15252 #define cfgBIF_CFG_DEV0_EPF2_1_PMI_CAP_DEFAULT 0x0000c800 15253 #define cfgBIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 15254 #define cfgBIF_CFG_DEV0_EPF2_1_SBRN_DEFAULT 0x00000000 15255 #define cfgBIF_CFG_DEV0_EPF2_1_FLADJ_DEFAULT 0x00000020 15256 #define cfgBIF_CFG_DEV0_EPF2_1_DBESL_DBESLD_DEFAULT 0x00000000 15257 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 15258 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CAP_DEFAULT 0x00000002 15259 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CAP_DEFAULT 0x00000f81 15260 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL_DEFAULT 0x00002810 15261 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS_DEFAULT 0x00000000 15262 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_CAP_DEFAULT 0x00000d04 15263 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_CNTL_DEFAULT 0x00000000 15264 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_STATUS_DEFAULT 0x00000001 15265 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CAP2_DEFAULT 0x00010000 15266 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2_DEFAULT 0x00000000 15267 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2_DEFAULT 0x00000000 15268 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_CAP2_DEFAULT 0x0000001e 15269 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_CNTL2_DEFAULT 0x00000004 15270 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_STATUS2_DEFAULT 0x00000001 15271 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST_DEFAULT 0x0000c000 15272 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL_DEFAULT 0x00000086 15273 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 15274 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 15275 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_DEFAULT 0x00000000 15276 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MASK_DEFAULT 0x00000000 15277 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 15278 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MASK_64_DEFAULT 0x00000000 15279 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_PENDING_DEFAULT 0x00000000 15280 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_PENDING_64_DEFAULT 0x00000000 15281 #define cfgBIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST_DEFAULT 0x00000000 15282 #define cfgBIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 15283 #define cfgBIF_CFG_DEV0_EPF2_1_MSIX_TABLE_DEFAULT 0x00000000 15284 #define cfgBIF_CFG_DEV0_EPF2_1_MSIX_PBA_DEFAULT 0x00000000 15285 #define cfgBIF_CFG_DEV0_EPF2_1_SATA_CAP_0_DEFAULT 0x00000000 15286 #define cfgBIF_CFG_DEV0_EPF2_1_SATA_CAP_1_DEFAULT 0x00000000 15287 #define cfgBIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX_DEFAULT 0x00000000 15288 #define cfgBIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA_DEFAULT 0x00000000 15289 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 15290 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 15291 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 15292 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 15293 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 15294 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 15295 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 15296 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 15297 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 15298 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 15299 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 15300 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 15301 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 15302 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 15303 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 15304 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 15305 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 15306 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 15307 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 15308 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 15309 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP_DEFAULT 0x00000000 15310 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020 15311 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP_DEFAULT 0x00000000 15312 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000 15313 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP_DEFAULT 0x00000000 15314 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000 15315 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP_DEFAULT 0x00000000 15316 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000 15317 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP_DEFAULT 0x00000000 15318 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 15319 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP_DEFAULT 0x00000000 15320 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000 15321 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 15322 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 15323 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 15324 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 15325 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 15326 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP_DEFAULT 0x00000000 15327 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 15328 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS_DEFAULT 0x00000100 15329 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL_DEFAULT 0x00000000 15330 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 15331 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 15332 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 15333 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 15334 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 15335 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 15336 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 15337 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 15338 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 15339 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP_DEFAULT 0x00000000 15340 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 15341 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000 15342 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP_DEFAULT 0x00001000 15343 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL_DEFAULT 0x00000000 15344 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 15345 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP_DEFAULT 0x00000000 15346 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 15347 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000 15348 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000 15349 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 15350 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0_DEFAULT 0x00000000 15351 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1_DEFAULT 0x00000000 15352 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2_DEFAULT 0x00000000 15353 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3_DEFAULT 0x00000000 15354 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4_DEFAULT 0x00000000 15355 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5_DEFAULT 0x00000000 15356 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6_DEFAULT 0x00000000 15357 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7_DEFAULT 0x00000000 15358 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8_DEFAULT 0x00000000 15359 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9_DEFAULT 0x00000000 15360 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10_DEFAULT 0x00000000 15361 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11_DEFAULT 0x00000000 15362 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12_DEFAULT 0x00000000 15363 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13_DEFAULT 0x00000000 15364 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14_DEFAULT 0x00000000 15365 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15_DEFAULT 0x00000000 15366 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16_DEFAULT 0x00000000 15367 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17_DEFAULT 0x00000000 15368 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18_DEFAULT 0x00000000 15369 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19_DEFAULT 0x00000000 15370 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20_DEFAULT 0x00000000 15371 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21_DEFAULT 0x00000000 15372 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22_DEFAULT 0x00000000 15373 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23_DEFAULT 0x00000000 15374 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24_DEFAULT 0x00000000 15375 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25_DEFAULT 0x00000000 15376 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26_DEFAULT 0x00000000 15377 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27_DEFAULT 0x00000000 15378 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28_DEFAULT 0x00000000 15379 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29_DEFAULT 0x00000000 15380 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30_DEFAULT 0x00000000 15381 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31_DEFAULT 0x00000000 15382 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32_DEFAULT 0x00000000 15383 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33_DEFAULT 0x00000000 15384 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34_DEFAULT 0x00000000 15385 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35_DEFAULT 0x00000000 15386 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36_DEFAULT 0x00000000 15387 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37_DEFAULT 0x00000000 15388 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38_DEFAULT 0x00000000 15389 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39_DEFAULT 0x00000000 15390 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40_DEFAULT 0x00000000 15391 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41_DEFAULT 0x00000000 15392 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42_DEFAULT 0x00000000 15393 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43_DEFAULT 0x00000000 15394 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44_DEFAULT 0x00000000 15395 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45_DEFAULT 0x00000000 15396 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46_DEFAULT 0x00000000 15397 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47_DEFAULT 0x00000000 15398 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48_DEFAULT 0x00000000 15399 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49_DEFAULT 0x00000000 15400 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50_DEFAULT 0x00000000 15401 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51_DEFAULT 0x00000000 15402 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52_DEFAULT 0x00000000 15403 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53_DEFAULT 0x00000000 15404 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54_DEFAULT 0x00000000 15405 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55_DEFAULT 0x00000000 15406 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56_DEFAULT 0x00000000 15407 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57_DEFAULT 0x00000000 15408 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58_DEFAULT 0x00000000 15409 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59_DEFAULT 0x00000000 15410 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60_DEFAULT 0x00000000 15411 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61_DEFAULT 0x00000000 15412 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62_DEFAULT 0x00000000 15413 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63_DEFAULT 0x00000000 15414 15415 15416 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp 15417 #define cfgBIF_CFG_DEV0_EPF3_1_VENDOR_ID_DEFAULT 0x00001002 15418 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_ID_DEFAULT 0x00007314 15419 #define cfgBIF_CFG_DEV0_EPF3_1_COMMAND_DEFAULT 0x00000000 15420 #define cfgBIF_CFG_DEV0_EPF3_1_STATUS_DEFAULT 0x00000000 15421 #define cfgBIF_CFG_DEV0_EPF3_1_REVISION_ID_DEFAULT 0x00000000 15422 #define cfgBIF_CFG_DEV0_EPF3_1_PROG_INTERFACE_DEFAULT 0x00000000 15423 #define cfgBIF_CFG_DEV0_EPF3_1_SUB_CLASS_DEFAULT 0x00000080 15424 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_CLASS_DEFAULT 0x0000000c 15425 #define cfgBIF_CFG_DEV0_EPF3_1_CACHE_LINE_DEFAULT 0x00000000 15426 #define cfgBIF_CFG_DEV0_EPF3_1_LATENCY_DEFAULT 0x00000000 15427 #define cfgBIF_CFG_DEV0_EPF3_1_HEADER_DEFAULT 0x00000080 15428 #define cfgBIF_CFG_DEV0_EPF3_1_BIST_DEFAULT 0x00000000 15429 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_1_DEFAULT 0x00000000 15430 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_2_DEFAULT 0x00000000 15431 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_3_DEFAULT 0x00000000 15432 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_4_DEFAULT 0x00000000 15433 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_5_DEFAULT 0x00000000 15434 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_6_DEFAULT 0x00000000 15435 #define cfgBIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 15436 #define cfgBIF_CFG_DEV0_EPF3_1_ADAPTER_ID_DEFAULT 0x73141002 15437 #define cfgBIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR_DEFAULT 0x00000000 15438 #define cfgBIF_CFG_DEV0_EPF3_1_CAP_PTR_DEFAULT 0x00000048 15439 #define cfgBIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE_DEFAULT 0x00000000 15440 #define cfgBIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN_DEFAULT 0x00000004 15441 #define cfgBIF_CFG_DEV0_EPF3_1_MIN_GRANT_DEFAULT 0x00000000 15442 #define cfgBIF_CFG_DEV0_EPF3_1_MAX_LATENCY_DEFAULT 0x00000000 15443 #define cfgBIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST_DEFAULT 0x00000000 15444 #define cfgBIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W_DEFAULT 0x73141002 15445 #define cfgBIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST_DEFAULT 0x00006400 15446 #define cfgBIF_CFG_DEV0_EPF3_1_PMI_CAP_DEFAULT 0x00000000 15447 #define cfgBIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 15448 #define cfgBIF_CFG_DEV0_EPF3_1_SBRN_DEFAULT 0x00000000 15449 #define cfgBIF_CFG_DEV0_EPF3_1_FLADJ_DEFAULT 0x00000020 15450 #define cfgBIF_CFG_DEV0_EPF3_1_DBESL_DBESLD_DEFAULT 0x00000000 15451 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 15452 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CAP_DEFAULT 0x00000002 15453 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CAP_DEFAULT 0x00000f81 15454 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL_DEFAULT 0x00002810 15455 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS_DEFAULT 0x00000000 15456 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_CAP_DEFAULT 0x00000d04 15457 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_CNTL_DEFAULT 0x00000000 15458 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_STATUS_DEFAULT 0x00000001 15459 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CAP2_DEFAULT 0x00010000 15460 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2_DEFAULT 0x00000000 15461 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2_DEFAULT 0x00000000 15462 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_CAP2_DEFAULT 0x0000001e 15463 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_CNTL2_DEFAULT 0x00000004 15464 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_STATUS2_DEFAULT 0x00000001 15465 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST_DEFAULT 0x0000c000 15466 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL_DEFAULT 0x00000082 15467 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 15468 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 15469 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_DEFAULT 0x00000000 15470 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MASK_DEFAULT 0x00000000 15471 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 15472 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MASK_64_DEFAULT 0x00000000 15473 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_PENDING_DEFAULT 0x00000000 15474 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_PENDING_64_DEFAULT 0x00000000 15475 #define cfgBIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST_DEFAULT 0x00000000 15476 #define cfgBIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 15477 #define cfgBIF_CFG_DEV0_EPF3_1_MSIX_TABLE_DEFAULT 0x00000000 15478 #define cfgBIF_CFG_DEV0_EPF3_1_MSIX_PBA_DEFAULT 0x00000000 15479 #define cfgBIF_CFG_DEV0_EPF3_1_SATA_CAP_0_DEFAULT 0x00000000 15480 #define cfgBIF_CFG_DEV0_EPF3_1_SATA_CAP_1_DEFAULT 0x00000000 15481 #define cfgBIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX_DEFAULT 0x00000000 15482 #define cfgBIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA_DEFAULT 0x00000000 15483 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 15484 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 15485 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 15486 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 15487 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 15488 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 15489 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 15490 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 15491 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 15492 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 15493 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 15494 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 15495 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 15496 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 15497 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 15498 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 15499 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 15500 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 15501 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 15502 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 15503 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP_DEFAULT 0x00000000 15504 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020 15505 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP_DEFAULT 0x00000000 15506 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000 15507 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP_DEFAULT 0x00000000 15508 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000 15509 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP_DEFAULT 0x00000000 15510 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000 15511 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP_DEFAULT 0x00000000 15512 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 15513 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP_DEFAULT 0x00000000 15514 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000 15515 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 15516 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 15517 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 15518 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 15519 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 15520 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP_DEFAULT 0x00000000 15521 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 15522 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS_DEFAULT 0x00000100 15523 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL_DEFAULT 0x00000000 15524 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 15525 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 15526 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 15527 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 15528 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 15529 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 15530 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 15531 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 15532 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 15533 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP_DEFAULT 0x00000000 15534 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 15535 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2f000000 15536 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP_DEFAULT 0x00001000 15537 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL_DEFAULT 0x00000000 15538 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 15539 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP_DEFAULT 0x00000000 15540 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 15541 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x40000000 15542 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000 15543 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 15544 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0_DEFAULT 0x00000000 15545 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1_DEFAULT 0x00000000 15546 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2_DEFAULT 0x00000000 15547 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3_DEFAULT 0x00000000 15548 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4_DEFAULT 0x00000000 15549 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5_DEFAULT 0x00000000 15550 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6_DEFAULT 0x00000000 15551 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7_DEFAULT 0x00000000 15552 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8_DEFAULT 0x00000000 15553 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9_DEFAULT 0x00000000 15554 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10_DEFAULT 0x00000000 15555 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11_DEFAULT 0x00000000 15556 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12_DEFAULT 0x00000000 15557 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13_DEFAULT 0x00000000 15558 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14_DEFAULT 0x00000000 15559 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15_DEFAULT 0x00000000 15560 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16_DEFAULT 0x00000000 15561 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17_DEFAULT 0x00000000 15562 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18_DEFAULT 0x00000000 15563 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19_DEFAULT 0x00000000 15564 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20_DEFAULT 0x00000000 15565 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21_DEFAULT 0x00000000 15566 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22_DEFAULT 0x00000000 15567 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23_DEFAULT 0x00000000 15568 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24_DEFAULT 0x00000000 15569 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25_DEFAULT 0x00000000 15570 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26_DEFAULT 0x00000000 15571 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27_DEFAULT 0x00000000 15572 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28_DEFAULT 0x00000000 15573 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29_DEFAULT 0x00000000 15574 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30_DEFAULT 0x00000000 15575 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31_DEFAULT 0x00000000 15576 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32_DEFAULT 0x00000000 15577 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33_DEFAULT 0x00000000 15578 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34_DEFAULT 0x00000000 15579 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35_DEFAULT 0x00000000 15580 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36_DEFAULT 0x00000000 15581 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37_DEFAULT 0x00000000 15582 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38_DEFAULT 0x00000000 15583 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39_DEFAULT 0x00000000 15584 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40_DEFAULT 0x00000000 15585 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41_DEFAULT 0x00000000 15586 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42_DEFAULT 0x00000000 15587 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43_DEFAULT 0x00000000 15588 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44_DEFAULT 0x00000000 15589 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45_DEFAULT 0x00000000 15590 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46_DEFAULT 0x00000000 15591 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47_DEFAULT 0x00000000 15592 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48_DEFAULT 0x00000000 15593 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49_DEFAULT 0x00000000 15594 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50_DEFAULT 0x00000000 15595 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51_DEFAULT 0x00000000 15596 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52_DEFAULT 0x00000000 15597 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53_DEFAULT 0x00000000 15598 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54_DEFAULT 0x00000000 15599 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55_DEFAULT 0x00000000 15600 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56_DEFAULT 0x00000000 15601 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57_DEFAULT 0x00000000 15602 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58_DEFAULT 0x00000000 15603 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59_DEFAULT 0x00000000 15604 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60_DEFAULT 0x00000000 15605 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61_DEFAULT 0x00000000 15606 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62_DEFAULT 0x00000000 15607 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63_DEFAULT 0x00000000 15608 15609 15610 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp 15611 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID_DEFAULT 0x00000000 15612 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID_DEFAULT 0x00000000 15613 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_COMMAND_DEFAULT 0x00000000 15614 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_STATUS_DEFAULT 0x00000000 15615 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID_DEFAULT 0x00000000 15616 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE_DEFAULT 0x00000000 15617 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS_DEFAULT 0x00000000 15618 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS_DEFAULT 0x00000000 15619 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE_DEFAULT 0x00000000 15620 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LATENCY_DEFAULT 0x00000000 15621 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_HEADER_DEFAULT 0x00000000 15622 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BIST_DEFAULT 0x00000000 15623 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1_DEFAULT 0x00000000 15624 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2_DEFAULT 0x00000000 15625 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3_DEFAULT 0x00000000 15626 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4_DEFAULT 0x00000000 15627 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5_DEFAULT 0x00000000 15628 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6_DEFAULT 0x00000000 15629 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 15630 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID_DEFAULT 0x73101002 15631 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR_DEFAULT 0x00000000 15632 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR_DEFAULT 0x00000048 15633 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE_DEFAULT 0x00000000 15634 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN_DEFAULT 0x00000000 15635 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT_DEFAULT 0x00000000 15636 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY_DEFAULT 0x00000000 15637 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 15638 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_DEFAULT 0x00000002 15639 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP_DEFAULT 0x00000000 15640 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL_DEFAULT 0x00000000 15641 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS_DEFAULT 0x00000000 15642 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP_DEFAULT 0x00000d04 15643 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL_DEFAULT 0x00000000 15644 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS_DEFAULT 0x00000000 15645 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2_DEFAULT 0x00010000 15646 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2_DEFAULT 0x00000000 15647 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2_DEFAULT 0x00000000 15648 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2_DEFAULT 0x0000001e 15649 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2_DEFAULT 0x00000000 15650 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2_DEFAULT 0x00000000 15651 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST_DEFAULT 0x0000c000 15652 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL_DEFAULT 0x00000082 15653 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 15654 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 15655 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_DEFAULT 0x00000000 15656 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_DEFAULT 0x00000000 15657 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 15658 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64_DEFAULT 0x00000000 15659 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_DEFAULT 0x00000000 15660 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64_DEFAULT 0x00000000 15661 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST_DEFAULT 0x00000000 15662 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 15663 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE_DEFAULT 0x00000000 15664 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA_DEFAULT 0x00000000 15665 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 15666 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 15667 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 15668 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 15669 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 15670 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 15671 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 15672 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 15673 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 15674 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 15675 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 15676 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 15677 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 15678 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 15679 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 15680 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 15681 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 15682 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 15683 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 15684 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 15685 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP_DEFAULT 0x00000000 15686 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 15687 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 15688 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP_DEFAULT 0x00000000 15689 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 15690 15691 15692 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp 15693 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID_DEFAULT 0x00000000 15694 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID_DEFAULT 0x00000000 15695 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_COMMAND_DEFAULT 0x00000000 15696 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_STATUS_DEFAULT 0x00000000 15697 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID_DEFAULT 0x00000000 15698 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE_DEFAULT 0x00000000 15699 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS_DEFAULT 0x00000000 15700 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS_DEFAULT 0x00000000 15701 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE_DEFAULT 0x00000000 15702 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LATENCY_DEFAULT 0x00000000 15703 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_HEADER_DEFAULT 0x00000000 15704 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BIST_DEFAULT 0x00000000 15705 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1_DEFAULT 0x00000000 15706 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2_DEFAULT 0x00000000 15707 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3_DEFAULT 0x00000000 15708 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4_DEFAULT 0x00000000 15709 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5_DEFAULT 0x00000000 15710 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6_DEFAULT 0x00000000 15711 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 15712 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID_DEFAULT 0x73101002 15713 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR_DEFAULT 0x00000000 15714 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR_DEFAULT 0x00000048 15715 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE_DEFAULT 0x00000000 15716 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN_DEFAULT 0x00000000 15717 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT_DEFAULT 0x00000000 15718 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY_DEFAULT 0x00000000 15719 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 15720 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_DEFAULT 0x00000002 15721 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP_DEFAULT 0x00000000 15722 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL_DEFAULT 0x00000000 15723 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS_DEFAULT 0x00000000 15724 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP_DEFAULT 0x00000d04 15725 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL_DEFAULT 0x00000000 15726 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS_DEFAULT 0x00000000 15727 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2_DEFAULT 0x00010000 15728 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2_DEFAULT 0x00000000 15729 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2_DEFAULT 0x00000000 15730 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2_DEFAULT 0x0000001e 15731 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2_DEFAULT 0x00000000 15732 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2_DEFAULT 0x00000000 15733 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST_DEFAULT 0x0000c000 15734 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL_DEFAULT 0x00000082 15735 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 15736 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 15737 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_DEFAULT 0x00000000 15738 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_DEFAULT 0x00000000 15739 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 15740 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64_DEFAULT 0x00000000 15741 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_DEFAULT 0x00000000 15742 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64_DEFAULT 0x00000000 15743 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST_DEFAULT 0x00000000 15744 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 15745 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE_DEFAULT 0x00000000 15746 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA_DEFAULT 0x00000000 15747 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 15748 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 15749 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 15750 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 15751 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 15752 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 15753 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 15754 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 15755 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 15756 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 15757 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 15758 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 15759 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 15760 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 15761 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 15762 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 15763 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 15764 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 15765 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 15766 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 15767 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP_DEFAULT 0x00000000 15768 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 15769 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 15770 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP_DEFAULT 0x00000000 15771 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 15772 15773 15774 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp 15775 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID_DEFAULT 0x00000000 15776 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID_DEFAULT 0x00000000 15777 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_COMMAND_DEFAULT 0x00000000 15778 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_STATUS_DEFAULT 0x00000000 15779 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID_DEFAULT 0x00000000 15780 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE_DEFAULT 0x00000000 15781 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS_DEFAULT 0x00000000 15782 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS_DEFAULT 0x00000000 15783 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE_DEFAULT 0x00000000 15784 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LATENCY_DEFAULT 0x00000000 15785 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_HEADER_DEFAULT 0x00000000 15786 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BIST_DEFAULT 0x00000000 15787 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1_DEFAULT 0x00000000 15788 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2_DEFAULT 0x00000000 15789 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3_DEFAULT 0x00000000 15790 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4_DEFAULT 0x00000000 15791 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5_DEFAULT 0x00000000 15792 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6_DEFAULT 0x00000000 15793 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 15794 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID_DEFAULT 0x73101002 15795 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR_DEFAULT 0x00000000 15796 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR_DEFAULT 0x00000048 15797 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE_DEFAULT 0x00000000 15798 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN_DEFAULT 0x00000000 15799 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT_DEFAULT 0x00000000 15800 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY_DEFAULT 0x00000000 15801 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 15802 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_DEFAULT 0x00000002 15803 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP_DEFAULT 0x00000000 15804 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL_DEFAULT 0x00000000 15805 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS_DEFAULT 0x00000000 15806 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP_DEFAULT 0x00000d04 15807 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL_DEFAULT 0x00000000 15808 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS_DEFAULT 0x00000000 15809 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2_DEFAULT 0x00010000 15810 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2_DEFAULT 0x00000000 15811 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2_DEFAULT 0x00000000 15812 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2_DEFAULT 0x0000001e 15813 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2_DEFAULT 0x00000000 15814 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2_DEFAULT 0x00000000 15815 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST_DEFAULT 0x0000c000 15816 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL_DEFAULT 0x00000082 15817 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 15818 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 15819 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_DEFAULT 0x00000000 15820 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_DEFAULT 0x00000000 15821 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 15822 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64_DEFAULT 0x00000000 15823 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_DEFAULT 0x00000000 15824 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64_DEFAULT 0x00000000 15825 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST_DEFAULT 0x00000000 15826 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 15827 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE_DEFAULT 0x00000000 15828 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA_DEFAULT 0x00000000 15829 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 15830 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 15831 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 15832 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 15833 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 15834 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 15835 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 15836 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 15837 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 15838 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 15839 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 15840 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 15841 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 15842 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 15843 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 15844 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 15845 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 15846 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 15847 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 15848 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 15849 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP_DEFAULT 0x00000000 15850 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 15851 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 15852 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP_DEFAULT 0x00000000 15853 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 15854 15855 15856 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp 15857 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID_DEFAULT 0x00000000 15858 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID_DEFAULT 0x00000000 15859 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_COMMAND_DEFAULT 0x00000000 15860 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_STATUS_DEFAULT 0x00000000 15861 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID_DEFAULT 0x00000000 15862 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE_DEFAULT 0x00000000 15863 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS_DEFAULT 0x00000000 15864 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS_DEFAULT 0x00000000 15865 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE_DEFAULT 0x00000000 15866 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LATENCY_DEFAULT 0x00000000 15867 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_HEADER_DEFAULT 0x00000000 15868 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BIST_DEFAULT 0x00000000 15869 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1_DEFAULT 0x00000000 15870 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2_DEFAULT 0x00000000 15871 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3_DEFAULT 0x00000000 15872 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4_DEFAULT 0x00000000 15873 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5_DEFAULT 0x00000000 15874 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6_DEFAULT 0x00000000 15875 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 15876 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID_DEFAULT 0x73101002 15877 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR_DEFAULT 0x00000000 15878 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR_DEFAULT 0x00000048 15879 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE_DEFAULT 0x00000000 15880 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN_DEFAULT 0x00000000 15881 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT_DEFAULT 0x00000000 15882 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY_DEFAULT 0x00000000 15883 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 15884 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_DEFAULT 0x00000002 15885 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP_DEFAULT 0x00000000 15886 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL_DEFAULT 0x00000000 15887 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS_DEFAULT 0x00000000 15888 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP_DEFAULT 0x00000d04 15889 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL_DEFAULT 0x00000000 15890 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS_DEFAULT 0x00000000 15891 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2_DEFAULT 0x00010000 15892 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2_DEFAULT 0x00000000 15893 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2_DEFAULT 0x00000000 15894 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2_DEFAULT 0x0000001e 15895 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2_DEFAULT 0x00000000 15896 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2_DEFAULT 0x00000000 15897 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST_DEFAULT 0x0000c000 15898 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL_DEFAULT 0x00000082 15899 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 15900 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 15901 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_DEFAULT 0x00000000 15902 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_DEFAULT 0x00000000 15903 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 15904 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64_DEFAULT 0x00000000 15905 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_DEFAULT 0x00000000 15906 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64_DEFAULT 0x00000000 15907 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST_DEFAULT 0x00000000 15908 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 15909 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE_DEFAULT 0x00000000 15910 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA_DEFAULT 0x00000000 15911 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 15912 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 15913 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 15914 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 15915 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 15916 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 15917 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 15918 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 15919 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 15920 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 15921 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 15922 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 15923 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 15924 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 15925 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 15926 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 15927 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 15928 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 15929 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 15930 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 15931 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP_DEFAULT 0x00000000 15932 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 15933 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 15934 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP_DEFAULT 0x00000000 15935 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 15936 15937 15938 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp 15939 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID_DEFAULT 0x00000000 15940 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID_DEFAULT 0x00000000 15941 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_COMMAND_DEFAULT 0x00000000 15942 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_STATUS_DEFAULT 0x00000000 15943 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID_DEFAULT 0x00000000 15944 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE_DEFAULT 0x00000000 15945 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS_DEFAULT 0x00000000 15946 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS_DEFAULT 0x00000000 15947 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE_DEFAULT 0x00000000 15948 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LATENCY_DEFAULT 0x00000000 15949 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_HEADER_DEFAULT 0x00000000 15950 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BIST_DEFAULT 0x00000000 15951 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1_DEFAULT 0x00000000 15952 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2_DEFAULT 0x00000000 15953 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3_DEFAULT 0x00000000 15954 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4_DEFAULT 0x00000000 15955 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5_DEFAULT 0x00000000 15956 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6_DEFAULT 0x00000000 15957 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 15958 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID_DEFAULT 0x73101002 15959 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR_DEFAULT 0x00000000 15960 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR_DEFAULT 0x00000048 15961 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE_DEFAULT 0x00000000 15962 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN_DEFAULT 0x00000000 15963 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT_DEFAULT 0x00000000 15964 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY_DEFAULT 0x00000000 15965 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 15966 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_DEFAULT 0x00000002 15967 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP_DEFAULT 0x00000000 15968 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL_DEFAULT 0x00000000 15969 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS_DEFAULT 0x00000000 15970 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP_DEFAULT 0x00000d04 15971 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL_DEFAULT 0x00000000 15972 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS_DEFAULT 0x00000000 15973 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2_DEFAULT 0x00010000 15974 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2_DEFAULT 0x00000000 15975 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2_DEFAULT 0x00000000 15976 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2_DEFAULT 0x0000001e 15977 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2_DEFAULT 0x00000000 15978 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2_DEFAULT 0x00000000 15979 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST_DEFAULT 0x0000c000 15980 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL_DEFAULT 0x00000082 15981 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 15982 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 15983 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_DEFAULT 0x00000000 15984 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_DEFAULT 0x00000000 15985 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 15986 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64_DEFAULT 0x00000000 15987 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_DEFAULT 0x00000000 15988 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64_DEFAULT 0x00000000 15989 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST_DEFAULT 0x00000000 15990 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 15991 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE_DEFAULT 0x00000000 15992 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA_DEFAULT 0x00000000 15993 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 15994 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 15995 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 15996 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 15997 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 15998 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 15999 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 16000 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 16001 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 16002 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 16003 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 16004 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 16005 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 16006 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 16007 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 16008 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 16009 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 16010 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 16011 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 16012 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 16013 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP_DEFAULT 0x00000000 16014 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 16015 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 16016 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP_DEFAULT 0x00000000 16017 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 16018 16019 16020 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp 16021 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID_DEFAULT 0x00000000 16022 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID_DEFAULT 0x00000000 16023 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_COMMAND_DEFAULT 0x00000000 16024 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_STATUS_DEFAULT 0x00000000 16025 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID_DEFAULT 0x00000000 16026 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE_DEFAULT 0x00000000 16027 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS_DEFAULT 0x00000000 16028 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS_DEFAULT 0x00000000 16029 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE_DEFAULT 0x00000000 16030 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LATENCY_DEFAULT 0x00000000 16031 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_HEADER_DEFAULT 0x00000000 16032 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BIST_DEFAULT 0x00000000 16033 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1_DEFAULT 0x00000000 16034 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2_DEFAULT 0x00000000 16035 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3_DEFAULT 0x00000000 16036 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4_DEFAULT 0x00000000 16037 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5_DEFAULT 0x00000000 16038 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6_DEFAULT 0x00000000 16039 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 16040 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID_DEFAULT 0x73101002 16041 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR_DEFAULT 0x00000000 16042 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR_DEFAULT 0x00000048 16043 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE_DEFAULT 0x00000000 16044 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN_DEFAULT 0x00000000 16045 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT_DEFAULT 0x00000000 16046 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY_DEFAULT 0x00000000 16047 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 16048 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_DEFAULT 0x00000002 16049 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP_DEFAULT 0x00000000 16050 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL_DEFAULT 0x00000000 16051 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS_DEFAULT 0x00000000 16052 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP_DEFAULT 0x00000d04 16053 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL_DEFAULT 0x00000000 16054 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS_DEFAULT 0x00000000 16055 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2_DEFAULT 0x00010000 16056 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2_DEFAULT 0x00000000 16057 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2_DEFAULT 0x00000000 16058 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2_DEFAULT 0x0000001e 16059 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2_DEFAULT 0x00000000 16060 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2_DEFAULT 0x00000000 16061 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST_DEFAULT 0x0000c000 16062 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL_DEFAULT 0x00000082 16063 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 16064 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 16065 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_DEFAULT 0x00000000 16066 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_DEFAULT 0x00000000 16067 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 16068 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64_DEFAULT 0x00000000 16069 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_DEFAULT 0x00000000 16070 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64_DEFAULT 0x00000000 16071 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST_DEFAULT 0x00000000 16072 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 16073 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE_DEFAULT 0x00000000 16074 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA_DEFAULT 0x00000000 16075 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 16076 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 16077 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 16078 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 16079 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 16080 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 16081 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 16082 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 16083 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 16084 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 16085 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 16086 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 16087 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 16088 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 16089 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 16090 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 16091 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 16092 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 16093 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 16094 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 16095 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP_DEFAULT 0x00000000 16096 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 16097 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 16098 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP_DEFAULT 0x00000000 16099 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 16100 16101 16102 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp 16103 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID_DEFAULT 0x00000000 16104 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID_DEFAULT 0x00000000 16105 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_COMMAND_DEFAULT 0x00000000 16106 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_STATUS_DEFAULT 0x00000000 16107 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID_DEFAULT 0x00000000 16108 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE_DEFAULT 0x00000000 16109 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS_DEFAULT 0x00000000 16110 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS_DEFAULT 0x00000000 16111 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE_DEFAULT 0x00000000 16112 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LATENCY_DEFAULT 0x00000000 16113 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_HEADER_DEFAULT 0x00000000 16114 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BIST_DEFAULT 0x00000000 16115 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1_DEFAULT 0x00000000 16116 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2_DEFAULT 0x00000000 16117 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3_DEFAULT 0x00000000 16118 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4_DEFAULT 0x00000000 16119 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5_DEFAULT 0x00000000 16120 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6_DEFAULT 0x00000000 16121 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 16122 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID_DEFAULT 0x73101002 16123 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR_DEFAULT 0x00000000 16124 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR_DEFAULT 0x00000048 16125 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE_DEFAULT 0x00000000 16126 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN_DEFAULT 0x00000000 16127 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT_DEFAULT 0x00000000 16128 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY_DEFAULT 0x00000000 16129 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 16130 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_DEFAULT 0x00000002 16131 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP_DEFAULT 0x00000000 16132 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL_DEFAULT 0x00000000 16133 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS_DEFAULT 0x00000000 16134 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP_DEFAULT 0x00000d04 16135 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL_DEFAULT 0x00000000 16136 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS_DEFAULT 0x00000000 16137 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2_DEFAULT 0x00010000 16138 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2_DEFAULT 0x00000000 16139 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2_DEFAULT 0x00000000 16140 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2_DEFAULT 0x0000001e 16141 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2_DEFAULT 0x00000000 16142 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2_DEFAULT 0x00000000 16143 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST_DEFAULT 0x0000c000 16144 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL_DEFAULT 0x00000082 16145 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 16146 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 16147 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_DEFAULT 0x00000000 16148 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_DEFAULT 0x00000000 16149 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 16150 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64_DEFAULT 0x00000000 16151 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_DEFAULT 0x00000000 16152 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64_DEFAULT 0x00000000 16153 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST_DEFAULT 0x00000000 16154 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 16155 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE_DEFAULT 0x00000000 16156 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA_DEFAULT 0x00000000 16157 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 16158 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 16159 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 16160 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 16161 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 16162 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 16163 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 16164 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 16165 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 16166 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 16167 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 16168 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 16169 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 16170 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 16171 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 16172 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 16173 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 16174 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 16175 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 16176 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 16177 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP_DEFAULT 0x00000000 16178 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 16179 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 16180 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP_DEFAULT 0x00000000 16181 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 16182 16183 16184 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp 16185 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID_DEFAULT 0x00000000 16186 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID_DEFAULT 0x00000000 16187 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_COMMAND_DEFAULT 0x00000000 16188 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_STATUS_DEFAULT 0x00000000 16189 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID_DEFAULT 0x00000000 16190 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE_DEFAULT 0x00000000 16191 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS_DEFAULT 0x00000000 16192 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS_DEFAULT 0x00000000 16193 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE_DEFAULT 0x00000000 16194 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LATENCY_DEFAULT 0x00000000 16195 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_HEADER_DEFAULT 0x00000000 16196 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BIST_DEFAULT 0x00000000 16197 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1_DEFAULT 0x00000000 16198 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2_DEFAULT 0x00000000 16199 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3_DEFAULT 0x00000000 16200 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4_DEFAULT 0x00000000 16201 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5_DEFAULT 0x00000000 16202 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6_DEFAULT 0x00000000 16203 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 16204 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID_DEFAULT 0x73101002 16205 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR_DEFAULT 0x00000000 16206 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR_DEFAULT 0x00000048 16207 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE_DEFAULT 0x00000000 16208 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN_DEFAULT 0x00000000 16209 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT_DEFAULT 0x00000000 16210 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY_DEFAULT 0x00000000 16211 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 16212 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_DEFAULT 0x00000002 16213 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP_DEFAULT 0x00000000 16214 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL_DEFAULT 0x00000000 16215 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS_DEFAULT 0x00000000 16216 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP_DEFAULT 0x00000d04 16217 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL_DEFAULT 0x00000000 16218 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS_DEFAULT 0x00000000 16219 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2_DEFAULT 0x00010000 16220 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2_DEFAULT 0x00000000 16221 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2_DEFAULT 0x00000000 16222 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2_DEFAULT 0x0000001e 16223 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2_DEFAULT 0x00000000 16224 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2_DEFAULT 0x00000000 16225 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST_DEFAULT 0x0000c000 16226 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL_DEFAULT 0x00000082 16227 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 16228 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 16229 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_DEFAULT 0x00000000 16230 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_DEFAULT 0x00000000 16231 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 16232 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64_DEFAULT 0x00000000 16233 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_DEFAULT 0x00000000 16234 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64_DEFAULT 0x00000000 16235 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST_DEFAULT 0x00000000 16236 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 16237 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE_DEFAULT 0x00000000 16238 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA_DEFAULT 0x00000000 16239 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 16240 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 16241 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 16242 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 16243 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 16244 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 16245 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 16246 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 16247 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 16248 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 16249 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 16250 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 16251 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 16252 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 16253 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 16254 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 16255 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 16256 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 16257 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 16258 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 16259 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP_DEFAULT 0x00000000 16260 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 16261 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 16262 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP_DEFAULT 0x00000000 16263 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 16264 16265 16266 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp 16267 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID_DEFAULT 0x00000000 16268 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID_DEFAULT 0x00000000 16269 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_COMMAND_DEFAULT 0x00000000 16270 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_STATUS_DEFAULT 0x00000000 16271 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID_DEFAULT 0x00000000 16272 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE_DEFAULT 0x00000000 16273 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS_DEFAULT 0x00000000 16274 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS_DEFAULT 0x00000000 16275 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE_DEFAULT 0x00000000 16276 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LATENCY_DEFAULT 0x00000000 16277 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_HEADER_DEFAULT 0x00000000 16278 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BIST_DEFAULT 0x00000000 16279 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1_DEFAULT 0x00000000 16280 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2_DEFAULT 0x00000000 16281 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3_DEFAULT 0x00000000 16282 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4_DEFAULT 0x00000000 16283 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5_DEFAULT 0x00000000 16284 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6_DEFAULT 0x00000000 16285 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 16286 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID_DEFAULT 0x73101002 16287 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR_DEFAULT 0x00000000 16288 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR_DEFAULT 0x00000048 16289 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE_DEFAULT 0x00000000 16290 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN_DEFAULT 0x00000000 16291 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT_DEFAULT 0x00000000 16292 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY_DEFAULT 0x00000000 16293 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 16294 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_DEFAULT 0x00000002 16295 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP_DEFAULT 0x00000000 16296 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL_DEFAULT 0x00000000 16297 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS_DEFAULT 0x00000000 16298 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP_DEFAULT 0x00000d04 16299 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL_DEFAULT 0x00000000 16300 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS_DEFAULT 0x00000000 16301 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2_DEFAULT 0x00010000 16302 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2_DEFAULT 0x00000000 16303 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2_DEFAULT 0x00000000 16304 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2_DEFAULT 0x0000001e 16305 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2_DEFAULT 0x00000000 16306 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2_DEFAULT 0x00000000 16307 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST_DEFAULT 0x0000c000 16308 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL_DEFAULT 0x00000082 16309 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 16310 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 16311 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_DEFAULT 0x00000000 16312 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_DEFAULT 0x00000000 16313 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 16314 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64_DEFAULT 0x00000000 16315 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_DEFAULT 0x00000000 16316 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64_DEFAULT 0x00000000 16317 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST_DEFAULT 0x00000000 16318 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 16319 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE_DEFAULT 0x00000000 16320 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA_DEFAULT 0x00000000 16321 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 16322 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 16323 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 16324 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 16325 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 16326 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 16327 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 16328 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 16329 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 16330 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 16331 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 16332 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 16333 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 16334 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 16335 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 16336 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 16337 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 16338 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 16339 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 16340 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 16341 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP_DEFAULT 0x00000000 16342 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 16343 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 16344 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP_DEFAULT 0x00000000 16345 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 16346 16347 16348 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp 16349 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID_DEFAULT 0x00000000 16350 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID_DEFAULT 0x00000000 16351 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_COMMAND_DEFAULT 0x00000000 16352 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_STATUS_DEFAULT 0x00000000 16353 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID_DEFAULT 0x00000000 16354 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE_DEFAULT 0x00000000 16355 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS_DEFAULT 0x00000000 16356 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS_DEFAULT 0x00000000 16357 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE_DEFAULT 0x00000000 16358 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LATENCY_DEFAULT 0x00000000 16359 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_HEADER_DEFAULT 0x00000000 16360 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BIST_DEFAULT 0x00000000 16361 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1_DEFAULT 0x00000000 16362 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2_DEFAULT 0x00000000 16363 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3_DEFAULT 0x00000000 16364 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4_DEFAULT 0x00000000 16365 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5_DEFAULT 0x00000000 16366 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6_DEFAULT 0x00000000 16367 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 16368 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID_DEFAULT 0x73101002 16369 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR_DEFAULT 0x00000000 16370 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR_DEFAULT 0x00000048 16371 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE_DEFAULT 0x00000000 16372 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN_DEFAULT 0x00000000 16373 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT_DEFAULT 0x00000000 16374 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY_DEFAULT 0x00000000 16375 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 16376 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_DEFAULT 0x00000002 16377 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP_DEFAULT 0x00000000 16378 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL_DEFAULT 0x00000000 16379 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS_DEFAULT 0x00000000 16380 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP_DEFAULT 0x00000d04 16381 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL_DEFAULT 0x00000000 16382 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS_DEFAULT 0x00000000 16383 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2_DEFAULT 0x00010000 16384 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2_DEFAULT 0x00000000 16385 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2_DEFAULT 0x00000000 16386 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2_DEFAULT 0x0000001e 16387 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2_DEFAULT 0x00000000 16388 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2_DEFAULT 0x00000000 16389 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST_DEFAULT 0x0000c000 16390 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL_DEFAULT 0x00000082 16391 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 16392 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 16393 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_DEFAULT 0x00000000 16394 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_DEFAULT 0x00000000 16395 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 16396 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64_DEFAULT 0x00000000 16397 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_DEFAULT 0x00000000 16398 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64_DEFAULT 0x00000000 16399 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST_DEFAULT 0x00000000 16400 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 16401 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE_DEFAULT 0x00000000 16402 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA_DEFAULT 0x00000000 16403 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 16404 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 16405 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 16406 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 16407 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 16408 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 16409 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 16410 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 16411 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 16412 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 16413 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 16414 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 16415 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 16416 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 16417 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 16418 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 16419 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 16420 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 16421 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 16422 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 16423 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP_DEFAULT 0x00000000 16424 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 16425 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 16426 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP_DEFAULT 0x00000000 16427 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 16428 16429 16430 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp 16431 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID_DEFAULT 0x00000000 16432 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID_DEFAULT 0x00000000 16433 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_COMMAND_DEFAULT 0x00000000 16434 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_STATUS_DEFAULT 0x00000000 16435 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID_DEFAULT 0x00000000 16436 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE_DEFAULT 0x00000000 16437 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS_DEFAULT 0x00000000 16438 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS_DEFAULT 0x00000000 16439 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE_DEFAULT 0x00000000 16440 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LATENCY_DEFAULT 0x00000000 16441 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_HEADER_DEFAULT 0x00000000 16442 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BIST_DEFAULT 0x00000000 16443 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1_DEFAULT 0x00000000 16444 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2_DEFAULT 0x00000000 16445 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3_DEFAULT 0x00000000 16446 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4_DEFAULT 0x00000000 16447 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5_DEFAULT 0x00000000 16448 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6_DEFAULT 0x00000000 16449 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 16450 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID_DEFAULT 0x73101002 16451 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR_DEFAULT 0x00000000 16452 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR_DEFAULT 0x00000048 16453 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE_DEFAULT 0x00000000 16454 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN_DEFAULT 0x00000000 16455 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT_DEFAULT 0x00000000 16456 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY_DEFAULT 0x00000000 16457 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 16458 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_DEFAULT 0x00000002 16459 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP_DEFAULT 0x00000000 16460 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL_DEFAULT 0x00000000 16461 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS_DEFAULT 0x00000000 16462 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP_DEFAULT 0x00000d04 16463 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL_DEFAULT 0x00000000 16464 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS_DEFAULT 0x00000000 16465 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2_DEFAULT 0x00010000 16466 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2_DEFAULT 0x00000000 16467 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2_DEFAULT 0x00000000 16468 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2_DEFAULT 0x0000001e 16469 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2_DEFAULT 0x00000000 16470 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2_DEFAULT 0x00000000 16471 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST_DEFAULT 0x0000c000 16472 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL_DEFAULT 0x00000082 16473 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 16474 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 16475 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_DEFAULT 0x00000000 16476 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_DEFAULT 0x00000000 16477 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 16478 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64_DEFAULT 0x00000000 16479 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_DEFAULT 0x00000000 16480 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64_DEFAULT 0x00000000 16481 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST_DEFAULT 0x00000000 16482 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 16483 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE_DEFAULT 0x00000000 16484 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA_DEFAULT 0x00000000 16485 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 16486 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 16487 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 16488 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 16489 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 16490 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 16491 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 16492 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 16493 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 16494 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 16495 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 16496 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 16497 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 16498 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 16499 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 16500 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 16501 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 16502 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 16503 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 16504 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 16505 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP_DEFAULT 0x00000000 16506 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 16507 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 16508 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP_DEFAULT 0x00000000 16509 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 16510 16511 16512 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp 16513 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID_DEFAULT 0x00000000 16514 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID_DEFAULT 0x00000000 16515 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_COMMAND_DEFAULT 0x00000000 16516 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_STATUS_DEFAULT 0x00000000 16517 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID_DEFAULT 0x00000000 16518 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE_DEFAULT 0x00000000 16519 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS_DEFAULT 0x00000000 16520 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS_DEFAULT 0x00000000 16521 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE_DEFAULT 0x00000000 16522 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LATENCY_DEFAULT 0x00000000 16523 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_HEADER_DEFAULT 0x00000000 16524 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BIST_DEFAULT 0x00000000 16525 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1_DEFAULT 0x00000000 16526 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2_DEFAULT 0x00000000 16527 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3_DEFAULT 0x00000000 16528 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4_DEFAULT 0x00000000 16529 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5_DEFAULT 0x00000000 16530 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6_DEFAULT 0x00000000 16531 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 16532 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID_DEFAULT 0x73101002 16533 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR_DEFAULT 0x00000000 16534 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR_DEFAULT 0x00000048 16535 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE_DEFAULT 0x00000000 16536 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN_DEFAULT 0x00000000 16537 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT_DEFAULT 0x00000000 16538 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY_DEFAULT 0x00000000 16539 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 16540 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_DEFAULT 0x00000002 16541 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP_DEFAULT 0x00000000 16542 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL_DEFAULT 0x00000000 16543 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS_DEFAULT 0x00000000 16544 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP_DEFAULT 0x00000d04 16545 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL_DEFAULT 0x00000000 16546 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS_DEFAULT 0x00000000 16547 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2_DEFAULT 0x00010000 16548 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2_DEFAULT 0x00000000 16549 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2_DEFAULT 0x00000000 16550 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2_DEFAULT 0x0000001e 16551 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2_DEFAULT 0x00000000 16552 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2_DEFAULT 0x00000000 16553 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST_DEFAULT 0x0000c000 16554 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL_DEFAULT 0x00000082 16555 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 16556 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 16557 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_DEFAULT 0x00000000 16558 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_DEFAULT 0x00000000 16559 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 16560 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64_DEFAULT 0x00000000 16561 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_DEFAULT 0x00000000 16562 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64_DEFAULT 0x00000000 16563 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST_DEFAULT 0x00000000 16564 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 16565 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE_DEFAULT 0x00000000 16566 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA_DEFAULT 0x00000000 16567 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 16568 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 16569 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 16570 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 16571 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 16572 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 16573 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 16574 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 16575 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 16576 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 16577 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 16578 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 16579 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 16580 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 16581 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 16582 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 16583 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 16584 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 16585 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 16586 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 16587 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP_DEFAULT 0x00000000 16588 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 16589 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 16590 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP_DEFAULT 0x00000000 16591 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 16592 16593 16594 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp 16595 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID_DEFAULT 0x00000000 16596 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID_DEFAULT 0x00000000 16597 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_COMMAND_DEFAULT 0x00000000 16598 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_STATUS_DEFAULT 0x00000000 16599 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID_DEFAULT 0x00000000 16600 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE_DEFAULT 0x00000000 16601 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS_DEFAULT 0x00000000 16602 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS_DEFAULT 0x00000000 16603 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE_DEFAULT 0x00000000 16604 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LATENCY_DEFAULT 0x00000000 16605 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_HEADER_DEFAULT 0x00000000 16606 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BIST_DEFAULT 0x00000000 16607 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1_DEFAULT 0x00000000 16608 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2_DEFAULT 0x00000000 16609 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3_DEFAULT 0x00000000 16610 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4_DEFAULT 0x00000000 16611 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5_DEFAULT 0x00000000 16612 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6_DEFAULT 0x00000000 16613 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 16614 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID_DEFAULT 0x73101002 16615 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR_DEFAULT 0x00000000 16616 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR_DEFAULT 0x00000048 16617 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE_DEFAULT 0x00000000 16618 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN_DEFAULT 0x00000000 16619 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT_DEFAULT 0x00000000 16620 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY_DEFAULT 0x00000000 16621 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 16622 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_DEFAULT 0x00000002 16623 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP_DEFAULT 0x00000000 16624 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL_DEFAULT 0x00000000 16625 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS_DEFAULT 0x00000000 16626 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP_DEFAULT 0x00000d04 16627 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL_DEFAULT 0x00000000 16628 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS_DEFAULT 0x00000000 16629 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2_DEFAULT 0x00010000 16630 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2_DEFAULT 0x00000000 16631 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2_DEFAULT 0x00000000 16632 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2_DEFAULT 0x0000001e 16633 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2_DEFAULT 0x00000000 16634 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2_DEFAULT 0x00000000 16635 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST_DEFAULT 0x0000c000 16636 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL_DEFAULT 0x00000082 16637 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 16638 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 16639 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_DEFAULT 0x00000000 16640 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_DEFAULT 0x00000000 16641 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 16642 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64_DEFAULT 0x00000000 16643 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_DEFAULT 0x00000000 16644 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64_DEFAULT 0x00000000 16645 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST_DEFAULT 0x00000000 16646 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 16647 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE_DEFAULT 0x00000000 16648 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA_DEFAULT 0x00000000 16649 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 16650 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 16651 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 16652 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 16653 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 16654 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 16655 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 16656 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 16657 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 16658 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 16659 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 16660 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 16661 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 16662 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 16663 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 16664 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 16665 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 16666 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 16667 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 16668 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 16669 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP_DEFAULT 0x00000000 16670 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 16671 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 16672 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP_DEFAULT 0x00000000 16673 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 16674 16675 16676 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp 16677 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID_DEFAULT 0x00000000 16678 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID_DEFAULT 0x00000000 16679 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_COMMAND_DEFAULT 0x00000000 16680 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_STATUS_DEFAULT 0x00000000 16681 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID_DEFAULT 0x00000000 16682 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE_DEFAULT 0x00000000 16683 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS_DEFAULT 0x00000000 16684 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS_DEFAULT 0x00000000 16685 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE_DEFAULT 0x00000000 16686 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LATENCY_DEFAULT 0x00000000 16687 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_HEADER_DEFAULT 0x00000000 16688 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BIST_DEFAULT 0x00000000 16689 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1_DEFAULT 0x00000000 16690 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2_DEFAULT 0x00000000 16691 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3_DEFAULT 0x00000000 16692 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4_DEFAULT 0x00000000 16693 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5_DEFAULT 0x00000000 16694 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6_DEFAULT 0x00000000 16695 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 16696 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID_DEFAULT 0x73101002 16697 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR_DEFAULT 0x00000000 16698 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR_DEFAULT 0x00000048 16699 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE_DEFAULT 0x00000000 16700 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN_DEFAULT 0x00000000 16701 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT_DEFAULT 0x00000000 16702 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY_DEFAULT 0x00000000 16703 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 16704 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_DEFAULT 0x00000002 16705 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP_DEFAULT 0x00000000 16706 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL_DEFAULT 0x00000000 16707 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS_DEFAULT 0x00000000 16708 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP_DEFAULT 0x00000d04 16709 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL_DEFAULT 0x00000000 16710 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS_DEFAULT 0x00000000 16711 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2_DEFAULT 0x00010000 16712 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2_DEFAULT 0x00000000 16713 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2_DEFAULT 0x00000000 16714 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2_DEFAULT 0x0000001e 16715 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2_DEFAULT 0x00000000 16716 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2_DEFAULT 0x00000000 16717 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST_DEFAULT 0x0000c000 16718 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL_DEFAULT 0x00000082 16719 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 16720 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 16721 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_DEFAULT 0x00000000 16722 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_DEFAULT 0x00000000 16723 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 16724 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64_DEFAULT 0x00000000 16725 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_DEFAULT 0x00000000 16726 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64_DEFAULT 0x00000000 16727 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST_DEFAULT 0x00000000 16728 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 16729 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE_DEFAULT 0x00000000 16730 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA_DEFAULT 0x00000000 16731 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 16732 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 16733 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 16734 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 16735 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 16736 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 16737 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 16738 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 16739 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 16740 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 16741 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 16742 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 16743 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 16744 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 16745 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 16746 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 16747 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 16748 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 16749 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 16750 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 16751 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP_DEFAULT 0x00000000 16752 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 16753 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 16754 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP_DEFAULT 0x00000000 16755 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 16756 16757 16758 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp 16759 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID_DEFAULT 0x00000000 16760 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID_DEFAULT 0x00000000 16761 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_COMMAND_DEFAULT 0x00000000 16762 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_STATUS_DEFAULT 0x00000000 16763 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID_DEFAULT 0x00000000 16764 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE_DEFAULT 0x00000000 16765 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS_DEFAULT 0x00000000 16766 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS_DEFAULT 0x00000000 16767 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE_DEFAULT 0x00000000 16768 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LATENCY_DEFAULT 0x00000000 16769 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_HEADER_DEFAULT 0x00000000 16770 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BIST_DEFAULT 0x00000000 16771 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1_DEFAULT 0x00000000 16772 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2_DEFAULT 0x00000000 16773 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3_DEFAULT 0x00000000 16774 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4_DEFAULT 0x00000000 16775 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5_DEFAULT 0x00000000 16776 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6_DEFAULT 0x00000000 16777 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 16778 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID_DEFAULT 0x73101002 16779 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR_DEFAULT 0x00000000 16780 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR_DEFAULT 0x00000048 16781 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE_DEFAULT 0x00000000 16782 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN_DEFAULT 0x00000000 16783 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT_DEFAULT 0x00000000 16784 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY_DEFAULT 0x00000000 16785 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 16786 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_DEFAULT 0x00000002 16787 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP_DEFAULT 0x00000000 16788 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL_DEFAULT 0x00000000 16789 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS_DEFAULT 0x00000000 16790 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP_DEFAULT 0x00000d04 16791 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL_DEFAULT 0x00000000 16792 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS_DEFAULT 0x00000000 16793 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2_DEFAULT 0x00010000 16794 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2_DEFAULT 0x00000000 16795 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2_DEFAULT 0x00000000 16796 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2_DEFAULT 0x0000001e 16797 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2_DEFAULT 0x00000000 16798 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2_DEFAULT 0x00000000 16799 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST_DEFAULT 0x0000c000 16800 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL_DEFAULT 0x00000082 16801 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 16802 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 16803 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_DEFAULT 0x00000000 16804 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_DEFAULT 0x00000000 16805 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 16806 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64_DEFAULT 0x00000000 16807 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_DEFAULT 0x00000000 16808 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64_DEFAULT 0x00000000 16809 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST_DEFAULT 0x00000000 16810 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 16811 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE_DEFAULT 0x00000000 16812 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA_DEFAULT 0x00000000 16813 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 16814 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 16815 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 16816 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 16817 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 16818 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 16819 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 16820 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 16821 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 16822 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 16823 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 16824 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 16825 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 16826 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 16827 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 16828 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 16829 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 16830 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 16831 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 16832 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 16833 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP_DEFAULT 0x00000000 16834 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 16835 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 16836 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP_DEFAULT 0x00000000 16837 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 16838 16839 16840 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp 16841 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID_DEFAULT 0x00000000 16842 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID_DEFAULT 0x00000000 16843 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_COMMAND_DEFAULT 0x00000000 16844 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_STATUS_DEFAULT 0x00000000 16845 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID_DEFAULT 0x00000000 16846 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE_DEFAULT 0x00000000 16847 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS_DEFAULT 0x00000000 16848 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS_DEFAULT 0x00000000 16849 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE_DEFAULT 0x00000000 16850 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LATENCY_DEFAULT 0x00000000 16851 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_HEADER_DEFAULT 0x00000000 16852 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BIST_DEFAULT 0x00000000 16853 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1_DEFAULT 0x00000000 16854 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2_DEFAULT 0x00000000 16855 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3_DEFAULT 0x00000000 16856 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4_DEFAULT 0x00000000 16857 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5_DEFAULT 0x00000000 16858 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6_DEFAULT 0x00000000 16859 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 16860 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID_DEFAULT 0x73101002 16861 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR_DEFAULT 0x00000000 16862 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR_DEFAULT 0x00000048 16863 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE_DEFAULT 0x00000000 16864 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN_DEFAULT 0x00000000 16865 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT_DEFAULT 0x00000000 16866 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY_DEFAULT 0x00000000 16867 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 16868 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_DEFAULT 0x00000002 16869 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP_DEFAULT 0x00000000 16870 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL_DEFAULT 0x00000000 16871 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS_DEFAULT 0x00000000 16872 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP_DEFAULT 0x00000d04 16873 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL_DEFAULT 0x00000000 16874 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS_DEFAULT 0x00000000 16875 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2_DEFAULT 0x00010000 16876 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2_DEFAULT 0x00000000 16877 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2_DEFAULT 0x00000000 16878 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2_DEFAULT 0x0000001e 16879 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2_DEFAULT 0x00000000 16880 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2_DEFAULT 0x00000000 16881 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST_DEFAULT 0x0000c000 16882 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL_DEFAULT 0x00000082 16883 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 16884 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 16885 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_DEFAULT 0x00000000 16886 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_DEFAULT 0x00000000 16887 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 16888 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64_DEFAULT 0x00000000 16889 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_DEFAULT 0x00000000 16890 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64_DEFAULT 0x00000000 16891 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST_DEFAULT 0x00000000 16892 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 16893 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE_DEFAULT 0x00000000 16894 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA_DEFAULT 0x00000000 16895 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 16896 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 16897 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 16898 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 16899 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 16900 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 16901 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 16902 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 16903 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 16904 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 16905 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 16906 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 16907 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 16908 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 16909 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 16910 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 16911 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 16912 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 16913 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 16914 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 16915 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP_DEFAULT 0x00000000 16916 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 16917 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 16918 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP_DEFAULT 0x00000000 16919 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 16920 16921 16922 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf16_bifcfgdecp 16923 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_VENDOR_ID_DEFAULT 0x00000000 16924 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_ID_DEFAULT 0x00000000 16925 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_COMMAND_DEFAULT 0x00000000 16926 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_STATUS_DEFAULT 0x00000000 16927 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_REVISION_ID_DEFAULT 0x00000000 16928 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PROG_INTERFACE_DEFAULT 0x00000000 16929 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_SUB_CLASS_DEFAULT 0x00000000 16930 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_CLASS_DEFAULT 0x00000000 16931 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_CACHE_LINE_DEFAULT 0x00000000 16932 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_LATENCY_DEFAULT 0x00000000 16933 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_HEADER_DEFAULT 0x00000000 16934 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_BIST_DEFAULT 0x00000000 16935 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_1_DEFAULT 0x00000000 16936 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_2_DEFAULT 0x00000000 16937 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_3_DEFAULT 0x00000000 16938 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_4_DEFAULT 0x00000000 16939 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_5_DEFAULT 0x00000000 16940 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_6_DEFAULT 0x00000000 16941 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 16942 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_ADAPTER_ID_DEFAULT 0x73101002 16943 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_ROM_BASE_ADDR_DEFAULT 0x00000000 16944 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_CAP_PTR_DEFAULT 0x00000048 16945 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_LINE_DEFAULT 0x00000000 16946 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_PIN_DEFAULT 0x00000000 16947 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MIN_GRANT_DEFAULT 0x00000000 16948 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MAX_LATENCY_DEFAULT 0x00000000 16949 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 16950 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP_DEFAULT 0x00000002 16951 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP_DEFAULT 0x00000000 16952 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL_DEFAULT 0x00000000 16953 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS_DEFAULT 0x00000000 16954 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP_DEFAULT 0x00000d04 16955 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL_DEFAULT 0x00000000 16956 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS_DEFAULT 0x00000000 16957 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2_DEFAULT 0x00010000 16958 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2_DEFAULT 0x00000000 16959 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS2_DEFAULT 0x00000000 16960 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2_DEFAULT 0x0000001e 16961 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2_DEFAULT 0x00000000 16962 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2_DEFAULT 0x00000000 16963 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_CAP_LIST_DEFAULT 0x0000c000 16964 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL_DEFAULT 0x00000082 16965 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 16966 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 16967 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA_DEFAULT 0x00000000 16968 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK_DEFAULT 0x00000000 16969 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 16970 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK_64_DEFAULT 0x00000000 16971 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING_DEFAULT 0x00000000 16972 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING_64_DEFAULT 0x00000000 16973 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSIX_CAP_LIST_DEFAULT 0x00000000 16974 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 16975 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSIX_TABLE_DEFAULT 0x00000000 16976 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSIX_PBA_DEFAULT 0x00000000 16977 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 16978 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 16979 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 16980 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 16981 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 16982 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 16983 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 16984 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 16985 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 16986 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 16987 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 16988 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 16989 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 16990 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 16991 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 16992 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 16993 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 16994 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 16995 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 16996 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 16997 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP_DEFAULT 0x00000000 16998 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 16999 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 17000 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP_DEFAULT 0x00000000 17001 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 17002 17003 17004 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf17_bifcfgdecp 17005 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_VENDOR_ID_DEFAULT 0x00000000 17006 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_ID_DEFAULT 0x00000000 17007 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_COMMAND_DEFAULT 0x00000000 17008 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_STATUS_DEFAULT 0x00000000 17009 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_REVISION_ID_DEFAULT 0x00000000 17010 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PROG_INTERFACE_DEFAULT 0x00000000 17011 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_SUB_CLASS_DEFAULT 0x00000000 17012 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_CLASS_DEFAULT 0x00000000 17013 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_CACHE_LINE_DEFAULT 0x00000000 17014 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_LATENCY_DEFAULT 0x00000000 17015 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_HEADER_DEFAULT 0x00000000 17016 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_BIST_DEFAULT 0x00000000 17017 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_1_DEFAULT 0x00000000 17018 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_2_DEFAULT 0x00000000 17019 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_3_DEFAULT 0x00000000 17020 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_4_DEFAULT 0x00000000 17021 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_5_DEFAULT 0x00000000 17022 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_6_DEFAULT 0x00000000 17023 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 17024 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_ADAPTER_ID_DEFAULT 0x73101002 17025 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_ROM_BASE_ADDR_DEFAULT 0x00000000 17026 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_CAP_PTR_DEFAULT 0x00000048 17027 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_LINE_DEFAULT 0x00000000 17028 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_PIN_DEFAULT 0x00000000 17029 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MIN_GRANT_DEFAULT 0x00000000 17030 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MAX_LATENCY_DEFAULT 0x00000000 17031 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 17032 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP_DEFAULT 0x00000002 17033 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP_DEFAULT 0x00000000 17034 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL_DEFAULT 0x00000000 17035 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS_DEFAULT 0x00000000 17036 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP_DEFAULT 0x00000d04 17037 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL_DEFAULT 0x00000000 17038 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS_DEFAULT 0x00000000 17039 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2_DEFAULT 0x00010000 17040 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2_DEFAULT 0x00000000 17041 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS2_DEFAULT 0x00000000 17042 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2_DEFAULT 0x0000001e 17043 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2_DEFAULT 0x00000000 17044 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2_DEFAULT 0x00000000 17045 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_CAP_LIST_DEFAULT 0x0000c000 17046 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL_DEFAULT 0x00000082 17047 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 17048 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 17049 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA_DEFAULT 0x00000000 17050 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK_DEFAULT 0x00000000 17051 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 17052 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK_64_DEFAULT 0x00000000 17053 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING_DEFAULT 0x00000000 17054 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING_64_DEFAULT 0x00000000 17055 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSIX_CAP_LIST_DEFAULT 0x00000000 17056 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 17057 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSIX_TABLE_DEFAULT 0x00000000 17058 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSIX_PBA_DEFAULT 0x00000000 17059 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 17060 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 17061 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 17062 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 17063 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 17064 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 17065 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 17066 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 17067 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 17068 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 17069 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 17070 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 17071 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 17072 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 17073 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 17074 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 17075 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 17076 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 17077 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 17078 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 17079 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP_DEFAULT 0x00000000 17080 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 17081 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 17082 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP_DEFAULT 0x00000000 17083 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 17084 17085 17086 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf18_bifcfgdecp 17087 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_VENDOR_ID_DEFAULT 0x00000000 17088 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_ID_DEFAULT 0x00000000 17089 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_COMMAND_DEFAULT 0x00000000 17090 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_STATUS_DEFAULT 0x00000000 17091 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_REVISION_ID_DEFAULT 0x00000000 17092 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PROG_INTERFACE_DEFAULT 0x00000000 17093 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_SUB_CLASS_DEFAULT 0x00000000 17094 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_CLASS_DEFAULT 0x00000000 17095 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_CACHE_LINE_DEFAULT 0x00000000 17096 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_LATENCY_DEFAULT 0x00000000 17097 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_HEADER_DEFAULT 0x00000000 17098 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_BIST_DEFAULT 0x00000000 17099 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_1_DEFAULT 0x00000000 17100 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_2_DEFAULT 0x00000000 17101 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_3_DEFAULT 0x00000000 17102 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_4_DEFAULT 0x00000000 17103 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_5_DEFAULT 0x00000000 17104 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_6_DEFAULT 0x00000000 17105 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 17106 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_ADAPTER_ID_DEFAULT 0x73101002 17107 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_ROM_BASE_ADDR_DEFAULT 0x00000000 17108 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_CAP_PTR_DEFAULT 0x00000048 17109 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_LINE_DEFAULT 0x00000000 17110 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_PIN_DEFAULT 0x00000000 17111 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MIN_GRANT_DEFAULT 0x00000000 17112 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MAX_LATENCY_DEFAULT 0x00000000 17113 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 17114 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP_DEFAULT 0x00000002 17115 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP_DEFAULT 0x00000000 17116 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL_DEFAULT 0x00000000 17117 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS_DEFAULT 0x00000000 17118 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP_DEFAULT 0x00000d04 17119 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL_DEFAULT 0x00000000 17120 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS_DEFAULT 0x00000000 17121 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2_DEFAULT 0x00010000 17122 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2_DEFAULT 0x00000000 17123 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS2_DEFAULT 0x00000000 17124 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2_DEFAULT 0x0000001e 17125 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2_DEFAULT 0x00000000 17126 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2_DEFAULT 0x00000000 17127 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_CAP_LIST_DEFAULT 0x0000c000 17128 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL_DEFAULT 0x00000082 17129 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 17130 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 17131 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA_DEFAULT 0x00000000 17132 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK_DEFAULT 0x00000000 17133 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 17134 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK_64_DEFAULT 0x00000000 17135 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING_DEFAULT 0x00000000 17136 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING_64_DEFAULT 0x00000000 17137 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSIX_CAP_LIST_DEFAULT 0x00000000 17138 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 17139 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSIX_TABLE_DEFAULT 0x00000000 17140 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSIX_PBA_DEFAULT 0x00000000 17141 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 17142 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 17143 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 17144 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 17145 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 17146 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 17147 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 17148 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 17149 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 17150 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 17151 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 17152 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 17153 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 17154 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 17155 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 17156 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 17157 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 17158 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 17159 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 17160 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 17161 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP_DEFAULT 0x00000000 17162 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 17163 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 17164 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP_DEFAULT 0x00000000 17165 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 17166 17167 17168 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf19_bifcfgdecp 17169 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_VENDOR_ID_DEFAULT 0x00000000 17170 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_ID_DEFAULT 0x00000000 17171 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_COMMAND_DEFAULT 0x00000000 17172 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_STATUS_DEFAULT 0x00000000 17173 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_REVISION_ID_DEFAULT 0x00000000 17174 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PROG_INTERFACE_DEFAULT 0x00000000 17175 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_SUB_CLASS_DEFAULT 0x00000000 17176 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_CLASS_DEFAULT 0x00000000 17177 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_CACHE_LINE_DEFAULT 0x00000000 17178 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_LATENCY_DEFAULT 0x00000000 17179 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_HEADER_DEFAULT 0x00000000 17180 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_BIST_DEFAULT 0x00000000 17181 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_1_DEFAULT 0x00000000 17182 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_2_DEFAULT 0x00000000 17183 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_3_DEFAULT 0x00000000 17184 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_4_DEFAULT 0x00000000 17185 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_5_DEFAULT 0x00000000 17186 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_6_DEFAULT 0x00000000 17187 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 17188 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_ADAPTER_ID_DEFAULT 0x73101002 17189 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_ROM_BASE_ADDR_DEFAULT 0x00000000 17190 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_CAP_PTR_DEFAULT 0x00000048 17191 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_LINE_DEFAULT 0x00000000 17192 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_PIN_DEFAULT 0x00000000 17193 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MIN_GRANT_DEFAULT 0x00000000 17194 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MAX_LATENCY_DEFAULT 0x00000000 17195 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 17196 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP_DEFAULT 0x00000002 17197 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP_DEFAULT 0x00000000 17198 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL_DEFAULT 0x00000000 17199 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS_DEFAULT 0x00000000 17200 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP_DEFAULT 0x00000d04 17201 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL_DEFAULT 0x00000000 17202 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS_DEFAULT 0x00000000 17203 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2_DEFAULT 0x00010000 17204 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2_DEFAULT 0x00000000 17205 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS2_DEFAULT 0x00000000 17206 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2_DEFAULT 0x0000001e 17207 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2_DEFAULT 0x00000000 17208 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2_DEFAULT 0x00000000 17209 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_CAP_LIST_DEFAULT 0x0000c000 17210 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL_DEFAULT 0x00000082 17211 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 17212 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 17213 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA_DEFAULT 0x00000000 17214 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK_DEFAULT 0x00000000 17215 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 17216 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK_64_DEFAULT 0x00000000 17217 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING_DEFAULT 0x00000000 17218 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING_64_DEFAULT 0x00000000 17219 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSIX_CAP_LIST_DEFAULT 0x00000000 17220 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 17221 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSIX_TABLE_DEFAULT 0x00000000 17222 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSIX_PBA_DEFAULT 0x00000000 17223 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 17224 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 17225 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 17226 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 17227 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 17228 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 17229 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 17230 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 17231 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 17232 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 17233 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 17234 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 17235 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 17236 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 17237 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 17238 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 17239 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 17240 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 17241 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 17242 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 17243 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP_DEFAULT 0x00000000 17244 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 17245 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 17246 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP_DEFAULT 0x00000000 17247 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 17248 17249 17250 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf20_bifcfgdecp 17251 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_VENDOR_ID_DEFAULT 0x00000000 17252 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_ID_DEFAULT 0x00000000 17253 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_COMMAND_DEFAULT 0x00000000 17254 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_STATUS_DEFAULT 0x00000000 17255 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_REVISION_ID_DEFAULT 0x00000000 17256 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PROG_INTERFACE_DEFAULT 0x00000000 17257 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_SUB_CLASS_DEFAULT 0x00000000 17258 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_CLASS_DEFAULT 0x00000000 17259 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_CACHE_LINE_DEFAULT 0x00000000 17260 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_LATENCY_DEFAULT 0x00000000 17261 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_HEADER_DEFAULT 0x00000000 17262 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_BIST_DEFAULT 0x00000000 17263 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_1_DEFAULT 0x00000000 17264 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_2_DEFAULT 0x00000000 17265 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_3_DEFAULT 0x00000000 17266 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_4_DEFAULT 0x00000000 17267 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_5_DEFAULT 0x00000000 17268 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_6_DEFAULT 0x00000000 17269 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 17270 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_ADAPTER_ID_DEFAULT 0x73101002 17271 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_ROM_BASE_ADDR_DEFAULT 0x00000000 17272 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_CAP_PTR_DEFAULT 0x00000048 17273 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_LINE_DEFAULT 0x00000000 17274 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_PIN_DEFAULT 0x00000000 17275 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MIN_GRANT_DEFAULT 0x00000000 17276 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MAX_LATENCY_DEFAULT 0x00000000 17277 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 17278 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP_DEFAULT 0x00000002 17279 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP_DEFAULT 0x00000000 17280 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL_DEFAULT 0x00000000 17281 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS_DEFAULT 0x00000000 17282 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP_DEFAULT 0x00000d04 17283 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL_DEFAULT 0x00000000 17284 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS_DEFAULT 0x00000000 17285 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2_DEFAULT 0x00010000 17286 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2_DEFAULT 0x00000000 17287 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS2_DEFAULT 0x00000000 17288 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2_DEFAULT 0x0000001e 17289 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2_DEFAULT 0x00000000 17290 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2_DEFAULT 0x00000000 17291 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_CAP_LIST_DEFAULT 0x0000c000 17292 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL_DEFAULT 0x00000082 17293 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 17294 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 17295 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA_DEFAULT 0x00000000 17296 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK_DEFAULT 0x00000000 17297 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 17298 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK_64_DEFAULT 0x00000000 17299 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING_DEFAULT 0x00000000 17300 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING_64_DEFAULT 0x00000000 17301 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSIX_CAP_LIST_DEFAULT 0x00000000 17302 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 17303 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSIX_TABLE_DEFAULT 0x00000000 17304 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSIX_PBA_DEFAULT 0x00000000 17305 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 17306 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 17307 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 17308 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 17309 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 17310 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 17311 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 17312 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 17313 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 17314 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 17315 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 17316 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 17317 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 17318 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 17319 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 17320 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 17321 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 17322 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 17323 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 17324 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 17325 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP_DEFAULT 0x00000000 17326 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 17327 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 17328 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP_DEFAULT 0x00000000 17329 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 17330 17331 17332 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf21_bifcfgdecp 17333 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_VENDOR_ID_DEFAULT 0x00000000 17334 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_ID_DEFAULT 0x00000000 17335 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_COMMAND_DEFAULT 0x00000000 17336 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_STATUS_DEFAULT 0x00000000 17337 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_REVISION_ID_DEFAULT 0x00000000 17338 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PROG_INTERFACE_DEFAULT 0x00000000 17339 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_SUB_CLASS_DEFAULT 0x00000000 17340 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_CLASS_DEFAULT 0x00000000 17341 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_CACHE_LINE_DEFAULT 0x00000000 17342 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_LATENCY_DEFAULT 0x00000000 17343 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_HEADER_DEFAULT 0x00000000 17344 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_BIST_DEFAULT 0x00000000 17345 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_1_DEFAULT 0x00000000 17346 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_2_DEFAULT 0x00000000 17347 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_3_DEFAULT 0x00000000 17348 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_4_DEFAULT 0x00000000 17349 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_5_DEFAULT 0x00000000 17350 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_6_DEFAULT 0x00000000 17351 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 17352 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_ADAPTER_ID_DEFAULT 0x73101002 17353 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_ROM_BASE_ADDR_DEFAULT 0x00000000 17354 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_CAP_PTR_DEFAULT 0x00000048 17355 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_LINE_DEFAULT 0x00000000 17356 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_PIN_DEFAULT 0x00000000 17357 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MIN_GRANT_DEFAULT 0x00000000 17358 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MAX_LATENCY_DEFAULT 0x00000000 17359 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 17360 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP_DEFAULT 0x00000002 17361 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP_DEFAULT 0x00000000 17362 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL_DEFAULT 0x00000000 17363 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS_DEFAULT 0x00000000 17364 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP_DEFAULT 0x00000d04 17365 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL_DEFAULT 0x00000000 17366 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS_DEFAULT 0x00000000 17367 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2_DEFAULT 0x00010000 17368 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2_DEFAULT 0x00000000 17369 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS2_DEFAULT 0x00000000 17370 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2_DEFAULT 0x0000001e 17371 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2_DEFAULT 0x00000000 17372 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2_DEFAULT 0x00000000 17373 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_CAP_LIST_DEFAULT 0x0000c000 17374 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL_DEFAULT 0x00000082 17375 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 17376 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 17377 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA_DEFAULT 0x00000000 17378 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK_DEFAULT 0x00000000 17379 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 17380 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK_64_DEFAULT 0x00000000 17381 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING_DEFAULT 0x00000000 17382 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING_64_DEFAULT 0x00000000 17383 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSIX_CAP_LIST_DEFAULT 0x00000000 17384 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 17385 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSIX_TABLE_DEFAULT 0x00000000 17386 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSIX_PBA_DEFAULT 0x00000000 17387 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 17388 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 17389 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 17390 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 17391 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 17392 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 17393 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 17394 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 17395 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 17396 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 17397 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 17398 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 17399 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 17400 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 17401 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 17402 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 17403 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 17404 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 17405 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 17406 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 17407 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP_DEFAULT 0x00000000 17408 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 17409 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 17410 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP_DEFAULT 0x00000000 17411 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 17412 17413 17414 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf22_bifcfgdecp 17415 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_VENDOR_ID_DEFAULT 0x00000000 17416 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_ID_DEFAULT 0x00000000 17417 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_COMMAND_DEFAULT 0x00000000 17418 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_STATUS_DEFAULT 0x00000000 17419 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_REVISION_ID_DEFAULT 0x00000000 17420 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PROG_INTERFACE_DEFAULT 0x00000000 17421 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_SUB_CLASS_DEFAULT 0x00000000 17422 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_CLASS_DEFAULT 0x00000000 17423 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_CACHE_LINE_DEFAULT 0x00000000 17424 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_LATENCY_DEFAULT 0x00000000 17425 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_HEADER_DEFAULT 0x00000000 17426 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_BIST_DEFAULT 0x00000000 17427 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_1_DEFAULT 0x00000000 17428 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_2_DEFAULT 0x00000000 17429 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_3_DEFAULT 0x00000000 17430 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_4_DEFAULT 0x00000000 17431 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_5_DEFAULT 0x00000000 17432 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_6_DEFAULT 0x00000000 17433 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 17434 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_ADAPTER_ID_DEFAULT 0x73101002 17435 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_ROM_BASE_ADDR_DEFAULT 0x00000000 17436 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_CAP_PTR_DEFAULT 0x00000048 17437 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_LINE_DEFAULT 0x00000000 17438 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_PIN_DEFAULT 0x00000000 17439 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MIN_GRANT_DEFAULT 0x00000000 17440 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MAX_LATENCY_DEFAULT 0x00000000 17441 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 17442 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP_DEFAULT 0x00000002 17443 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP_DEFAULT 0x00000000 17444 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL_DEFAULT 0x00000000 17445 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS_DEFAULT 0x00000000 17446 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP_DEFAULT 0x00000d04 17447 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL_DEFAULT 0x00000000 17448 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS_DEFAULT 0x00000000 17449 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2_DEFAULT 0x00010000 17450 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2_DEFAULT 0x00000000 17451 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS2_DEFAULT 0x00000000 17452 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2_DEFAULT 0x0000001e 17453 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2_DEFAULT 0x00000000 17454 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2_DEFAULT 0x00000000 17455 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_CAP_LIST_DEFAULT 0x0000c000 17456 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL_DEFAULT 0x00000082 17457 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 17458 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 17459 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA_DEFAULT 0x00000000 17460 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK_DEFAULT 0x00000000 17461 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 17462 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK_64_DEFAULT 0x00000000 17463 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING_DEFAULT 0x00000000 17464 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING_64_DEFAULT 0x00000000 17465 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSIX_CAP_LIST_DEFAULT 0x00000000 17466 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 17467 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSIX_TABLE_DEFAULT 0x00000000 17468 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSIX_PBA_DEFAULT 0x00000000 17469 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 17470 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 17471 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 17472 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 17473 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 17474 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 17475 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 17476 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 17477 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 17478 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 17479 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 17480 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 17481 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 17482 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 17483 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 17484 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 17485 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 17486 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 17487 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 17488 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 17489 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP_DEFAULT 0x00000000 17490 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 17491 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 17492 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP_DEFAULT 0x00000000 17493 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 17494 17495 17496 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf23_bifcfgdecp 17497 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_VENDOR_ID_DEFAULT 0x00000000 17498 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_ID_DEFAULT 0x00000000 17499 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_COMMAND_DEFAULT 0x00000000 17500 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_STATUS_DEFAULT 0x00000000 17501 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_REVISION_ID_DEFAULT 0x00000000 17502 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PROG_INTERFACE_DEFAULT 0x00000000 17503 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_SUB_CLASS_DEFAULT 0x00000000 17504 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_CLASS_DEFAULT 0x00000000 17505 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_CACHE_LINE_DEFAULT 0x00000000 17506 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_LATENCY_DEFAULT 0x00000000 17507 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_HEADER_DEFAULT 0x00000000 17508 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_BIST_DEFAULT 0x00000000 17509 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_1_DEFAULT 0x00000000 17510 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_2_DEFAULT 0x00000000 17511 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_3_DEFAULT 0x00000000 17512 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_4_DEFAULT 0x00000000 17513 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_5_DEFAULT 0x00000000 17514 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_6_DEFAULT 0x00000000 17515 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 17516 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_ADAPTER_ID_DEFAULT 0x73101002 17517 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_ROM_BASE_ADDR_DEFAULT 0x00000000 17518 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_CAP_PTR_DEFAULT 0x00000048 17519 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_LINE_DEFAULT 0x00000000 17520 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_PIN_DEFAULT 0x00000000 17521 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MIN_GRANT_DEFAULT 0x00000000 17522 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MAX_LATENCY_DEFAULT 0x00000000 17523 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 17524 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP_DEFAULT 0x00000002 17525 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP_DEFAULT 0x00000000 17526 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL_DEFAULT 0x00000000 17527 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS_DEFAULT 0x00000000 17528 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP_DEFAULT 0x00000d04 17529 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL_DEFAULT 0x00000000 17530 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS_DEFAULT 0x00000000 17531 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2_DEFAULT 0x00010000 17532 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2_DEFAULT 0x00000000 17533 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS2_DEFAULT 0x00000000 17534 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2_DEFAULT 0x0000001e 17535 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2_DEFAULT 0x00000000 17536 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2_DEFAULT 0x00000000 17537 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_CAP_LIST_DEFAULT 0x0000c000 17538 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL_DEFAULT 0x00000082 17539 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 17540 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 17541 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA_DEFAULT 0x00000000 17542 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK_DEFAULT 0x00000000 17543 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 17544 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK_64_DEFAULT 0x00000000 17545 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING_DEFAULT 0x00000000 17546 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING_64_DEFAULT 0x00000000 17547 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSIX_CAP_LIST_DEFAULT 0x00000000 17548 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 17549 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSIX_TABLE_DEFAULT 0x00000000 17550 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSIX_PBA_DEFAULT 0x00000000 17551 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 17552 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 17553 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 17554 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 17555 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 17556 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 17557 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 17558 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 17559 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 17560 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 17561 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 17562 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 17563 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 17564 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 17565 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 17566 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 17567 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 17568 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 17569 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 17570 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 17571 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP_DEFAULT 0x00000000 17572 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 17573 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 17574 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP_DEFAULT 0x00000000 17575 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 17576 17577 17578 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf24_bifcfgdecp 17579 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_VENDOR_ID_DEFAULT 0x00000000 17580 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_ID_DEFAULT 0x00000000 17581 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_COMMAND_DEFAULT 0x00000000 17582 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_STATUS_DEFAULT 0x00000000 17583 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_REVISION_ID_DEFAULT 0x00000000 17584 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PROG_INTERFACE_DEFAULT 0x00000000 17585 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_SUB_CLASS_DEFAULT 0x00000000 17586 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_CLASS_DEFAULT 0x00000000 17587 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_CACHE_LINE_DEFAULT 0x00000000 17588 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_LATENCY_DEFAULT 0x00000000 17589 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_HEADER_DEFAULT 0x00000000 17590 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_BIST_DEFAULT 0x00000000 17591 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_1_DEFAULT 0x00000000 17592 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_2_DEFAULT 0x00000000 17593 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_3_DEFAULT 0x00000000 17594 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_4_DEFAULT 0x00000000 17595 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_5_DEFAULT 0x00000000 17596 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_6_DEFAULT 0x00000000 17597 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 17598 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_ADAPTER_ID_DEFAULT 0x73101002 17599 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_ROM_BASE_ADDR_DEFAULT 0x00000000 17600 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_CAP_PTR_DEFAULT 0x00000048 17601 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_LINE_DEFAULT 0x00000000 17602 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_PIN_DEFAULT 0x00000000 17603 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MIN_GRANT_DEFAULT 0x00000000 17604 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MAX_LATENCY_DEFAULT 0x00000000 17605 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 17606 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP_DEFAULT 0x00000002 17607 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP_DEFAULT 0x00000000 17608 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL_DEFAULT 0x00000000 17609 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS_DEFAULT 0x00000000 17610 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP_DEFAULT 0x00000d04 17611 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL_DEFAULT 0x00000000 17612 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS_DEFAULT 0x00000000 17613 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2_DEFAULT 0x00010000 17614 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2_DEFAULT 0x00000000 17615 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS2_DEFAULT 0x00000000 17616 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2_DEFAULT 0x0000001e 17617 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2_DEFAULT 0x00000000 17618 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2_DEFAULT 0x00000000 17619 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_CAP_LIST_DEFAULT 0x0000c000 17620 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL_DEFAULT 0x00000082 17621 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 17622 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 17623 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA_DEFAULT 0x00000000 17624 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK_DEFAULT 0x00000000 17625 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 17626 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK_64_DEFAULT 0x00000000 17627 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING_DEFAULT 0x00000000 17628 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING_64_DEFAULT 0x00000000 17629 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSIX_CAP_LIST_DEFAULT 0x00000000 17630 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 17631 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSIX_TABLE_DEFAULT 0x00000000 17632 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSIX_PBA_DEFAULT 0x00000000 17633 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 17634 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 17635 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 17636 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 17637 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 17638 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 17639 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 17640 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 17641 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 17642 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 17643 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 17644 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 17645 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 17646 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 17647 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 17648 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 17649 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 17650 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 17651 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 17652 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 17653 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP_DEFAULT 0x00000000 17654 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 17655 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 17656 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP_DEFAULT 0x00000000 17657 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 17658 17659 17660 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf25_bifcfgdecp 17661 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_VENDOR_ID_DEFAULT 0x00000000 17662 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_ID_DEFAULT 0x00000000 17663 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_COMMAND_DEFAULT 0x00000000 17664 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_STATUS_DEFAULT 0x00000000 17665 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_REVISION_ID_DEFAULT 0x00000000 17666 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PROG_INTERFACE_DEFAULT 0x00000000 17667 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_SUB_CLASS_DEFAULT 0x00000000 17668 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_CLASS_DEFAULT 0x00000000 17669 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_CACHE_LINE_DEFAULT 0x00000000 17670 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_LATENCY_DEFAULT 0x00000000 17671 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_HEADER_DEFAULT 0x00000000 17672 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_BIST_DEFAULT 0x00000000 17673 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_1_DEFAULT 0x00000000 17674 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_2_DEFAULT 0x00000000 17675 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_3_DEFAULT 0x00000000 17676 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_4_DEFAULT 0x00000000 17677 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_5_DEFAULT 0x00000000 17678 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_6_DEFAULT 0x00000000 17679 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 17680 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_ADAPTER_ID_DEFAULT 0x73101002 17681 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_ROM_BASE_ADDR_DEFAULT 0x00000000 17682 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_CAP_PTR_DEFAULT 0x00000048 17683 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_LINE_DEFAULT 0x00000000 17684 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_PIN_DEFAULT 0x00000000 17685 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MIN_GRANT_DEFAULT 0x00000000 17686 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MAX_LATENCY_DEFAULT 0x00000000 17687 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 17688 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP_DEFAULT 0x00000002 17689 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP_DEFAULT 0x00000000 17690 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL_DEFAULT 0x00000000 17691 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS_DEFAULT 0x00000000 17692 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP_DEFAULT 0x00000d04 17693 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL_DEFAULT 0x00000000 17694 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS_DEFAULT 0x00000000 17695 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2_DEFAULT 0x00010000 17696 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2_DEFAULT 0x00000000 17697 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS2_DEFAULT 0x00000000 17698 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2_DEFAULT 0x0000001e 17699 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2_DEFAULT 0x00000000 17700 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2_DEFAULT 0x00000000 17701 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_CAP_LIST_DEFAULT 0x0000c000 17702 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL_DEFAULT 0x00000082 17703 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 17704 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 17705 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA_DEFAULT 0x00000000 17706 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK_DEFAULT 0x00000000 17707 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 17708 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK_64_DEFAULT 0x00000000 17709 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING_DEFAULT 0x00000000 17710 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING_64_DEFAULT 0x00000000 17711 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSIX_CAP_LIST_DEFAULT 0x00000000 17712 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 17713 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSIX_TABLE_DEFAULT 0x00000000 17714 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSIX_PBA_DEFAULT 0x00000000 17715 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 17716 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 17717 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 17718 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 17719 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 17720 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 17721 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 17722 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 17723 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 17724 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 17725 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 17726 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 17727 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 17728 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 17729 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 17730 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 17731 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 17732 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 17733 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 17734 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 17735 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP_DEFAULT 0x00000000 17736 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 17737 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 17738 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP_DEFAULT 0x00000000 17739 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 17740 17741 17742 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf26_bifcfgdecp 17743 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_VENDOR_ID_DEFAULT 0x00000000 17744 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_ID_DEFAULT 0x00000000 17745 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_COMMAND_DEFAULT 0x00000000 17746 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_STATUS_DEFAULT 0x00000000 17747 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_REVISION_ID_DEFAULT 0x00000000 17748 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PROG_INTERFACE_DEFAULT 0x00000000 17749 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_SUB_CLASS_DEFAULT 0x00000000 17750 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_CLASS_DEFAULT 0x00000000 17751 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_CACHE_LINE_DEFAULT 0x00000000 17752 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_LATENCY_DEFAULT 0x00000000 17753 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_HEADER_DEFAULT 0x00000000 17754 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_BIST_DEFAULT 0x00000000 17755 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_1_DEFAULT 0x00000000 17756 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_2_DEFAULT 0x00000000 17757 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_3_DEFAULT 0x00000000 17758 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_4_DEFAULT 0x00000000 17759 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_5_DEFAULT 0x00000000 17760 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_6_DEFAULT 0x00000000 17761 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 17762 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_ADAPTER_ID_DEFAULT 0x73101002 17763 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_ROM_BASE_ADDR_DEFAULT 0x00000000 17764 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_CAP_PTR_DEFAULT 0x00000048 17765 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_LINE_DEFAULT 0x00000000 17766 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_PIN_DEFAULT 0x00000000 17767 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MIN_GRANT_DEFAULT 0x00000000 17768 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MAX_LATENCY_DEFAULT 0x00000000 17769 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 17770 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP_DEFAULT 0x00000002 17771 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP_DEFAULT 0x00000000 17772 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL_DEFAULT 0x00000000 17773 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS_DEFAULT 0x00000000 17774 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP_DEFAULT 0x00000d04 17775 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL_DEFAULT 0x00000000 17776 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS_DEFAULT 0x00000000 17777 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2_DEFAULT 0x00010000 17778 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2_DEFAULT 0x00000000 17779 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS2_DEFAULT 0x00000000 17780 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2_DEFAULT 0x0000001e 17781 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2_DEFAULT 0x00000000 17782 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2_DEFAULT 0x00000000 17783 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_CAP_LIST_DEFAULT 0x0000c000 17784 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL_DEFAULT 0x00000082 17785 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 17786 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 17787 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA_DEFAULT 0x00000000 17788 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK_DEFAULT 0x00000000 17789 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 17790 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK_64_DEFAULT 0x00000000 17791 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING_DEFAULT 0x00000000 17792 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING_64_DEFAULT 0x00000000 17793 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSIX_CAP_LIST_DEFAULT 0x00000000 17794 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 17795 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSIX_TABLE_DEFAULT 0x00000000 17796 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSIX_PBA_DEFAULT 0x00000000 17797 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 17798 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 17799 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 17800 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 17801 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 17802 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 17803 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 17804 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 17805 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 17806 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 17807 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 17808 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 17809 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 17810 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 17811 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 17812 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 17813 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 17814 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 17815 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 17816 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 17817 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP_DEFAULT 0x00000000 17818 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 17819 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 17820 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP_DEFAULT 0x00000000 17821 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 17822 17823 17824 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf27_bifcfgdecp 17825 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_VENDOR_ID_DEFAULT 0x00000000 17826 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_ID_DEFAULT 0x00000000 17827 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_COMMAND_DEFAULT 0x00000000 17828 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_STATUS_DEFAULT 0x00000000 17829 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_REVISION_ID_DEFAULT 0x00000000 17830 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PROG_INTERFACE_DEFAULT 0x00000000 17831 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_SUB_CLASS_DEFAULT 0x00000000 17832 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_CLASS_DEFAULT 0x00000000 17833 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_CACHE_LINE_DEFAULT 0x00000000 17834 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_LATENCY_DEFAULT 0x00000000 17835 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_HEADER_DEFAULT 0x00000000 17836 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_BIST_DEFAULT 0x00000000 17837 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_1_DEFAULT 0x00000000 17838 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_2_DEFAULT 0x00000000 17839 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_3_DEFAULT 0x00000000 17840 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_4_DEFAULT 0x00000000 17841 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_5_DEFAULT 0x00000000 17842 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_6_DEFAULT 0x00000000 17843 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 17844 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_ADAPTER_ID_DEFAULT 0x73101002 17845 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_ROM_BASE_ADDR_DEFAULT 0x00000000 17846 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_CAP_PTR_DEFAULT 0x00000048 17847 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_LINE_DEFAULT 0x00000000 17848 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_PIN_DEFAULT 0x00000000 17849 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MIN_GRANT_DEFAULT 0x00000000 17850 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MAX_LATENCY_DEFAULT 0x00000000 17851 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 17852 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP_DEFAULT 0x00000002 17853 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP_DEFAULT 0x00000000 17854 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL_DEFAULT 0x00000000 17855 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS_DEFAULT 0x00000000 17856 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP_DEFAULT 0x00000d04 17857 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL_DEFAULT 0x00000000 17858 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS_DEFAULT 0x00000000 17859 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2_DEFAULT 0x00010000 17860 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2_DEFAULT 0x00000000 17861 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS2_DEFAULT 0x00000000 17862 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2_DEFAULT 0x0000001e 17863 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2_DEFAULT 0x00000000 17864 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2_DEFAULT 0x00000000 17865 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_CAP_LIST_DEFAULT 0x0000c000 17866 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL_DEFAULT 0x00000082 17867 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 17868 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 17869 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA_DEFAULT 0x00000000 17870 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK_DEFAULT 0x00000000 17871 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 17872 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK_64_DEFAULT 0x00000000 17873 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING_DEFAULT 0x00000000 17874 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING_64_DEFAULT 0x00000000 17875 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSIX_CAP_LIST_DEFAULT 0x00000000 17876 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 17877 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSIX_TABLE_DEFAULT 0x00000000 17878 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSIX_PBA_DEFAULT 0x00000000 17879 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 17880 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 17881 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 17882 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 17883 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 17884 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 17885 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 17886 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 17887 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 17888 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 17889 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 17890 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 17891 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 17892 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 17893 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 17894 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 17895 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 17896 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 17897 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 17898 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 17899 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP_DEFAULT 0x00000000 17900 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 17901 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 17902 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP_DEFAULT 0x00000000 17903 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 17904 17905 17906 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf28_bifcfgdecp 17907 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_VENDOR_ID_DEFAULT 0x00000000 17908 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_ID_DEFAULT 0x00000000 17909 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_COMMAND_DEFAULT 0x00000000 17910 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_STATUS_DEFAULT 0x00000000 17911 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_REVISION_ID_DEFAULT 0x00000000 17912 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PROG_INTERFACE_DEFAULT 0x00000000 17913 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_SUB_CLASS_DEFAULT 0x00000000 17914 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_CLASS_DEFAULT 0x00000000 17915 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_CACHE_LINE_DEFAULT 0x00000000 17916 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_LATENCY_DEFAULT 0x00000000 17917 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_HEADER_DEFAULT 0x00000000 17918 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_BIST_DEFAULT 0x00000000 17919 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_1_DEFAULT 0x00000000 17920 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_2_DEFAULT 0x00000000 17921 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_3_DEFAULT 0x00000000 17922 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_4_DEFAULT 0x00000000 17923 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_5_DEFAULT 0x00000000 17924 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_6_DEFAULT 0x00000000 17925 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 17926 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_ADAPTER_ID_DEFAULT 0x73101002 17927 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_ROM_BASE_ADDR_DEFAULT 0x00000000 17928 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_CAP_PTR_DEFAULT 0x00000048 17929 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_LINE_DEFAULT 0x00000000 17930 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_PIN_DEFAULT 0x00000000 17931 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MIN_GRANT_DEFAULT 0x00000000 17932 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MAX_LATENCY_DEFAULT 0x00000000 17933 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 17934 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP_DEFAULT 0x00000002 17935 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP_DEFAULT 0x00000000 17936 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL_DEFAULT 0x00000000 17937 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS_DEFAULT 0x00000000 17938 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP_DEFAULT 0x00000d04 17939 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL_DEFAULT 0x00000000 17940 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS_DEFAULT 0x00000000 17941 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2_DEFAULT 0x00010000 17942 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2_DEFAULT 0x00000000 17943 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS2_DEFAULT 0x00000000 17944 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2_DEFAULT 0x0000001e 17945 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2_DEFAULT 0x00000000 17946 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2_DEFAULT 0x00000000 17947 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_CAP_LIST_DEFAULT 0x0000c000 17948 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL_DEFAULT 0x00000082 17949 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 17950 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 17951 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA_DEFAULT 0x00000000 17952 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK_DEFAULT 0x00000000 17953 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 17954 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK_64_DEFAULT 0x00000000 17955 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING_DEFAULT 0x00000000 17956 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING_64_DEFAULT 0x00000000 17957 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSIX_CAP_LIST_DEFAULT 0x00000000 17958 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 17959 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSIX_TABLE_DEFAULT 0x00000000 17960 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSIX_PBA_DEFAULT 0x00000000 17961 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 17962 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 17963 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 17964 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 17965 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 17966 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 17967 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 17968 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 17969 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 17970 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 17971 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 17972 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 17973 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 17974 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 17975 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 17976 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 17977 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 17978 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 17979 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 17980 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 17981 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP_DEFAULT 0x00000000 17982 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 17983 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 17984 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP_DEFAULT 0x00000000 17985 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 17986 17987 17988 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf29_bifcfgdecp 17989 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_VENDOR_ID_DEFAULT 0x00000000 17990 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_ID_DEFAULT 0x00000000 17991 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_COMMAND_DEFAULT 0x00000000 17992 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_STATUS_DEFAULT 0x00000000 17993 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_REVISION_ID_DEFAULT 0x00000000 17994 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PROG_INTERFACE_DEFAULT 0x00000000 17995 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_SUB_CLASS_DEFAULT 0x00000000 17996 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_CLASS_DEFAULT 0x00000000 17997 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_CACHE_LINE_DEFAULT 0x00000000 17998 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_LATENCY_DEFAULT 0x00000000 17999 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_HEADER_DEFAULT 0x00000000 18000 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_BIST_DEFAULT 0x00000000 18001 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_1_DEFAULT 0x00000000 18002 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_2_DEFAULT 0x00000000 18003 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_3_DEFAULT 0x00000000 18004 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_4_DEFAULT 0x00000000 18005 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_5_DEFAULT 0x00000000 18006 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_6_DEFAULT 0x00000000 18007 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 18008 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_ADAPTER_ID_DEFAULT 0x73101002 18009 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_ROM_BASE_ADDR_DEFAULT 0x00000000 18010 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_CAP_PTR_DEFAULT 0x00000048 18011 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_LINE_DEFAULT 0x00000000 18012 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_PIN_DEFAULT 0x00000000 18013 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MIN_GRANT_DEFAULT 0x00000000 18014 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MAX_LATENCY_DEFAULT 0x00000000 18015 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 18016 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP_DEFAULT 0x00000002 18017 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP_DEFAULT 0x00000000 18018 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL_DEFAULT 0x00000000 18019 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS_DEFAULT 0x00000000 18020 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP_DEFAULT 0x00000d04 18021 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL_DEFAULT 0x00000000 18022 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS_DEFAULT 0x00000000 18023 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2_DEFAULT 0x00010000 18024 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2_DEFAULT 0x00000000 18025 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS2_DEFAULT 0x00000000 18026 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2_DEFAULT 0x0000001e 18027 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2_DEFAULT 0x00000000 18028 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2_DEFAULT 0x00000000 18029 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_CAP_LIST_DEFAULT 0x0000c000 18030 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL_DEFAULT 0x00000082 18031 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 18032 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 18033 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA_DEFAULT 0x00000000 18034 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK_DEFAULT 0x00000000 18035 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 18036 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK_64_DEFAULT 0x00000000 18037 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING_DEFAULT 0x00000000 18038 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING_64_DEFAULT 0x00000000 18039 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSIX_CAP_LIST_DEFAULT 0x00000000 18040 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 18041 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSIX_TABLE_DEFAULT 0x00000000 18042 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSIX_PBA_DEFAULT 0x00000000 18043 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 18044 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 18045 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 18046 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 18047 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 18048 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 18049 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 18050 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 18051 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 18052 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 18053 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 18054 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 18055 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 18056 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 18057 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 18058 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 18059 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 18060 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 18061 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 18062 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 18063 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP_DEFAULT 0x00000000 18064 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 18065 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 18066 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP_DEFAULT 0x00000000 18067 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 18068 18069 18070 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf30_bifcfgdecp 18071 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_VENDOR_ID_DEFAULT 0x00000000 18072 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_ID_DEFAULT 0x00000000 18073 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_COMMAND_DEFAULT 0x00000000 18074 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_STATUS_DEFAULT 0x00000000 18075 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_REVISION_ID_DEFAULT 0x00000000 18076 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PROG_INTERFACE_DEFAULT 0x00000000 18077 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_SUB_CLASS_DEFAULT 0x00000000 18078 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_CLASS_DEFAULT 0x00000000 18079 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_CACHE_LINE_DEFAULT 0x00000000 18080 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_LATENCY_DEFAULT 0x00000000 18081 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_HEADER_DEFAULT 0x00000000 18082 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_BIST_DEFAULT 0x00000000 18083 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_1_DEFAULT 0x00000000 18084 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_2_DEFAULT 0x00000000 18085 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_3_DEFAULT 0x00000000 18086 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_4_DEFAULT 0x00000000 18087 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_5_DEFAULT 0x00000000 18088 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_6_DEFAULT 0x00000000 18089 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_CARDBUS_CIS_PTR_DEFAULT 0x00000000 18090 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_ADAPTER_ID_DEFAULT 0x73101002 18091 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_ROM_BASE_ADDR_DEFAULT 0x00000000 18092 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_CAP_PTR_DEFAULT 0x00000048 18093 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_LINE_DEFAULT 0x00000000 18094 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_PIN_DEFAULT 0x00000000 18095 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MIN_GRANT_DEFAULT 0x00000000 18096 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MAX_LATENCY_DEFAULT 0x00000000 18097 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 18098 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP_DEFAULT 0x00000002 18099 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP_DEFAULT 0x00000000 18100 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL_DEFAULT 0x00000000 18101 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS_DEFAULT 0x00000000 18102 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP_DEFAULT 0x00000d04 18103 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL_DEFAULT 0x00000000 18104 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS_DEFAULT 0x00000000 18105 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2_DEFAULT 0x00010000 18106 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2_DEFAULT 0x00000000 18107 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS2_DEFAULT 0x00000000 18108 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2_DEFAULT 0x0000001e 18109 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2_DEFAULT 0x00000000 18110 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2_DEFAULT 0x00000000 18111 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_CAP_LIST_DEFAULT 0x0000c000 18112 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL_DEFAULT 0x00000082 18113 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 18114 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 18115 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA_DEFAULT 0x00000000 18116 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK_DEFAULT 0x00000000 18117 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 18118 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK_64_DEFAULT 0x00000000 18119 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING_DEFAULT 0x00000000 18120 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING_64_DEFAULT 0x00000000 18121 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSIX_CAP_LIST_DEFAULT 0x00000000 18122 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 18123 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSIX_TABLE_DEFAULT 0x00000000 18124 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSIX_PBA_DEFAULT 0x00000000 18125 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 18126 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 18127 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 18128 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 18129 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 18130 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 18131 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 18132 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00000000 18133 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 18134 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00000000 18135 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 18136 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 18137 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 18138 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 18139 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 18140 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 18141 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 18142 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 18143 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 18144 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 18145 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP_DEFAULT 0x00000000 18146 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 18147 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x00000000 18148 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP_DEFAULT 0x00000000 18149 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 18150 18151 18152 // addressBlock: nbio_nbif0_rcc_shadow_reg_shadowdec 18153 #define cfgSHADOW_COMMAND_DEFAULT 0x00000000 18154 #define cfgSHADOW_BASE_ADDR_1_DEFAULT 0x00000000 18155 #define cfgSHADOW_BASE_ADDR_2_DEFAULT 0x00000000 18156 #define cfgSHADOW_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 18157 #define cfgSHADOW_IO_BASE_LIMIT_DEFAULT 0x00000000 18158 #define cfgSHADOW_MEM_BASE_LIMIT_DEFAULT 0x00000000 18159 #define cfgSHADOW_PREF_BASE_LIMIT_DEFAULT 0x00000000 18160 #define cfgSHADOW_PREF_BASE_UPPER_DEFAULT 0x00000000 18161 #define cfgSHADOW_PREF_LIMIT_UPPER_DEFAULT 0x00000000 18162 #define cfgSHADOW_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 18163 #define cfgSHADOW_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 18164 #define cfgSUC_INDEX_DEFAULT 0x00000000 18165 #define cfgSUC_DATA_DEFAULT 0x00000000 18166 18167 18168 // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC 18169 #define cfgBIF_BX_PF1_MM_INDEX_DEFAULT 0x00000000 18170 #define cfgBIF_BX_PF1_MM_DATA_DEFAULT 0x00000000 18171 #define cfgBIF_BX_PF1_MM_INDEX_HI_DEFAULT 0x00000000 18172 18173 18174 // addressBlock: nbio_nbif0_bif_bx_SYSDEC 18175 #define cfgSYSHUB_INDEX_OVLP_DEFAULT 0x00000000 18176 #define cfgSYSHUB_DATA_OVLP_DEFAULT 0x00000000 18177 #define cfgPCIE_INDEX_DEFAULT 0x00000000 18178 #define cfgPCIE_DATA_DEFAULT 0x00000000 18179 #define cfgPCIE_INDEX2_DEFAULT 0x00000000 18180 #define cfgPCIE_DATA2_DEFAULT 0x00000000 18181 #define cfgSBIOS_SCRATCH_0_DEFAULT 0x00000000 18182 #define cfgSBIOS_SCRATCH_1_DEFAULT 0x00000000 18183 #define cfgSBIOS_SCRATCH_2_DEFAULT 0x00000000 18184 #define cfgSBIOS_SCRATCH_3_DEFAULT 0x00000000 18185 #define cfgBIOS_SCRATCH_0_DEFAULT 0x00000000 18186 #define cfgBIOS_SCRATCH_1_DEFAULT 0x00000000 18187 #define cfgBIOS_SCRATCH_2_DEFAULT 0x00000000 18188 #define cfgBIOS_SCRATCH_3_DEFAULT 0x00000000 18189 #define cfgBIOS_SCRATCH_4_DEFAULT 0x00000000 18190 #define cfgBIOS_SCRATCH_5_DEFAULT 0x00000000 18191 #define cfgBIOS_SCRATCH_6_DEFAULT 0x00000000 18192 #define cfgBIOS_SCRATCH_7_DEFAULT 0x00000000 18193 #define cfgBIOS_SCRATCH_8_DEFAULT 0x00000000 18194 #define cfgBIOS_SCRATCH_9_DEFAULT 0x00000000 18195 #define cfgBIOS_SCRATCH_10_DEFAULT 0x00000000 18196 #define cfgBIOS_SCRATCH_11_DEFAULT 0x00000000 18197 #define cfgBIOS_SCRATCH_12_DEFAULT 0x00000000 18198 #define cfgBIOS_SCRATCH_13_DEFAULT 0x00000000 18199 #define cfgBIOS_SCRATCH_14_DEFAULT 0x00000000 18200 #define cfgBIOS_SCRATCH_15_DEFAULT 0x00000000 18201 #define cfgBIF_RLC_INTR_CNTL_DEFAULT 0x00000000 18202 #define cfgBIF_VCE_INTR_CNTL_DEFAULT 0x00000000 18203 #define cfgBIF_UVD_INTR_CNTL_DEFAULT 0x00000000 18204 #define cfgGFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000 18205 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000 18206 #define cfgGFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000 18207 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000 18208 #define cfgGFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000 18209 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000 18210 #define cfgGFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000 18211 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000 18212 #define cfgGFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000 18213 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000 18214 #define cfgGFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000 18215 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000 18216 #define cfgGFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000 18217 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000 18218 #define cfgGFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000 18219 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000 18220 #define cfgGFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000 18221 #define cfgGFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000 18222 #define cfgGFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000 18223 #define cfgGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000 18224 18225 18226 // addressBlock: nbio_nbif0_syshub_mmreg_syshubdec 18227 #define cfgSYSHUB_INDEX_DEFAULT 0x00000000 18228 #define cfgSYSHUB_DATA_DEFAULT 0x00000000 18229 18230 18231 // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 18232 #define cfgRCC_BIF_STRAP0_DEFAULT 0x00040a00 18233 #define cfgRCC_BIF_STRAP1_DEFAULT 0x00400108 18234 #define cfgRCC_BIF_STRAP2_DEFAULT 0x000a0079 18235 #define cfgRCC_BIF_STRAP3_DEFAULT 0x00000000 18236 #define cfgRCC_BIF_STRAP4_DEFAULT 0x00100010 18237 #define cfgRCC_BIF_STRAP5_DEFAULT 0x31130010 18238 #define cfgRCC_BIF_STRAP6_DEFAULT 0x00000000 18239 #define cfgRCC_DEV0_PORT_STRAP0_DEFAULT 0x54228f20 18240 #define cfgRCC_DEV0_PORT_STRAP1_DEFAULT 0x10221479 18241 #define cfgRCC_DEV0_PORT_STRAP2_DEFAULT 0x1c6fe009 18242 #define cfgRCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849 18243 #define cfgRCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000 18244 #define cfgRCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000 18245 #define cfgRCC_DEV0_PORT_STRAP6_DEFAULT 0x0000ff02 18246 #define cfgRCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000 18247 #define cfgRCC_DEV0_PORT_STRAP8_DEFAULT 0x00000000 18248 #define cfgRCC_DEV0_PORT_STRAP9_DEFAULT 0x00000000 18249 #define cfgRCC_DEV0_EPF0_STRAP0_DEFAULT 0x30007310 18250 #define cfgRCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000 18251 #define cfgRCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000 18252 #define cfgRCC_DEV0_EPF0_STRAP2_DEFAULT 0x02002000 18253 #define cfgRCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b5cc41 18254 #define cfgRCC_DEV0_EPF0_STRAP4_DEFAULT 0x1f000000 18255 #define cfgRCC_DEV0_EPF0_STRAP5_DEFAULT 0x00001002 18256 #define cfgRCC_DEV0_EPF0_STRAP8_DEFAULT 0xcb026001 18257 #define cfgRCC_DEV0_EPF0_STRAP9_DEFAULT 0x00000100 18258 #define cfgRCC_DEV0_EPF1_STRAP0_DEFAULT 0x3000ab38 18259 #define cfgRCC_DEV0_EPF1_STRAP10_DEFAULT 0x00000000 18260 #define cfgRCC_DEV0_EPF1_STRAP11_DEFAULT 0x00000000 18261 #define cfgRCC_DEV0_EPF1_STRAP12_DEFAULT 0x00000000 18262 #define cfgRCC_DEV0_EPF1_STRAP13_DEFAULT 0x00000000 18263 #define cfgRCC_DEV0_EPF1_STRAP2_DEFAULT 0x00002000 18264 #define cfgRCC_DEV0_EPF1_STRAP3_DEFAULT 0x0806ace1 18265 #define cfgRCC_DEV0_EPF1_STRAP4_DEFAULT 0x2f000000 18266 #define cfgRCC_DEV0_EPF1_STRAP5_DEFAULT 0x00001002 18267 #define cfgRCC_DEV0_EPF1_STRAP6_DEFAULT 0x00000000 18268 #define cfgRCC_DEV0_EPF1_STRAP7_DEFAULT 0x00000000 18269 18270 18271 // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 18272 #define cfgEP_PCIE_SCRATCH_DEFAULT 0x00000000 18273 #define cfgEP_PCIE_CNTL_DEFAULT 0x00000000 18274 #define cfgEP_PCIE_INT_CNTL_DEFAULT 0x00000000 18275 #define cfgEP_PCIE_INT_STATUS_DEFAULT 0x00000000 18276 #define cfgEP_PCIE_RX_CNTL2_DEFAULT 0x00000000 18277 #define cfgEP_PCIE_BUS_CNTL_DEFAULT 0x00000080 18278 #define cfgEP_PCIE_CFG_CNTL_DEFAULT 0x00000000 18279 #define cfgEP_PCIE_TX_LTR_CNTL_DEFAULT 0x00007468 18280 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa 18281 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 18282 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 18283 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 18284 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b 18285 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 18286 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 18287 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a 18288 #define cfgEP_PCIE_STRAP_MISC_DEFAULT 0x00000000 18289 #define cfgEP_PCIE_STRAP_MISC2_DEFAULT 0x00000000 18290 #define cfgEP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000 18291 #define cfgEP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0 18292 #define cfgEP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100 18293 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa 18294 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 18295 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 18296 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 18297 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b 18298 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 18299 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 18300 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a 18301 #define cfgEP_PCIE_PME_CONTROL_DEFAULT 0x00000000 18302 #define cfgEP_PCIEP_RESERVED_DEFAULT 0x00000000 18303 #define cfgEP_PCIE_TX_CNTL_DEFAULT 0x00000000 18304 #define cfgEP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 18305 #define cfgEP_PCIE_ERR_CNTL_DEFAULT 0x00000500 18306 #define cfgEP_PCIE_RX_CNTL_DEFAULT 0x01000000 18307 #define cfgEP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 18308 18309 18310 // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 18311 #define cfgDN_PCIE_RESERVED_DEFAULT 0x00000000 18312 #define cfgDN_PCIE_SCRATCH_DEFAULT 0x00000000 18313 #define cfgDN_PCIE_CNTL_DEFAULT 0x00000000 18314 #define cfgDN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000 18315 #define cfgDN_PCIE_RX_CNTL2_DEFAULT 0x00000000 18316 #define cfgDN_PCIE_BUS_CNTL_DEFAULT 0x00000080 18317 #define cfgDN_PCIE_CFG_CNTL_DEFAULT 0x00000000 18318 #define cfgDN_PCIE_STRAP_F0_DEFAULT 0x00000001 18319 #define cfgDN_PCIE_STRAP_MISC_DEFAULT 0x00000000 18320 #define cfgDN_PCIE_STRAP_MISC2_DEFAULT 0x00000000 18321 18322 18323 // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 18324 #define cfgPCIE_ERR_CNTL_DEFAULT 0x00000500 18325 #define cfgPCIE_RX_CNTL_DEFAULT 0x00000000 18326 #define cfgPCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 18327 #define cfgPCIE_LC_CNTL2_DEFAULT 0x00000000 18328 #define cfgPCIEP_STRAP_MISC_DEFAULT 0x00000000 18329 #define cfgLTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000 18330 18331 18332 // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975] 18333 #define cfgRCC_DEV0_EPF0_RCC_ERR_LOG_DEFAULT 0x00000000 18334 #define cfgRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000 18335 #define cfgRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 18336 #define cfgRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_DEFAULT 0x00000000 18337 #define cfgRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 18338 18339 18340 // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 18341 #define cfgRCC_ERR_INT_CNTL_DEFAULT 0x00000000 18342 #define cfgRCC_BACO_CNTL_MISC_DEFAULT 0x00000000 18343 #define cfgRCC_RESET_EN_DEFAULT 0x00008000 18344 #define cfgRCC_VDM_SUPPORT_DEFAULT 0x00000000 18345 #define cfgRCC_MARGIN_PARAM_CNTL0_DEFAULT 0x0a80a0df 18346 #define cfgRCC_MARGIN_PARAM_CNTL1_DEFAULT 0x0000f000 18347 #define cfgRCC_GPUIOV_REGION_DEFAULT 0x00000000 18348 #define cfgRCC_PEER_REG_RANGE0_DEFAULT 0xffff0000 18349 #define cfgRCC_PEER_REG_RANGE1_DEFAULT 0xffff0000 18350 #define cfgRCC_BUS_CNTL_DEFAULT 0x00000000 18351 #define cfgRCC_CONFIG_CNTL_DEFAULT 0x00000000 18352 #define cfgRCC_CONFIG_F0_BASE_DEFAULT 0x00000000 18353 #define cfgRCC_CONFIG_APER_SIZE_DEFAULT 0x00000000 18354 #define cfgRCC_CONFIG_REG_APER_SIZE_DEFAULT 0x00000000 18355 #define cfgRCC_XDMA_LO_DEFAULT 0x00000000 18356 #define cfgRCC_XDMA_HI_DEFAULT 0x00000000 18357 #define cfgRCC_FEATURES_CONTROL_MISC_DEFAULT 0x00000000 18358 #define cfgRCC_BUSNUM_CNTL1_DEFAULT 0x00000000 18359 #define cfgRCC_BUSNUM_LIST0_DEFAULT 0x00000000 18360 #define cfgRCC_BUSNUM_LIST1_DEFAULT 0x00000000 18361 #define cfgRCC_BUSNUM_CNTL2_DEFAULT 0x00000000 18362 #define cfgRCC_CAPTURE_HOST_BUSNUM_DEFAULT 0x00000000 18363 #define cfgRCC_HOST_BUSNUM_DEFAULT 0x00000000 18364 #define cfgRCC_PEER0_FB_OFFSET_HI_DEFAULT 0x00000000 18365 #define cfgRCC_PEER0_FB_OFFSET_LO_DEFAULT 0x00000000 18366 #define cfgRCC_PEER1_FB_OFFSET_HI_DEFAULT 0x00000000 18367 #define cfgRCC_PEER1_FB_OFFSET_LO_DEFAULT 0x00000000 18368 #define cfgRCC_PEER2_FB_OFFSET_HI_DEFAULT 0x00000000 18369 #define cfgRCC_PEER2_FB_OFFSET_LO_DEFAULT 0x00000000 18370 #define cfgRCC_PEER3_FB_OFFSET_HI_DEFAULT 0x00000000 18371 #define cfgRCC_PEER3_FB_OFFSET_LO_DEFAULT 0x00000000 18372 #define cfgRCC_DEVFUNCNUM_LIST0_DEFAULT 0x00000000 18373 #define cfgRCC_DEVFUNCNUM_LIST1_DEFAULT 0x00000000 18374 #define cfgRCC_DEV0_LINK_CNTL_DEFAULT 0x00000000 18375 #define cfgRCC_CMN_LINK_CNTL_DEFAULT 0x00400000 18376 #define cfgRCC_EP_REQUESTERID_RESTORE_DEFAULT 0x00000000 18377 #define cfgRCC_LTR_LSWITCH_CNTL_DEFAULT 0x00000000 18378 #define cfgRCC_MH_ARB_CNTL_DEFAULT 0x00000000 18379 18380 18381 // addressBlock: nbio_nbif0_bif_bx_BIFDEC1 18382 #define cfgCC_BIF_BX_STRAP0_DEFAULT 0x00000000 18383 #define cfgCC_BIF_BX_PINSTRAP0_DEFAULT 0x00000000 18384 #define cfgBIF_MM_INDACCESS_CNTL_DEFAULT 0x00000000 18385 #define cfgBUS_CNTL_DEFAULT 0x00000000 18386 #define cfgBIF_SCRATCH0_DEFAULT 0x00000000 18387 #define cfgBIF_SCRATCH1_DEFAULT 0x00000000 18388 #define cfgBX_RESET_EN_DEFAULT 0x00010000 18389 #define cfgMM_CFGREGS_CNTL_DEFAULT 0x00000000 18390 #define cfgBX_RESET_CNTL_DEFAULT 0x00000000 18391 #define cfgINTERRUPT_CNTL_DEFAULT 0x00000000 18392 #define cfgINTERRUPT_CNTL2_DEFAULT 0x00000000 18393 #define cfgCLKREQB_PAD_CNTL_DEFAULT 0x000008e0 18394 #define cfgBIF_FEATURES_CONTROL_MISC_DEFAULT 0x00800000 18395 #define cfgBIF_DOORBELL_CNTL_DEFAULT 0x00000000 18396 #define cfgBIF_DOORBELL_INT_CNTL_DEFAULT 0x00000000 18397 #define cfgBIF_FB_EN_DEFAULT 0x00000000 18398 #define cfgBIF_INTR_CNTL_DEFAULT 0x00000000 18399 #define cfgBIF_MST_TRANS_PENDING_VF_DEFAULT 0x00000000 18400 #define cfgBIF_SLV_TRANS_PENDING_VF_DEFAULT 0x00000000 18401 #define cfgBACO_CNTL_DEFAULT 0x00000000 18402 #define cfgBIF_BACO_EXIT_TIME0_DEFAULT 0x00000100 18403 #define cfgBIF_BACO_EXIT_TIMER1_DEFAULT 0x1c000200 18404 #define cfgBIF_BACO_EXIT_TIMER2_DEFAULT 0x00000300 18405 #define cfgBIF_BACO_EXIT_TIMER3_DEFAULT 0x00000500 18406 #define cfgBIF_BACO_EXIT_TIMER4_DEFAULT 0x00000400 18407 #define cfgMEM_TYPE_CNTL_DEFAULT 0x00000000 18408 #define cfgNBIF_GFX_ADDR_LUT_CNTL_DEFAULT 0x00000000 18409 #define cfgNBIF_GFX_ADDR_LUT_0_DEFAULT 0x00000000 18410 #define cfgNBIF_GFX_ADDR_LUT_1_DEFAULT 0x00000001 18411 #define cfgNBIF_GFX_ADDR_LUT_2_DEFAULT 0x00000002 18412 #define cfgNBIF_GFX_ADDR_LUT_3_DEFAULT 0x00000003 18413 #define cfgNBIF_GFX_ADDR_LUT_4_DEFAULT 0x00000004 18414 #define cfgNBIF_GFX_ADDR_LUT_5_DEFAULT 0x00000005 18415 #define cfgNBIF_GFX_ADDR_LUT_6_DEFAULT 0x00000006 18416 #define cfgNBIF_GFX_ADDR_LUT_7_DEFAULT 0x00000007 18417 #define cfgNBIF_GFX_ADDR_LUT_8_DEFAULT 0x00000008 18418 #define cfgNBIF_GFX_ADDR_LUT_9_DEFAULT 0x00000009 18419 #define cfgNBIF_GFX_ADDR_LUT_10_DEFAULT 0x0000000a 18420 #define cfgNBIF_GFX_ADDR_LUT_11_DEFAULT 0x0000000b 18421 #define cfgNBIF_GFX_ADDR_LUT_12_DEFAULT 0x0000000c 18422 #define cfgNBIF_GFX_ADDR_LUT_13_DEFAULT 0x0000000d 18423 #define cfgNBIF_GFX_ADDR_LUT_14_DEFAULT 0x0000000e 18424 #define cfgNBIF_GFX_ADDR_LUT_15_DEFAULT 0x0000000f 18425 #define cfgREMAP_HDP_MEM_FLUSH_CNTL_DEFAULT 0x0000385c 18426 #define cfgREMAP_HDP_REG_FLUSH_CNTL_DEFAULT 0x00003858 18427 #define cfgBIF_RB_CNTL_DEFAULT 0x00000000 18428 #define cfgBIF_RB_BASE_DEFAULT 0x00000000 18429 #define cfgBIF_RB_RPTR_DEFAULT 0x00000000 18430 #define cfgBIF_RB_WPTR_DEFAULT 0x00000000 18431 #define cfgBIF_RB_WPTR_ADDR_HI_DEFAULT 0x00000000 18432 #define cfgBIF_RB_WPTR_ADDR_LO_DEFAULT 0x00000000 18433 #define cfgMAILBOX_INDEX_DEFAULT 0x00000000 18434 #define cfgBIF_MP1_INTR_CTRL_DEFAULT 0x00000000 18435 #define cfgBIF_UVD_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 18436 #define cfgBIF_VCE_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 18437 #define cfgBIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 18438 #define cfgBIF_PERSTB_PAD_CNTL_DEFAULT 0x000000c0 18439 #define cfgBIF_PX_EN_PAD_CNTL_DEFAULT 0x00000031 18440 #define cfgBIF_REFPADKIN_PAD_CNTL_DEFAULT 0x00000007 18441 #define cfgBIF_CLKREQB_PAD_CNTL_DEFAULT 0x00600100 18442 #define cfgBIF_PWRBRK_PAD_CNTL_DEFAULT 0x00000071 18443 #define cfgBIF_WAKEB_PAD_CNTL_DEFAULT 0x00000031 18444 #define cfgBIF_VAUX_PRESENT_PAD_CNTL_DEFAULT 0x0000000d 18445 18446 18447 // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 18448 #define cfgBIF_BX_PF_BIF_BME_STATUS_DEFAULT 0x00000000 18449 #define cfgBIF_BX_PF_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 18450 #define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 18451 #define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 18452 #define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 18453 #define cfgBIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 18454 #define cfgBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 18455 #define cfgBIF_BX_PF_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 18456 #define cfgBIF_BX_PF_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 18457 #define cfgBIF_BX_PF_BIF_TRANS_PENDING_DEFAULT 0x00000000 18458 #define cfgBIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS_DEFAULT 0x00000000 18459 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 18460 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 18461 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 18462 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 18463 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 18464 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 18465 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 18466 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 18467 #define cfgBIF_BX_PF_MAILBOX_CONTROL_DEFAULT 0x00000000 18468 #define cfgBIF_BX_PF_MAILBOX_INT_CNTL_DEFAULT 0x00000000 18469 #define cfgBIF_BX_PF_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 18470 18471 18472 // addressBlock: nbio_nbif0_gdc_GDCDEC 18473 #define cfgA2S_CNTL_CL0_DEFAULT 0x02a80540 18474 #define cfgA2S_CNTL_CL1_DEFAULT 0x02a825a0 18475 #define cfgA2S_CNTL3_CL0_DEFAULT 0x00000000 18476 #define cfgA2S_CNTL3_CL1_DEFAULT 0x00000008 18477 #define cfgA2S_CNTL_SW0_DEFAULT 0x04040000 18478 #define cfgA2S_CNTL_SW1_DEFAULT 0x04040200 18479 #define cfgA2S_CNTL_SW2_DEFAULT 0x04040200 18480 #define cfgA2S_CPLBUF_ALLOC_CNTL_DEFAULT 0x11100001 18481 #define cfgA2S_TAG_ALLOC_0_DEFAULT 0x00000000 18482 #define cfgA2S_TAG_ALLOC_1_DEFAULT 0x00000000 18483 #define cfgA2S_MISC_CNTL_DEFAULT 0x0005000b 18484 #define cfgNGDC_SDP_PORT_CTRL_DEFAULT 0x0000003f 18485 #define cfgSHUB_REGS_IF_CTL_DEFAULT 0x00000000 18486 #define cfgNGDC_MGCG_CTRL_DEFAULT 0x00000100 18487 #define cfgNGDC_RESERVED_0_DEFAULT 0x00000000 18488 #define cfgNGDC_RESERVED_1_DEFAULT 0x00000000 18489 #define cfgNGDC_SDP_PORT_CTRL_SOCCLK_DEFAULT 0x0000003f 18490 #define cfgBIF_SDMA0_DOORBELL_RANGE_DEFAULT 0x00000000 18491 #define cfgBIF_SDMA1_DOORBELL_RANGE_DEFAULT 0x00000000 18492 #define cfgBIF_IH_DOORBELL_RANGE_DEFAULT 0x00000000 18493 #define cfgBIF_MMSCH0_DOORBELL_RANGE_DEFAULT 0x00000000 18494 #define cfgBIF_ACV_DOORBELL_RANGE_DEFAULT 0x00000000 18495 #define cfgBIF_DOORBELL_FENCE_CNTL_DEFAULT 0x00000000 18496 #define cfgS2A_MISC_CNTL_DEFAULT 0x00000000 18497 #define cfgNGDC_PG_MISC_CTRL_DEFAULT 0x14006000 18498 #define cfgNGDC_PGMST_CTRL_DEFAULT 0x00000000 18499 #define cfgNGDC_PGSLV_CTRL_DEFAULT 0x00001084 18500 18501 18502 // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2 18503 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 18504 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 18505 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 18506 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 18507 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 18508 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 18509 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 18510 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 18511 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 18512 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 18513 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 18514 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 18515 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 18516 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 18517 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 18518 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_DEFAULT 0x00000001 18519 #define cfgRCC_DEV0_EPF0_GFXMSIX_PBA_DEFAULT 0x00000000 18520 18521 #endif 18522