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Searched refs:smc911x_reg_read (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/board/micronas/vct/
H A Dsmc_eeprom.c76 if (!(smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)) in mac_busy()
89 if (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) { in get_mac_reg()
102 reg_val = smc911x_reg_read(MAC_CSR_DATA); in get_mac_reg()
112 gpio = smc911x_reg_read(GPIO_CFG); in eeprom_enable_access()
130 ret = smc911x_reg_read(MAC_CSR_CMD) & E2P_CMD_MAC_ADDR_LOADED_; in eeprom_is_mac_address_loaded()
141 if ((temp = smc911x_reg_read(E2P_CMD)) & E2P_CMD_EPC_BUSY_) { in eeprom_read_location()
150 while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) { in eeprom_read_location()
159 (*data) = (unchar) (smc911x_reg_read(E2P_DATA)); in eeprom_read_location()
169 if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) { in eeprom_enable_erase_and_write()
175 while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) { in eeprom_enable_erase_and_write()
[all …]
H A Dvct.h72 u32 smc911x_reg_read(u32 addr);
H A Debi_smc911x.c35 u32 smc911x_reg_read(struct eth_device *dev, u32 addr) in smc911x_reg_read() function
/openbmc/u-boot/examples/standalone/
H A Dsmc911x_eeprom.c62 smc911x_reg_read(dev, i), in dump_regs()
71 if (smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY) { in do_eeprom_cmd()
73 smc911x_reg_read(dev, E2P_CMD)); in do_eeprom_cmd()
79 while (smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY) in do_eeprom_cmd()
82 smc911x_reg_read(dev, E2P_CMD)); in do_eeprom_cmd()
95 return (ret ? : smc911x_reg_read(dev, E2P_DATA)); in read_eeprom_reg()
251 if (smc911x_reg_read(dev, GPIO_CFG) & GPIO_CFG_EEPR_EN) { in smc911x_init()
252 while (smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY) in smc911x_init()
255 smc911x_reg_read(dev, E2P_CMD)); in smc911x_init()
259 smc911x_reg_read(dev, GPIO_CFG) & ~GPIO_CFG_EEPR_EN); in smc911x_init()
/openbmc/u-boot/drivers/net/
H A Dsmc911x.h26 u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
37 static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset) in smc911x_reg_read() function
406 while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) in smc911x_get_mac_csr()
410 while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) in smc911x_get_mac_csr()
413 return smc911x_reg_read(dev, MAC_CSR_DATA); in smc911x_get_mac_csr()
418 while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) in smc911x_set_mac_csr()
422 while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) in smc911x_set_mac_csr()
430 val = smc911x_reg_read(dev, BYTE_TEST); in smc911x_detect_chip()
439 val = smc911x_reg_read(dev, ID_REV) >> 16; in smc911x_detect_chip()
461 if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0) { in smc911x_reset()
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H A Dsmc911x.c70 reg = smc911x_reg_read(dev, PMT_CTRL); in smc911x_phy_reset()
163 while (!((smc911x_reg_read(dev, TX_FIFO_INF) & in smc911x_send()
169 status = smc911x_reg_read(dev, TX_STATUS_FIFO) & in smc911x_send()
198 if ((smc911x_reg_read(dev, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16) { in smc911x_rx()
199 status = smc911x_reg_read(dev, RX_STATUS_FIFO); in smc911x_rx()