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Searched refs:sll (Results 1 – 25 of 25) sorted by relevance

/openbmc/openbmc/meta-openembedded/meta-oe/recipes-connectivity/libwebsockets/libwebsockets/
H A D0001-sll_protocol-may-be-be16.patch9 497 | sll.sll_protocol = (uint32_t)(htons((uint16_t)0x800));
23 memset(&sll, 0, sizeof(sll));
24 sll.sll_family = AF_PACKET;
25 - sll.sll_protocol = (uint32_t)(htons((uint16_t)0x800));
26 + sll.sll_protocol = (uint16_t)(htons((uint16_t)0x800));
27 sll.sll_halen = 6;
28 sll.sll_ifindex = (int)if_nametoindex(iface);
29 memset(sll.sll_addr, 0xff, 6);
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/rarpd/rarpd/
H A D0003-rarpd.c-bug-fix.patch206 n = recvfrom(fd, buf, sizeof(buf), MSG_DONTWAIT, (struct sockaddr*)&sll, &sll_len);
216 - for (i=0; i<sll.sll_halen; i++) {
218 - sprintf(ptr, ":%02x", sll.sll_addr[i]);
221 - sprintf(ptr, "%02x", sll.sll_addr[i]);
224 - syslog(LOG_INFO, "RARP request from %s on if%d", tmpbuf, sll.sll_ifindex);
226 + snprintf(tmpbuf, 2, "%02x", sll.sll_addr[0]);
227 + for (ptr=tmpbuf+2, i=1; i<sll.sll_halen; i++) {
228 + snprintf(ptr, 3, ":%02x", sll.sll_addr[i]);
233 + if (ifl->index == sll.sll_ifindex)
239 + sprintf(tmpname, "if%d", sll.sll_ifindex);
/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_shift.S91 sll \dst, \src
98 sll \dst, \src
109 test sll
110 tests_shift sll, 0xa3c51249
/openbmc/u-boot/arch/mips/include/asm/
H A Dasm.h275 #define INT_SLL sll
313 #define LONG_SLL sll
363 #define PTR_SLL sll
414 #define SSNOP sll zero, zero, 1
/openbmc/u-boot/arch/nds32/cpu/n1213/
H A Dstart.S333 sll $t5, $t4, $t1 ! get $t5 cache line size
340 sll $p1, $p1, $t3 ! GET the total cache size
368 sll $t5, $t4, $t1 ! get $t5 cache line size
375 sll $p1, $p1, $t3 ! GET the total cache size
/openbmc/qemu/tests/tcg/mips/include/
H A Dwrappers_msa.h706 DO_MSA__WD__WS_WT(SLL_B, sll.b)
707 DO_MSA__WD__WS_WT(SLL_H, sll.h)
708 DO_MSA__WD__WS_WT(SLL_W, sll.w)
709 DO_MSA__WD__WS_WT(SLL_D, sll.d)
/openbmc/qemu/tests/tcg/s390x/
H A Dshift.c56 DEFINE_SHIFT_SINGLE_2(sll, 0xd04);
/openbmc/u-boot/arch/mips/lib/
H A Dgenex.S200 sll k1, k1, 30
/openbmc/qemu/tests/tcg/alpha/system/
H A Dboot.S21 sll \reg, 24, \reg
/openbmc/u-boot/arch/xtensa/cpu/
H A Dstart.S305 sll a0, a0
/openbmc/qemu/target/openrisc/
H A Ddisas.c66 INSN(sll, "r%d, r%d, r%d", a->d, a->a, a->b)
/openbmc/qemu/target/s390x/tcg/
H A Dinsn-data.h.inc820 C(0x8900, SLL, RS_a, Z, r1_o, sh, new, r1_32, sll, 0)
821 C(0xebdf, SLLK, RSY_a, DO, r3_o, sh, new, r1_32, sll, 0)
822 C(0xeb0d, SLLG, RSY_a, Z, r3_o, sh, r1, 0, sll, 0)
834 C(0x8d00, SLDL, RS_a, Z, r1_D32, sh, new, r1_D32, sll, 0)
/openbmc/qemu/target/riscv/
H A Dinsn32.decode161 sll 0000000 ..... ..... 001 ..... 0110011 @r
/openbmc/qemu/target/xtensa/core-fsf/
H A Dxtensa-modules.c.inc8028 { "sll", 66 /* xt_iclass_shifts */,
8919 return 105; /* sll */
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-insn-defs.c.inc1493 /* Emits the `sll.w d, j, k` instruction. */
1514 /* Emits the `sll.d d, j, k` instruction. */
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dxtensa-modules.c.inc11074 { "sll", 68 /* xt_iclass_shifts */,
12460 return 107; /* sll */
/openbmc/qemu/target/xtensa/core-lx106/
H A Dxtensa-modules.c.inc6067 { "sll", ICLASS_xt_iclass_shifts,
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dxtensa-modules.c.inc8931 { "sll", ICLASS_xt_iclass_shifts,
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dxtensa-modules.c.inc11717 { "sll", ICLASS_xt_iclass_shifts,
/openbmc/qemu/target/xtensa/core-de212/
H A Dxtensa-modules.c.inc11077 { "sll", ICLASS_xt_iclass_shifts,
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dxtensa-modules.c.inc16339 { "sll", ICLASS_xt_iclass_shifts,
/openbmc/qemu/target/mips/tcg/
H A Dmsa_helper.c5470 MSA_BINOP_IMMU_DF(slli, sll) in MSA_BINOP_IMMU_DF() argument
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dxtensa-modules.c.inc27089 { "sll", ICLASS_xt_iclass_shifts,
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dxtensa-modules.c.inc33218 { "sll", ICLASS_xt_iclass_shifts,
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dxtensa-modules.c.inc75632 { "sll", ICLASS_xt_iclass_shifts,