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Searched refs:slcr (Results 1 – 21 of 21) sorted by relevance

/openbmc/linux/drivers/reset/
H A Dreset-zynq.c21 struct regmap *slcr; member
40 return regmap_update_bits(priv->slcr, in zynq_reset_assert()
57 return regmap_update_bits(priv->slcr, in zynq_reset_deassert()
76 ret = regmap_read(priv->slcr, priv->offset + (bank * 4), &reg); in zynq_reset_status()
98 priv->slcr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in zynq_reset_probe()
100 if (IS_ERR(priv->slcr)) { in zynq_reset_probe()
102 return PTR_ERR(priv->slcr); in zynq_reset_probe()
/openbmc/linux/drivers/fpga/
H A Dzynq-fpga.c127 struct regmap *slcr; member
286 regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, in zynq_fpga_ops_write_init()
290 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_init()
293 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_init()
513 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_complete()
517 regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, in zynq_fpga_ops_write_complete()
569 priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node, in zynq_fpga_probe()
571 if (IS_ERR(priv->slcr)) { in zynq_fpga_probe()
573 return PTR_ERR(priv->slcr); in zynq_fpga_probe()
/openbmc/qemu/hw/arm/
H A Dxilinx_zynq.c208 DeviceState *dev, *slcr; in zynq_init() local
258 slcr = qdev_new("xilinx-zynq_slcr"); in zynq_init()
259 qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk); in zynq_init()
260 qdev_prop_set_uint8(slcr, "boot-mode", zynq_machine->boot_mode); in zynq_init()
261 sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal); in zynq_init()
262 sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000); in zynq_init()
295 qdev_get_clock_out(slcr, "uart0_ref_clk")); in zynq_init()
303 qdev_get_clock_out(slcr, "uart1_ref_clk")); in zynq_init()
H A Dxlnx-versal.c497 object_initialize_child(OBJECT(s), "versal-pmc-iou-slcr", &s->pmc.iou.slcr, in versal_create_pmc_iou_slcr()
500 sbd = SYS_BUS_DEVICE(&s->pmc.iou.slcr); in versal_create_pmc_iou_slcr()
579 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "ospi-mux-sel", 0, in versal_create_ospi()
905 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "sd-emmc-sel", 0, in versal_unimp()
909 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "sd-emmc-sel", 1, in versal_unimp()
913 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), in versal_unimp()
918 qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), in versal_unimp()
/openbmc/u-boot/arch/arm/dts/
H A Dzynq-cse-nand.dts41 slcr: slcr@f8000000 { label
45 compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
H A Dzynq-cse-nor.dts50 slcr: slcr@f8000000 { label
53 compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
H A Dzynq-cse-qspi.dtsi93 slcr: slcr@f8000000 { label
97 compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
H A Dzynq-7000.dtsi258 slcr: slcr@f8000000 { label
262 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
288 syscon = <&slcr>;
294 syscon = <&slcr>;
323 syscon = <&slcr>;
/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Dzynq-reset.txt10 - syscon: <&slcr>
21 syscon = <&slcr>;
/openbmc/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi310 slcr: slcr@f8000000 { label
313 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
338 syscon = <&slcr>;
344 syscon = <&slcr>;
373 syscon = <&slcr>;
/openbmc/linux/drivers/clk/zynq/
H A Dclkc.c580 struct device_node *slcr; in zynq_clock_init() local
594 slcr = of_get_parent(np); in zynq_clock_init()
596 if (slcr->data) { in zynq_clock_init()
597 zynq_clkc_base = (__force void __iomem *)slcr->data + res.start; in zynq_clock_init()
600 of_node_put(slcr); in zynq_clock_init()
606 of_node_put(slcr); in zynq_clock_init()
/openbmc/linux/arch/arm/mach-zynq/
H A DMakefile7 obj-y := common.o slcr.o pm.o
/openbmc/u-boot/arch/arm/mach-zynq/
H A DMakefile12 obj-y += slcr.o
/openbmc/u-boot/doc/
H A DREADME.zynq36 Zynq has a facility to read the bootmode from the slcr bootmode register
42 board_late_init() will read the bootmode values using slcr bootmode register
/openbmc/qemu/include/hw/arm/
H A Dxlnx-versal.h109 XlnxVersalPmcIouSlcr slcr; member
/openbmc/qemu/hw/misc/
H A Dmeson.build95 'xlnx-versal-pmc-iou-slcr.c',
/openbmc/linux/drivers/net/ethernet/mellanox/mlxsw/
H A Dreg.h1299 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN);
1313 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1322 MLXSW_ITEM32_LP(reg, slcr, 0x00, 16, 0x00, 12);
1334 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1394 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1400 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);
1404 MLXSW_REG_ZERO(slcr, payload); in mlxsw_reg_slcr_pack()
12927 MLXSW_REG(slcr),
H A Dspectrum.c2715 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl); in mlxsw_sp_lag_init()
/openbmc/linux/Documentation/devicetree/bindings/fpga/
H A Dfpga-region.txt357 syscon = <&slcr>;
/openbmc/linux/
H A Dopengrok0.0.log[all...]
H A Dopengrok1.0.log[all...]