Searched refs:simm12 (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/arch/riscv/include/asm/ |
| H A D | insn-def.h | 29 .macro insn_i, opcode, func3, rd, rs1, simm12
30 .insn i \opcode, \func3, \rd, \rs1, \simm12
46 .macro insn_i, opcode, func3, rd, rs1, simm12
51 (\simm12 << INSN_I_SIMM12_SHIFT))
66 #define __INSN_I(opcode, func3, rd, rs1, simm12) \ argument
67 ".insn i " opcode ", " func3 ", " rd ", " rs1 ", " simm12 "\n"
106 #define __INSN_I(opcode, func3, rd, rs1, simm12) \ argument
108 "insn_i " opcode ", " func3 ", " rd ", " rs1 ", " simm12 "\n" \
119 #define INSN_I(opcode, func3, rd, rs1, simm12) \ argument
121 RV_##rs1, RV_##simm12)
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| /openbmc/qemu/tcg/loongarch64/ |
| H A D | tcg-target.c.inc | 350 /* val fits in simm12: addi.w rd, zero, val */
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