Searched refs:sil_port (Results 1 – 1 of 1) sorted by relevance
230 } sil_port[] = { variable542 writel(0, mmio_base + sil_port[ap->port_no].sien); in sil_freeze()665 mmio_base + sil_port[i].fifo_cfg); in sil_init_controller()675 tmp = readl(mmio_base + sil_port[i].sfis_cfg); in sil_init_controller()681 writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg); in sil_init_controller()688 tmp = readl(mmio_base + sil_port[2].bmdma); in sil_init_controller()691 mmio_base + sil_port[2].bmdma); in sil_init_controller()771 ioaddr->cmd_addr = mmio_base + sil_port[i].tf; in sil_init_one()773 ioaddr->ctl_addr = mmio_base + sil_port[i].ctl; in sil_init_one()774 ioaddr->bmdma_addr = mmio_base + sil_port[i].bmdma; in sil_init_one()[all …]