xref: /openbmc/u-boot/arch/arm/include/asm/armv7m.h (revision d1e15041)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2010,2011
4  * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
5  *
6  * (C) Copyright 2015
7  * Kamil Lulko, <kamil.lulko@gmail.com>
8  */
9 
10 #ifndef ARMV7M_H
11 #define ARMV7M_H
12 
13 /* armv7m fixed base addresses */
14 #define V7M_SCS_BASE		0xE000E000
15 #define V7M_NVIC_BASE		(V7M_SCS_BASE + 0x0100)
16 #define V7M_SCB_BASE		(V7M_SCS_BASE + 0x0D00)
17 #define V7M_PROC_FTR_BASE	(V7M_SCS_BASE + 0x0D78)
18 #define V7M_MPU_BASE		(V7M_SCS_BASE + 0x0D90)
19 #define V7M_FPU_BASE		(V7M_SCS_BASE + 0x0F30)
20 #define V7M_CACHE_MAINT_BASE	(V7M_SCS_BASE + 0x0F50)
21 #define V7M_ACCESS_CNTL_BASE	(V7M_SCS_BASE + 0x0F90)
22 
23 #define V7M_SCB_VTOR		0x08
24 
25 #if !defined(__ASSEMBLY__)
26 struct v7m_scb {
27 	uint32_t cpuid;		/* CPUID Base Register */
28 	uint32_t icsr;		/* Interrupt Control and State Register */
29 	uint32_t vtor;		/* Vector Table Offset Register */
30 	uint32_t aircr;		/* App Interrupt and Reset Control Register */
31 	uint32_t scr;		/* offset 0x10: System Control Register */
32 	uint32_t ccr;		/* offset 0x14: Config and Control Register */
33 	uint32_t shpr1;		/* offset 0x18: System Handler Priority Reg 1 */
34 	uint32_t shpr2;		/* offset 0x1c: System Handler Priority Reg 2 */
35 	uint32_t shpr3;		/* offset 0x20: System Handler Priority Reg 3 */
36 	uint32_t shcrs;		/* offset 0x24: System Handler Control State */
37 	uint32_t cfsr;		/* offset 0x28: Configurable Fault Status Reg */
38 	uint32_t hfsr;		/* offset 0x2C: HardFault Status Register */
39 	uint32_t res;		/* offset 0x30: reserved */
40 	uint32_t mmar;		/* offset 0x34: MemManage Fault Address Reg */
41 	uint32_t bfar;		/* offset 0x38: BusFault Address Reg */
42 	uint32_t afsr;		/* offset 0x3C: Auxiliary Fault Status Reg */
43 };
44 #define V7M_SCB				((struct v7m_scb *)V7M_SCB_BASE)
45 
46 #define V7M_AIRCR_VECTKEY		0x5fa
47 #define V7M_AIRCR_VECTKEY_SHIFT		16
48 #define V7M_AIRCR_ENDIAN		(1 << 15)
49 #define V7M_AIRCR_PRIGROUP_SHIFT	8
50 #define V7M_AIRCR_PRIGROUP_MSK		(0x7 << V7M_AIRCR_PRIGROUP_SHIFT)
51 #define V7M_AIRCR_SYSRESET		(1 << 2)
52 
53 #define V7M_ICSR_VECTACT_MSK		0xFF
54 
55 #define V7M_CCR_DCACHE			16
56 #define V7M_CCR_ICACHE			17
57 
58 struct v7m_mpu {
59 	uint32_t type;		/* Type Register */
60 	uint32_t ctrl;		/* Control Register */
61 	uint32_t rnr;		/* Region Number Register */
62 	uint32_t rbar;		/* Region Base Address Register */
63 	uint32_t rasr;		/* Region Attribute and Size Register */
64 };
65 #define V7M_MPU				((struct v7m_mpu *)V7M_MPU_BASE)
66 
67 #endif /* !defined(__ASSEMBLY__) */
68 #endif /* ARMV7M_H */
69