| /openbmc/u-boot/drivers/video/ |
| H A D | logicore_dp_tx.c | 240 static void set_reg(struct udevice *dev, u32 reg, u32 value) in set_reg() function
393 set_reg(dev, REG_AUX_ADDRESS, request->address); in aux_request_send()
400 set_reg(dev, in aux_request_send()
406 set_reg(dev, REG_AUX_CMD, in aux_request_send()
644 set_reg(dev, REG_PHY_CONFIG, phy_config | PHY_CONFIG_GT_ALL_RESET_MASK); in initialize()
647 set_reg(dev, REG_SOFT_RESET, in initialize()
652 set_reg(dev, REG_ENABLE, 0); in initialize()
658 set_reg(dev, REG_AUX_CLK_DIVIDER, val); in initialize()
661 set_reg(dev, REG_PHY_CLOCK_SELECT, PHY_CLOCK_SELECT_DEFAULT); in initialize()
664 set_reg(dev, REG_PHY_CONFIG, in initialize()
[all …]
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| /openbmc/qemu/hw/intc/ |
| H A D | sh_intc.c | 111 static SHIntCMode sh_intc_mode(unsigned long address, unsigned long set_reg, in sh_intc_mode() argument
114 if (address != A7ADDR(set_reg) && address != A7ADDR(clr_reg)) { in sh_intc_mode()
117 if (set_reg && clr_reg) { in sh_intc_mode()
118 return address == A7ADDR(set_reg) ? in sh_intc_mode()
121 return set_reg ? INTC_MODE_ENABLE_REG : INTC_MODE_MASK_REG; in sh_intc_mode()
141 mode = sh_intc_mode(address, mr->set_reg, mr->clr_reg); in sh_intc_locate()
157 mode = sh_intc_mode(address, pr->set_reg, pr->clr_reg); in sh_intc_locate()
413 j += sh_intc_register(sysmem, desc, mr->set_reg, "mask", "set", j); in sh_intc_init()
422 j += sh_intc_register(sysmem, desc, pr->set_reg, "prio", "set", j); in sh_intc_init()
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| /openbmc/u-boot/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.c | 224 static void set_reg(const struct ddr_info *priv, in set_reg() function
416 set_reg(priv, REG_REG, &config->c_reg); in stm32mp1_ddr_init()
417 set_reg(priv, REG_TIMING, &config->c_timing); in stm32mp1_ddr_init()
418 set_reg(priv, REG_MAP, &config->c_map); in stm32mp1_ddr_init()
425 set_reg(priv, REG_PERF, &config->c_perf); in stm32mp1_ddr_init()
435 set_reg(priv, REGPHY_REG, &config->p_reg); in stm32mp1_ddr_init()
436 set_reg(priv, REGPHY_TIMING, &config->p_timing); in stm32mp1_ddr_init()
437 set_reg(priv, REGPHY_CAL, &config->p_cal); in stm32mp1_ddr_init()
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| /openbmc/qemu/include/hw/sh4/ |
| H A D | sh_intc.h | 23 unsigned long set_reg, clr_reg, reg_width; member
29 unsigned long set_reg, clr_reg, reg_width, field_width; member
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| /openbmc/qemu/include/exec/ |
| H A D | gdbstub.h | 40 gdb_get_reg_cb get_reg, gdb_set_reg_cb set_reg,
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| /openbmc/qemu/gdbstub/ |
| H A D | gdbstub.c | 55 gdb_set_reg_cb set_reg; member
549 return r->set_reg(cpu, mem_buf, reg - r->base_reg); in gdb_write_register()
556 gdb_get_reg_cb get_reg, gdb_set_reg_cb set_reg, in gdb_register_feature() argument
562 .set_reg = set_reg, in gdb_register_feature()
605 gdb_get_reg_cb get_reg, gdb_set_reg_cb set_reg, in gdb_register_coprocessor() argument
620 gdb_register_feature(cpu, base_reg, get_reg, set_reg, feature); in gdb_register_coprocessor()
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