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Searched refs:set_rate (Results 1 – 25 of 47) sorted by relevance

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/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3368.c282 static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate) in rk3368_ddr_set_clk() argument
292 switch (set_rate) { in rk3368_ddr_set_clk()
303 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate); in rk3368_ddr_set_clk()
307 return set_rate; in rk3368_ddr_set_clk()
312 static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru, ulong set_rate) in rk3368_gmac_set_clk() argument
322 ret = set_rate; in rk3368_gmac_set_clk()
338 div = DIV_ROUND_UP(pll_rate, set_rate) - 1; in rk3368_gmac_set_clk()
589 .set_rate = rk3368_clk_set_rate,
H A Dclk_rk3399.c750 ulong clk_id, ulong set_rate) in rk3399_mmc_set_clk() argument
760 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); in rk3399_mmc_set_clk()
764 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in rk3399_mmc_set_clk()
788 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate); in rk3399_mmc_set_clk()
828 ulong set_rate) in rk3399_ddr_set_clk() argument
836 switch (set_rate) { in rk3399_ddr_set_clk()
858 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate); in rk3399_ddr_set_clk()
862 return set_rate; in rk3399_ddr_set_clk()
1087 .set_rate = rk3399_clk_set_rate,
1363 .set_rate = rk3399_pmuclk_set_rate,
H A Dclk_rk322x.c317 static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate) in rk322x_ddr_set_clk() argument
322 switch (set_rate) { in rk322x_ddr_set_clk()
345 return set_rate; in rk322x_ddr_set_clk()
467 .set_rate = rk322x_clk_set_rate,
H A Dclk_rk3328.c467 ulong clk_id, ulong set_rate) in rk3328_mmc_set_clk() argument
486 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); in rk3328_mmc_set_clk()
490 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in rk3328_mmc_set_clk()
750 .set_rate = rk3328_clk_set_rate,
/openbmc/u-boot/drivers/clk/sifive/
H A Dfu540-prci.c187 int (*set_rate)(struct __prci_clock *pc, member
451 .set_rate = sifive_fu540_prci_wrpll_set_rate,
552 if (!pc->pd || !pc->ops->set_rate) in sifive_fu540_prci_set_rate()
555 err = pc->ops->set_rate(pc, rate, clk_get_rate(&pc->pd->parent)); in sifive_fu540_prci_set_rate()
587 .set_rate = sifive_fu540_prci_set_rate,
/openbmc/u-boot/include/
H A Dclk-uclass.h78 ulong (*set_rate)(struct clk *clk, ulong rate); member
/openbmc/u-boot/drivers/clk/at91/
H A Dclk-plladiv.c65 .set_rate = at91_plladiv_clk_set_rate,
H A Dclk-system.c100 .set_rate = system_clk_set_rate,
H A Dclk-usb.c104 .set_rate = at91_usb_clk_set_rate,
H A Dclk-generated.c146 .set_rate = generic_clk_set_rate,
/openbmc/u-boot/drivers/clk/tegra/
H A Dtegra-car-clk.c85 .set_rate = tegra_car_clk_set_rate,
H A Dtegra186-clk.c86 .set_rate = tegra186_clk_set_rate,
/openbmc/u-boot/drivers/clk/
H A Dclk_sandbox.c70 .set_rate = sandbox_clk_set_rate,
H A Dclk_vexpress_osc.c66 .set_rate = vexpress_osc_clk_set_rate,
H A Dclk-uclass.c349 if (!ops->set_rate) in clk_set_rate()
352 return ops->set_rate(clk, rate); in clk_set_rate()
H A Dclk-hsdk-cgu.c280 ulong (*set_rate)(struct clk *clk, ulong rate); member
670 return clock_map[sclk->id].set_rate(sclk, rate); in hsdk_cgu_set_rate()
685 .set_rate = hsdk_cgu_set_rate,
H A Dics8n3qv01.c208 .set_rate = ics8n3qv01_set_rate,
H A Dclk-ti-sci.c204 .set_rate = ti_sci_clk_set_rate,
/openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.c251 .set_rate = peri_clk_set_rate,
495 if (!c || !c->ops || !c->ops->set_rate) in clk_set_rate()
502 ret = c->ops->set_rate(c, rate); in clk_set_rate()
/openbmc/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.c251 .set_rate = peri_clk_set_rate,
495 if (!c || !c->ops || !c->ops->set_rate) in clk_set_rate()
502 ret = c->ops->set_rate(c, rate); in clk_set_rate()
/openbmc/u-boot/arch/arm/mach-snapdragon/
H A Dclock-snapdragon.c130 .set_rate = msm_clk_set_rate,
/openbmc/u-boot/drivers/video/
H A Dipu_common.c137 if (clk->set_rate) in clk_set_rate()
138 clk->set_rate(clk, rate); in clk_set_rate()
408 .set_rate = ipu_pixel_clk_set_rate,
419 .set_rate = ipu_pixel_clk_set_rate,
H A Dipu.h48 int (*set_rate) (struct clk *, unsigned long); member
/openbmc/u-boot/drivers/clk/imx/
H A Dclk-imx8.c372 .set_rate = imx8_clk_set_rate,
/openbmc/u-boot/drivers/clk/uniphier/
H A Dclk-uniphier-core.c246 .set_rate = uniphier_clk_set_rate,

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