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Searched refs:sdram (Results 1 – 25 of 148) sorted by relevance

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/openbmc/u-boot/board/freescale/m54418twr/
H A Dm54418twr.c38 sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); in dram_init() local
57 out_be32(&sdram->rcrcr, 0x40000000); in dram_init()
58 out_be32(&sdram->padcr, 0x01030203); in dram_init()
60 out_be32(&sdram->cr00, 0x01010101); in dram_init()
61 out_be32(&sdram->cr01, 0x00000101); in dram_init()
62 out_be32(&sdram->cr02, 0x01010100); in dram_init()
63 out_be32(&sdram->cr03, 0x01010000); in dram_init()
64 out_be32(&sdram->cr04, 0x00010101); in dram_init()
65 out_be32(&sdram->cr06, 0x00010100); in dram_init()
66 out_be32(&sdram->cr07, 0x00000001); in dram_init()
[all …]
/openbmc/linux/drivers/cpufreq/
H A Dsa1110-cpufreq.c144 struct sdram_params *sdram) in sdram_calculate_timing() argument
158 if ((ns_to_cycles(sdram->tck, sd_khz) > 1) || in sdram_calculate_timing()
164 twr = ns_to_cycles(sdram->twr, mem_khz); in sdram_calculate_timing()
167 trp = ns_to_cycles(sdram->trp, mem_khz) - 1; in sdram_calculate_timing()
173 sd->mdcnfg |= sdram->cas_latency << 12; in sdram_calculate_timing()
174 sd->mdcnfg |= sdram->cas_latency << 28; in sdram_calculate_timing()
186 ns_to_cycles(sdram->trcd, mem_khz)); in sdram_calculate_timing()
213 sdram_update_refresh(u_int cpu_khz, struct sdram_params *sdram) in sdram_update_refresh() argument
215 u_int ns_row = (sdram->refresh * 1000) >> sdram->rows; in sdram_update_refresh()
231 struct sdram_params *sdram = &sdram_params; in sa1110_target() local
[all …]
/openbmc/u-boot/board/freescale/m5208evbe/
H A Dm5208evbe.c26 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
37 out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
39 out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
41 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
42 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
47 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
51 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
52 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
56 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); in dram_init()
58 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
[all …]
/openbmc/u-boot/board/freescale/m5329evb/
H A Dm5329evb.c26 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
37 out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
38 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
39 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
42 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
45 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
46 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); in dram_init()
51 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
54 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
55 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
[all …]
/openbmc/u-boot/board/freescale/m53017evb/
H A Dm53017evb.c26 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
37 out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
39 out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
41 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
42 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
47 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
51 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
52 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
56 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); in dram_init()
58 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
[all …]
/openbmc/u-boot/board/freescale/m5373evb/
H A Dm5373evb.c26 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
37 out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
38 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
39 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
42 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
45 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
46 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); in dram_init()
51 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
54 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
55 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
[all …]
/openbmc/u-boot/board/freescale/m54451evb/
H A Dm54451evb.c38 sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); in dram_init() local
44 if ((in_be32(&sdram->sdcfg1) == CONFIG_SYS_SDRAM_CFG1) && in dram_init()
45 (in_be32(&sdram->sdcfg2) == CONFIG_SYS_SDRAM_CFG2)) in dram_init()
56 out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
58 out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
59 out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
64 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
68 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
70 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
74 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE); in dram_init()
[all …]
/openbmc/u-boot/doc/device-tree-bindings/memory-controllers/
H A Dst,stm32-fmc.txt8 on-board sdram memory attributes:
9 - st,sdram-control : parameters for sdram configuration, in this order:
18 - st,sdram-timing: timings for sdram, in this order:
27 include/dt-bindings/memory/stm32-sdram.h to define sdram control and timing
43 /* sdram memory configuration from sdram datasheet */
45 st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
47 st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
51 /* sdram memory configuration from sdram datasheet */
53 st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
55 st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
/openbmc/u-boot/board/freescale/m52277evb/
H A Dm52277evb.c34 sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); in dram_init() local
48 out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
50 out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
51 out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
54 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
58 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE); in dram_init()
60 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD); in dram_init()
66 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
70 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
72 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
[all …]
/openbmc/u-boot/board/freescale/m547xevb/
H A Dm547xevb.c28 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
55 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
56 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
59 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
62 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
63 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); in dram_init()
68 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
71 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
72 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
74 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); in dram_init()
[all …]
/openbmc/u-boot/board/freescale/m548xevb/
H A Dm548xevb.c28 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
55 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
56 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
59 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
62 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); in dram_init()
63 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); in dram_init()
68 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
71 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
72 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
74 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); in dram_init()
[all …]
/openbmc/u-boot/board/freescale/m54455evb/
H A Dm54455evb.c34 sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); in dram_init() local
48 out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i); in dram_init()
49 out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 | i); in dram_init()
51 out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
52 out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2); in dram_init()
55 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
58 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408); in dram_init()
59 out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x300); in dram_init()
64 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); in dram_init()
67 out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); in dram_init()
[all …]
/openbmc/u-boot/board/freescale/m5235evb/
H A Dm5235evb.c26 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in dram_init() local
52 if (!(in_be32(&sdram->dacr0) & SDRAMC_DARCn_RE)) { in dram_init()
56 out_be16(&sdram->dcr, SDRAMC_DCR_RTIM_9CLKS | in dram_init()
61 out_be32(&sdram->dacr0, in dram_init()
68 out_be32(&sdram->dmr0, in dram_init()
73 setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IP); in dram_init()
84 setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE); in dram_init()
92 setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IMRS); in dram_init()
/openbmc/linux/Documentation/devicetree/bindings/edac/
H A Daspeed-sdram-edac.txt15 - "aspeed,ast2400-sdram-edac"
16 - "aspeed,ast2500-sdram-edac"
17 - "aspeed,ast2600-sdram-edac"
18 - reg: sdram controller register set should be <0x1e6e0000 0x174>
24 edac: sdram@1e6e0000 {
25 compatible = "aspeed,ast2500-sdram-edac";
/openbmc/u-boot/arch/arm/mach-tegra/tegra20/
H A Dwarmboot.c124 struct sdram_params sdram; in warmboot_save_sdram_params() local
141 memcpy(&sdram, in warmboot_save_sdram_params()
143 sizeof(sdram)); in warmboot_save_sdram_params()
167 scratch2.memory_type = sdram.memory_type; in warmboot_save_sdram_params()
174 scratch4.emc_clock_divider = sdram.emc_clock_divider; in warmboot_save_sdram_params()
181 scratch24.emc_pin_program_wait = sdram.emc_pin_program_wait; in warmboot_save_sdram_params()
182 scratch24.emc_auto_cal_wait = sdram.emc_auto_cal_wait; in warmboot_save_sdram_params()
183 scratch24.warmboot_wait = sdram.warm_boot_wait; in warmboot_save_sdram_params()
/openbmc/u-boot/arch/arm/cpu/armv8/
H A Du-boot-spl.lds16 MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
61 } >.sdram
66 } >.sdram
70 } >.sdram
/openbmc/u-boot/arch/m68k/cpu/mcf532x/
H A Dspeed.c143 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); in clock_pll() local
199 if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF) in clock_pll()
200 clrbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE); in clock_pll()
232 if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF) in clock_pll()
233 setbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE); in clock_pll()
/openbmc/linux/Documentation/devicetree/bindings/arm/altera/
H A Dsocfpga-sdram-edac.txt5 - compatible : should contain "altr,sdram-edac" or "altr,sdram-edac-a10"
12 compatible = "altr,sdram-edac";
/openbmc/u-boot/arch/arm/dts/
H A Dstm32h743i-eval.dts46 #include <dt-bindings/memory/stm32-sdram.h>
89 * Memory configuration from sdram datasheet IS42S32800G-6BLI
94 st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4
96 st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2
98 st,sdram-refcount = <1539>;
H A Dstm32h743i-disco.dts46 #include <dt-bindings/memory/stm32-sdram.h>
90 * Memory configuration from sdram datasheet IS42S32800G-6BLI
95 st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4
97 st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2
99 st,sdram-refcount = <1539>;
H A Dstm32f429-disco-u-boot.dtsi7 #include <dt-bindings/memory/stm32-sdram.h>
45 * Memory configuration from sdram datasheet
49 st,sdram-control = /bits/ 8 <NO_COL_8
57 st,sdram-timing = /bits/ 8 <TMRD_3
63 st,sdram-refcount = < 1386 >;
H A Dstm32f469-disco-u-boot.dtsi7 #include <dt-bindings/memory/stm32-sdram.h>
45 * Memory configuration from sdram
49 st,sdram-control = /bits/ 8 <NO_COL_8
57 st,sdram-timing = /bits/ 8 <TMRD_2
64 st,sdram-refcount = < 1292 >;
H A Dstm32429i-eval-u-boot.dtsi7 #include <dt-bindings/memory/stm32-sdram.h>
45 * Memory configuration from sdram
49 st,sdram-control = /bits/ 8 <NO_COL_9
57 st,sdram-timing = /bits/ 8 <TMRD_2
64 st,sdram-refcount = < 2812 >;
/openbmc/u-boot/arch/arm/mach-aspeed/ast2500/
H A Du-boot-spl.lds11 sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
54 } > sdram
/openbmc/u-boot/arch/arm/mach-aspeed/ast2400/
H A Du-boot-spl.lds11 sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
54 } > sdram

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