Searched refs:sdm_cfg0 (Results 1 – 1 of 1) sorted by relevance
123 u32 sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3; in dsi_pll_28nm_clk_set_rate() local174 sdm_cfg0 = 0x0; in dsi_pll_28nm_clk_set_rate()175 sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(0); in dsi_pll_28nm_clk_set_rate()181 sdm_cfg0 = DSI_28nm_PHY_PLL_SDM_CFG0_BYP; in dsi_pll_28nm_clk_set_rate()182 sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV( in dsi_pll_28nm_clk_set_rate()189 DBG("sdm_cfg0=%d", sdm_cfg0); in dsi_pll_28nm_clk_set_rate()219 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0, sdm_cfg0); in dsi_pll_28nm_clk_set_rate()