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Searched refs:scr_el3 (Results 1 – 13 of 13) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/
H A Dmacro.h200 msr scr_el3, \tmp
218 msr scr_el3, \tmp
/openbmc/u-boot/arch/arm/cpu/armv8/
H A Dstart.S106 mrs x0, scr_el3
108 msr scr_el3, x0
/openbmc/qemu/target/arm/
H A Dcpu.c620 env->cp15.scr_el3 |= SCR_RW; in arm_emulate_firmware_reset()
622 env->cp15.scr_el3 |= SCR_API | SCR_APK; in arm_emulate_firmware_reset()
625 env->cp15.scr_el3 |= SCR_ATA; in arm_emulate_firmware_reset()
633 env->cp15.scr_el3 |= SCR_ENTP2; in arm_emulate_firmware_reset()
637 env->cp15.scr_el3 |= SCR_HXEN; in arm_emulate_firmware_reset()
640 env->cp15.scr_el3 |= SCR_FGTEN; in arm_emulate_firmware_reset()
646 env->cp15.scr_el3 |= SCR_HCE; in arm_emulate_firmware_reset()
650 env->cp15.scr_el3 |= SCR_NS; in arm_emulate_firmware_reset()
798 scr = (env->cp15.scr_el3 & SCR_FIQ); in arm_excp_unmasked()
806 scr = scr && !((env->cp15.scr_el3 in arm_excp_unmasked()
[all...]
H A Dhelper.c307 if (env->cp15.scr_el3 & SCR_EEL2) { in access_trap_aa32s_el1()
1957 changed = env->cp15.scr_el3 ^ value; in scr_write()
1958 env->cp15.scr_el3 = value; in scr_write()
2660 if (!(env->cp15.scr_el3 & SCR_ST)) { in gt_stimer_access()
2703 if (env->cp15.scr_el3 & SCR_EEL2) { in gt_rme_post_el_change()
2755 if ((env->cp15.scr_el3 & SCR_ECVEN) && in gt_recalc_timer()
3630 !(env->cp15.scr_el3 & SCR_ECVEN)) { in do_ats_write()
3727 if (env->cp15.scr_el3 & SCR_EEL2) { in do_ats_write()
3797 (env->cp15.scr_el3 & SCR_EA)) { in ats_write()
4028 if ((env->cp15.scr_el3 in pmsav7_write()
[all...]
H A Dcpu.h335 uint64_t scr_el3; /* Secure configuration register. */
2548 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); in arm_is_el2_enabled()
2622 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { in arm_el_is_aa64()
2623 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); in arm_el_is_aa64()
2648 !(env->cp15.scr_el3 & SCR_NS));
334 uint64_t scr_el3; /* Secure configuration register. */ global() member
H A Dinternals.h1373 && !(env->cp15.scr_el3 & SCR_ATA)) { in allocation_tag_access_enabled()
1758 (!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FGTEN)); in arm_fgt_active()
H A Dptw.c1416 if (env->cp15.scr_el3 & SCR_SIF) { in get_S1prot()
/openbmc/qemu/hw/intc/
H A Darm_gicv3_cpuif.c1114 (env->cp15.scr_el3 & SCR_FIQ)) { in icc_pmr_read()
1143 (env->cp15.scr_el3 & SCR_FIQ)) { in icc_pmr_write()
1920 route_fiq_to_el3 = env->cp15.scr_el3 & SCR_FIQ; in icc_dir_write()
1921 route_irq_to_el3 = env->cp15.scr_el3 & SCR_IRQ; in icc_dir_write()
1980 !arm_is_secure(env) && (env->cp15.scr_el3 & SCR_FIQ)) { in icc_rpr_read()
2282 if ((env->cp15.scr_el3 & (SCR_FIQ | SCR_IRQ)) == (SCR_FIQ | SCR_IRQ)) { in gicv3_irqfiq_access()
2345 if (env->cp15.scr_el3 & SCR_FIQ) { in gicv3_fiq_access()
2381 if (env->cp15.scr_el3 & SCR_IRQ) { in gicv3_irq_access()
/openbmc/qemu/target/arm/tcg/
H A Dop_helper.c358 if (env->cp15.scr_el3 & mask) { in check_wfx_trap()
1033 undef = !(env->cp15.scr_el3 & SCR_HCE); in HELPER()
1058 bool smd_flag = env->cp15.scr_el3 & SCR_SMD; in HELPER()
H A Dtlb_helper.c139 ret = (cpu->env.cp15.scr_el3 & SCR_GPF) && current_el != 3; in report_as_gpc_exception()
H A Dpauth_helper.c479 if (!(env->cp15.scr_el3 & SCR_API)) { in pauth_check_trap()
H A Dhelper-a64.c800 if (cur_el == 3 && (env->cp15.scr_el3 & (SCR_NS | SCR_NSE)) == SCR_NSE) { in HELPER()
H A Dtranslate.c2807 tcg_el = load_cpu_field_low32(cp15.scr_el3); in msr_banked_access_decode()