| /openbmc/qemu/target/riscv/ |
| H A D | monitor.c | 157 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; in mem_info_svxx()
158 vm = get_field(env->satp, SATP32_MODE); in mem_info_svxx()
160 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; in mem_info_svxx()
161 vm = get_field(env->satp, SATP64_MODE); in mem_info_svxx()
226 if (!(env->satp & SATP32_MODE)) { in hmp_info_mem()
231 if (!(env->satp & SATP64_MODE)) { in hmp_info_mem()
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| H A D | cpu_helper.c | 653 env->vsatp = env->satp; in riscv_cpu_swap_hypervisor_regs()
654 env->satp = env->satp_hs; in riscv_cpu_swap_hypervisor_regs()
676 env->satp_hs = env->satp; in riscv_cpu_swap_hypervisor_regs()
677 env->satp = env->vsatp; in riscv_cpu_swap_hypervisor_regs()
938 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; in get_physical_address()
939 vm = get_field(env->satp, SATP32_MODE); in get_physical_address()
941 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; in get_physical_address()
942 vm = get_field(env->satp, SATP64_MODE); in get_physical_address()
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| H A D | cpu.c | 426 /* Set the satp mode to the max supported */
435 warn_report("No satp mode set. Defaulting to 'bare'"); in set_satp_mode_default_map()
1065 /* The CPU wants the OS to decide which satp mode to use */ in riscv_cpu_satp_mode_finalize()
1075 /* If unset by the user, we fallback to the default satp mode. */ in riscv_cpu_satp_mode_finalize()
1117 error_setg(errp, "cannot disable %s satp mode if %s " in riscv_cpu_satp_mode_finalize()
1209 uint8_t satp = satp_mode_from_str(name); in cpu_riscv_get_satp() local
1212 value = satp_map->map & (1 << satp); in cpu_riscv_get_satp()
1221 uint8_t satp = satp_mode_from_str(name); in cpu_riscv_set_satp() local
1228 satp_map->map = deposit32(satp_map->map, satp, 1, value); in cpu_riscv_set_satp()
1229 satp_map->init |= 1 << satp; in cpu_riscv_set_satp()
[all...] |
| H A D | machine.c | 423 VMSTATE_UINTTL(env.satp, RISCVCPU),
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| H A D | cpu.h | 295 target_ulong satp; /* since: priv-1.10.0 */ member
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| H A D | csr.c | 515 static RISCVException satp(CPURISCVState *env, int csrno) in satp()
3395 *val = env->satp; in write_satp()
3406 env->satp = legalize_xatp(env, env->satp, val); in read_vstopi()
5189 [CSR_SATP] = { "satp", satp, read_satp, write_satp },
510 static RISCVException satp(CPURISCVState *env, int csrno) satp() function
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| /openbmc/linux/arch/riscv/kernel/ |
| H A D | suspend.c | 28 context->satp = csr_read(CSR_SATP); in suspend_save_csrs()
39 csr_write(CSR_SATP, context->satp); in suspend_restore_csrs()
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| H A D | hibernate-asm.S | 63 csrw satp, s1
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| /openbmc/qemu/hw/riscv/ |
| H A D | riscv-iommu.c | 60 uint64_t satp; /* S-Stage address translation and protection */ member
260 uint64_t satp, gatp, pte; in riscv_iommu_spa_fetch() local
275 satp = get_field(ctx->satp, RISCV_IOMMU_ATP_MODE_FIELD); in riscv_iommu_spa_fetch()
278 en_s = satp != RISCV_IOMMU_DC_FSC_MODE_BARE; in riscv_iommu_spa_fetch()
317 switch (pass ? gatp : satp) { in riscv_iommu_spa_fetch()
337 switch (pass ? gatp : satp) { in riscv_iommu_spa_fetch()
378 satp = PPN_PHYS(get_field(ctx->satp, RISCV_IOMMU_ATP_PPN_FIELD)); in riscv_iommu_spa_fetch()
379 addr = (en_s && en_g) ? satp : iotlb->iova; in riscv_iommu_spa_fetch()
380 base = en_g ? gatp : satp; in riscv_iommu_spa_fetch()
729 fsc_mode = get_field(ctx->satp, RISCV_IOMMU_DC_FSC_MODE); in riscv_iommu_validate_device_ctx()
[all …]
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| /openbmc/linux/tools/testing/selftests/kvm/lib/riscv/ |
| H A D | processor.c | 186 unsigned long satp; in riscv_vcpu_mmu_setup() local
201 satp = (vm->pgd >> PGTBL_PAGE_SIZE_SHIFT) & SATP_PPN; in riscv_vcpu_mmu_setup()
202 satp |= SATP_MODE_48; in riscv_vcpu_mmu_setup()
204 vcpu_set_reg(vcpu, RISCV_CSR_REG(satp), satp); in riscv_vcpu_mmu_setup()
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| /openbmc/linux/arch/riscv/include/asm/ |
| H A D | suspend.h | 20 unsigned long satp; member
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| /openbmc/u-boot/arch/riscv/cpu/ |
| H A D | cpu.c | 86 csr_write(satp, 0); in arch_cpu_init_dm()
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| /openbmc/linux/arch/riscv/include/uapi/asm/ |
| H A D | kvm.h | 81 unsigned long satp; member
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| /openbmc/qemu/linux-headers/asm-riscv/ |
| H A D | kvm.h | 80 unsigned long satp; member
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| /openbmc/qemu/target/arm/tcg/ |
| H A D | mve_helper.c | 1250 #define WRAP_QRSHL_HELPER(FN, N, M, ROUND, satp) \ argument
1255 *satp = true; \
1260 #define DO_SQSHL_OP(N, M, satp) \ argument
1261 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, false, satp)
1262 #define DO_UQSHL_OP(N, M, satp) \ argument
1263 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, false, satp)
1264 #define DO_SQRSHL_OP(N, M, satp) \ argument
1265 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
1266 #define DO_UQRSHL_OP(N, M, satp) \ argument
1267 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
[all …]
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| /openbmc/linux/tools/testing/selftests/kvm/riscv/ |
| H A D | get-reg-list.c | 208 case KVM_REG_RISCV_CSR_REG(satp): in general_csr_id_to_str()
209 return RISCV_CSR_GENERAL(satp); in general_csr_id_to_str()
533 …| KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(satp),
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| /openbmc/qemu/target/riscv/kvm/ |
| H A D | kvm-cpu.c | 620 KVM_RISCV_GET_CSR(cs, env, satp, env->satp); in kvm_riscv_get_regs_csr()
637 KVM_RISCV_SET_CSR(cs, env, satp, env->satp); in kvm_riscv_put_regs_csr()
1620 env->satp = 0; in kvm_riscv_reset_vcpu()
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| /openbmc/linux/Documentation/riscv/ |
| H A D | boot.rst | 34 * ``$satp = 0``: the MMU, if present, must be disabled.
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| /openbmc/linux/Documentation/virt/kvm/ |
| H A D | api.rst | 2792 0x80x0 0000 0300 0008 satp Supervisor address translation and protection
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