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Searched refs:rt_sysc_r32 (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/arch/mips/pci/
H A Dpci-rt3883.c306 rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); in rt3883_pci_preinit()
307 syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1); in rt3883_pci_preinit()
308 clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); in rt3883_pci_preinit()
319 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); in rt3883_pci_preinit()
323 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); in rt3883_pci_preinit()
327 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); in rt3883_pci_preinit()
331 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); in rt3883_pci_preinit()
381 t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); in rt3883_pci_preinit()
388 t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); in rt3883_pci_preinit()
392 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); in rt3883_pci_preinit()
H A Dpci-mt7620.c243 if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) { in mt7620_pci_hw_init()
/openbmc/linux/arch/mips/include/asm/mach-ralink/
H A Dralink_regs.h40 static inline u32 rt_sysc_r32(unsigned reg) in rt_sysc_r32() function
47 u32 val = rt_sysc_r32(reg) & ~clr; in rt_sysc_m32()
H A Dmt7620.h62 return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK; in mt7620_get_eco()
/openbmc/linux/drivers/watchdog/
H A Drt2880_wdt.c121 if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE) in rt288x_wdt_bootcause()
/openbmc/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mtmips.c141 mode = rt_sysc_r32(reg); in mtmips_pmx_group_enable()