Home
last modified time | relevance | path

Searched refs:rslr1 (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sun4i.h26 u32 rslr1; /* 0x50 rank system latency register */ member
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun4i.c370 u32 slr = readl(rank == 0 ? &dram->rslr0 : &dram->rslr1); in mctl_set_dqs_gating_delay()
380 writel(slr, rank == 0 ? &dram->rslr0 : &dram->rslr1); in mctl_set_dqs_gating_delay()