Searched refs:rslr0 (Results 1 – 2 of 2) sorted by relevance
25 u32 rslr0; /* 0x4c rank system latency register */ member
370 u32 slr = readl(rank == 0 ? &dram->rslr0 : &dram->rslr1); in mctl_set_dqs_gating_delay()380 writel(slr, rank == 0 ? &dram->rslr0 : &dram->rslr1); in mctl_set_dqs_gating_delay()