Searched refs:rlar (Results 1 – 6 of 6) sorted by relevance
/openbmc/qemu/target/arm/ |
H A D | cpu.c | 500 memset(env->pmsav8.rlar[M_REG_NS], 0, in arm_cpu_reset_hold() 501 sizeof(*env->pmsav8.rlar[M_REG_NS]) in arm_cpu_reset_hold() 507 memset(env->pmsav8.rlar[M_REG_S], 0, in arm_cpu_reset_hold() 508 sizeof(*env->pmsav8.rlar[M_REG_S]) in arm_cpu_reset_hold() 539 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); in arm_cpu_reset_hold() 2469 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); in arm_cpu_realizefn() 2472 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); in arm_cpu_realizefn() 2505 env->sau.rlar = g_new0(uint32_t, nr); in arm_cpu_realizefn()
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H A D | machine.c | 661 VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_NS], ARMCPU, pmsav7_dregion, 713 VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dregion, 725 VMSTATE_VARRAY_UINT32(env.sau.rlar, ARMCPU, sau_sregion, 0,
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H A D | ptw.c | 2569 return env->pmsav8.rlar[secure]; in regime_rlar() 2829 if (env->sau.rlar[r] & 1) { in v8m_security_lookup() 2831 uint32_t limit = env->sau.rlar[r] | 0x1f; in v8m_security_lookup() 2849 if (env->sau.rlar[r] & 2) { in v8m_security_lookup()
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H A D | cpu.h | 753 uint32_t *rlar[M_REG_NUM_BANKS]; member 764 uint32_t *rlar; member
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H A D | helper.c | 4055 env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value; in prlar_write() 4060 return env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]]; in prlar_read() 4182 env->pmsav8.rlar[M_REG_NS][index] = value; in pmsav8r_regn_write() 4209 return env->pmsav8.rlar[M_REG_NS][index]; in pmsav8r_regn_read()
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/openbmc/qemu/hw/intc/ |
H A D | armv7m_nvic.c | 1408 return cpu->env.pmsav8.rlar[attrs.secure][region]; in nvic_readl() 1479 return cpu->env.sau.rlar[region]; in nvic_readl() 1924 cpu->env.pmsav8.rlar[attrs.secure][region] = value; in nvic_writel() 2021 cpu->env.sau.rlar[region] = value & ~0x1c; in nvic_writel()
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