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Searched refs:rl_min_phase (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_hw_training.c492 DEBUG_MAIN_FULL_C("Min RL Phase: ", dram_info->rl_min_phase, 2); in ddr3_set_performance_params()
505 tmp2 = (dram_info->wl_max_phase - dram_info->rl_min_phase) / 2 + in ddr3_set_performance_params()
506 ((dram_info->wl_max_phase - dram_info->rl_min_phase) % 2 > in ddr3_set_performance_params()
H A Dddr3_read_leveling.c94 dram_info->rl_min_phase = 10; in ddr3_read_leveling_hw()
114 if (phase < dram_info->rl_min_phase) in ddr3_read_leveling_hw()
115 dram_info->rl_min_phase = phase; in ddr3_read_leveling_hw()
H A Dddr3_hw_training.h262 u32 rl_min_phase; member