Searched refs:riscv_csrrw (Results 1 – 3 of 3) sorted by relevance
| /openbmc/qemu/target/riscv/ |
| H A D | cpu.h | 780 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
791 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); in riscv_csr_write()
797 riscv_csrrw(env, csrno, &val, 0, 0); in riscv_csr_read()
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| H A D | op_helper.c | 65 RISCVException ret = riscv_csrrw(env, csr, NULL, src, mask); in helper_csrw()
76 RISCVException ret = riscv_csrrw(env, csr, &val, src, write_mask); in helper_csrrw()
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| H A D | csr.c | 4828 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, in riscv_csrrw() function
4960 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); in riscv_csrrw_debug()
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