| /openbmc/qemu/target/arm/ |
| H A D | cortex-regs.c | 40 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
43 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
46 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
49 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
52 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
55 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
58 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
61 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
64 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
67 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
[all …]
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| H A D | helper.c | 104 return ri->resetvalue; in raw_accessors_invalid()
442 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
447 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
464 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
470 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
481 .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0,
526 .resetvalue = 0 }, in cpacr_write()
529 .resetvalue = 0 }, in cpacr_write()
533 .resetvalue = 0 }, in cpacr_write()
541 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue in cpacr_write()
[all...] |
| H A D | debug_helper.c | 960 .type = ARM_CP_CONST | ARM_CP_NO_GDB, .resetvalue = 0 },
964 .type = ARM_CP_CONST, .resetvalue = 0 },
967 .type = ARM_CP_CONST | ARM_CP_NO_GDB, .resetvalue = 0 },
975 .resetvalue = 0 },
983 .type = ARM_CP_CONST, .resetvalue = 0 },
993 .type = ARM_CP_CONST, .resetvalue = 0 },
997 .type = ARM_CP_CONST, .resetvalue = 0 },
1002 .type = ARM_CP_CONST, .resetvalue = 0 },
1006 .type = ARM_CP_CONST, .resetvalue = 0 },
1011 .type = ARM_CP_CONST, .resetvalue = 0 },
[all …]
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| H A D | cpregs-pmu.c | 1034 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
1101 .resetvalue = 0, },
1109 .resetvalue = 0, },
1135 .resetvalue = 0,
1141 .resetvalue = 0,
1148 .resetvalue = 0,
1157 .resetvalue = 0x0 },
1219 .resetvalue = cpu->isar.reset_pmcr_el0, in define_pm_cpregs()
1236 .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO, in define_pm_cpregs()
1293 .resetvalue = extract64(cpu->pmceid0, 0, 32) }, in define_pm_cpregs()
[all …]
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| H A D | cpregs.h | 59 /* Flag: reads produce resetvalue; writes ignored. */
122 * - C_NZ: set const on the cpreg, but retain resetvalue,
123 * - else: set const on the cpreg, zero resetvalue, aka RES0.
986 uint64_t resetvalue;
1045 * by writing resetvalue to the field specified in fieldoffset. If
919 uint64_t resetvalue; global() member
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| H A D | cpu.c | 198 raw_write(&cpu->env, ri, ri->resetvalue); in cp_reg_reset()
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| /openbmc/qemu/target/arm/tcg/ |
| H A D | cpu64.c | 558 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
563 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
566 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
569 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
572 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
575 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, in define_neoverse_v1_cp_reginfo()
579 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, in define_neoverse_v1_cp_reginfo()
583 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, in aarch64_neoverse_n1_initfn()
591 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 }, in aarch64_neoverse_n1_initfn()
594 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue in aarch64_neoverse_n1_initfn()
[all...] |
| H A D | cpu32.c | 195 .resetvalue = 0 in arm1026_initfn()
337 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
339 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
389 .access = PL1_RW, .resetvalue = 0,
392 .access = PL1_RW, .resetvalue = 0,
395 .access = PL1_RW, .resetvalue = 0,
398 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
401 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
403 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
405 .access = PL1_RW, .resetvalue
[all...] |
| H A D | translate.c | 1886 tmp64 = tcg_constant_i64(ri->resetvalue); in disas_iwmmxt_insn()
1906 tmp = tcg_constant_i32(ri->resetvalue); in disas_iwmmxt_insn()
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| H A D | translate-a64.c | 3104 tcg_gen_movi_i64(tcg_rt, ri->resetvalue); in gen_compare_and_swap_pair()
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| /openbmc/u-boot/arch/nios2/dts/ |
| H A D | 3c120_devboard.dts | 145 resetvalue = <255>;
159 resetvalue = <0>;
173 resetvalue = <0>;
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| H A D | 10m50_devboard.dts | 200 resetvalue = <15>;
224 resetvalue = <0>;
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| /openbmc/u-boot/doc/device-tree-bindings/gpio/ |
| H A D | altera_pio.txt | 19 resetvalue = <255>;
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| /openbmc/qemu/hw/intc/ |
| H A D | arm_gicv3_cpuif.c | 2576 .resetvalue = 0x7,
2602 .resetvalue = 0xf,
2618 .resetvalue = 0xf,
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| /openbmc/qemu/target/arm/hvf/ |
| H A D | hvf.c | 1171 *val = ri->resetvalue; in hvf_handle_psci_call()
|