Searched refs:reserved_bits (Results 1 – 8 of 8) sorted by relevance
397 u64 reserved_bits, diff; in intel_pmu_set_msr() local447 reserved_bits = pmu->reserved_bits; in intel_pmu_set_msr()450 reserved_bits ^= HSW_IN_TX_CHECKPOINTED; in intel_pmu_set_msr()451 if (data & reserved_bits) in intel_pmu_set_msr()561 pmu->reserved_bits ^= HSW_IN_TX; in intel_pmu_refresh()583 pmu->reserved_bits &= ~ICL_EVENTSEL_ADAPTIVE; in intel_pmu_refresh()
31 reserved_bits:6; member
2651 reserved_bits |= CR4_OSXSAVE_MASK; in cr4_reserved_bits()2654 reserved_bits |= CR4_SMEP_MASK; in cr4_reserved_bits()2657 reserved_bits |= CR4_SMAP_MASK; in cr4_reserved_bits()2660 reserved_bits |= CR4_FSGSBASE_MASK; in cr4_reserved_bits()2663 reserved_bits |= CR4_PKE_MASK; in cr4_reserved_bits()2666 reserved_bits |= CR4_LA57_MASK; in cr4_reserved_bits()2669 reserved_bits |= CR4_UMIP_MASK; in cr4_reserved_bits()2672 reserved_bits |= CR4_PKS_MASK; in cr4_reserved_bits()2675 reserved_bits |= CR4_LAM_SUP_MASK; in cr4_reserved_bits()2678 reserved_bits |= CR4_FRED_MASK; in cr4_reserved_bits()[all …]
170 data &= ~pmu->reserved_bits; in amd_pmu_set_msr()212 pmu->reserved_bits = 0xfffffff000280000ull; in amd_pmu_refresh()
200 u8 reserved_bits : 7; member
710 pmu->reserved_bits = 0xffffffff00200000ull; in kvm_pmu_refresh()
489 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | in kvm_set_apic_base() local492 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) in kvm_set_apic_base()
527 u64 reserved_bits; member