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Searched refs:reg_value (Results 1 – 18 of 18) sorted by relevance

/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dfreeze_controller.c28 u32 reg_value; in sys_mgr_frzctrl_freeze_req() local
80 reg_value = readl(&freeze_controller_base->hioctrl); in sys_mgr_frzctrl_freeze_req()
84 reg_value in sys_mgr_frzctrl_freeze_req()
85 = (reg_value & ~reg_cfg_mask) in sys_mgr_frzctrl_freeze_req()
88 writel(reg_value, &freeze_controller_base->hioctrl); in sys_mgr_frzctrl_freeze_req()
94 reg_value = readl(&freeze_controller_base->hioctrl); in sys_mgr_frzctrl_freeze_req()
95 reg_value in sys_mgr_frzctrl_freeze_req()
96 = (reg_value & in sys_mgr_frzctrl_freeze_req()
99 writel(reg_value, &freeze_controller_base->hioctrl); in sys_mgr_frzctrl_freeze_req()
110 u32 reg_value; in sys_mgr_frzctrl_thaw_req() local
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/openbmc/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3399.c164 u32 reg_value; in set_ds_odt() local
211 reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) | in set_ds_odt()
214 clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value); in set_ds_odt()
215 clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value); in set_ds_odt()
216 clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value); in set_ds_odt()
217 clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value); in set_ds_odt()
224 clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value); in set_ds_odt()
225 clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value); in set_ds_odt()
226 clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value); in set_ds_odt()
227 clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value); in set_ds_odt()
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/openbmc/u-boot/drivers/net/phy/
H A Dcortina.c214 fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) & in cs4340_upload_firmware()
216 phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value); in cs4340_upload_firmware()
226 int reg_value; in cs4340_phy_init() local
240 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS); in cs4340_phy_init()
241 if (reg_value & mseq_edc_bist_done) { in cs4340_phy_init()
242 if (0 == (reg_value & mseq_edc_bist_fail)) in cs4340_phy_init()
256 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS); in cs4340_phy_init()
257 if (reg_value) { in cs4340_phy_init()
289 int reg_value; in cs4223_phy_init() local
291 reg_value = phy_read(phydev, 0x00, CS4223_EEPROM_STATUS); in cs4223_phy_init()
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/openbmc/qemu/hw/gpio/
H A Dimx_gpio.c147 uint32_t reg_value = 0; in imx_gpio_read() local
155 reg_value = (s->dr & s->gdir) | (s->psr & ~s->gdir); in imx_gpio_read()
159 reg_value = s->gdir; in imx_gpio_read()
163 reg_value = s->psr & ~s->gdir; in imx_gpio_read()
167 reg_value = extract64(s->icr, 0, 32); in imx_gpio_read()
171 reg_value = extract64(s->icr, 32, 32); in imx_gpio_read()
175 reg_value = s->imr; in imx_gpio_read()
179 reg_value = s->isr; in imx_gpio_read()
184 reg_value = s->edge_sel; in imx_gpio_read()
199 reg_value); in imx_gpio_read()
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/openbmc/qemu/hw/timer/
H A Dcadence_ttc.c140 if (is_between(cand, (uint64_t)s->reg_value, next_value)) { in cadence_timer_run()
148 event_interval = next_value - (int64_t)s->reg_value; in cadence_timer_run()
172 x = (int64_t)s->reg_value + ((s->reg_count & COUNTER_CTRL_DEC) ? -r : r); in cadence_timer_sync()
181 if (is_between(m, s->reg_value, x) || in cadence_timer_sync()
182 is_between(m + interval, s->reg_value, x) || in cadence_timer_sync()
183 is_between(m - interval, s->reg_value, x)) { in cadence_timer_sync()
194 s->reg_value = (uint32_t)(x % interval); in cadence_timer_sync()
229 return (uint16_t)(s->reg_value >> 16); in cadence_ttc_read_imp()
309 s->reg_value = 0; in cadence_ttc_write()
431 VMSTATE_UINT32(reg_value, CadenceTimerState),
H A Dimx_gpt.c266 uint32_t reg_value = 0; in imx_gpt_read() local
270 reg_value = s->cr; in imx_gpt_read()
274 reg_value = s->pr; in imx_gpt_read()
278 reg_value = s->sr; in imx_gpt_read()
282 reg_value = s->ir; in imx_gpt_read()
286 reg_value = s->ocr1; in imx_gpt_read()
290 reg_value = s->ocr2; in imx_gpt_read()
294 reg_value = s->ocr3; in imx_gpt_read()
300 reg_value = s->icr1; in imx_gpt_read()
306 reg_value = s->icr2; in imx_gpt_read()
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H A Dimx_epit.c121 uint32_t reg_value = 0; in imx_epit_read() local
125 reg_value = s->cr; in imx_epit_read()
129 reg_value = s->sr; in imx_epit_read()
133 reg_value = s->lr; in imx_epit_read()
137 reg_value = s->cmp; in imx_epit_read()
141 reg_value = ptimer_get_count(s->timer_reload); in imx_epit_read()
150 DPRINTF("(%s) = 0x%08x\n", imx_epit_reg_name(offset >> 2), reg_value); in imx_epit_read()
152 return reg_value; in imx_epit_read()
/openbmc/qemu/hw/acpi/
H A Derst.c176 uint64_t reg_value; member
802 s->reg_value = erst_wr_reg64(addr, s->reg_value, val, size); in erst_reg_write()
820 s->record_offset = s->reg_value; in erst_reg_write()
823 if ((uint8_t)s->reg_value == ERST_EXECUTE_OPERATION_MAGIC) { in erst_reg_write()
849 s->reg_value = s->busy_status; in erst_reg_write()
852 s->reg_value = s->command_status; in erst_reg_write()
856 &s->reg_value, false); in erst_reg_write()
859 s->record_identifier = s->reg_value; in erst_reg_write()
862 s->reg_value = le32_to_cpu(s->header->record_count); in erst_reg_write()
865 s->reg_value = (hwaddr)pci_get_bar_addr(PCI_DEVICE(s), 1); in erst_reg_write()
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/openbmc/qemu/hw/display/
H A Dcirrus_vga.c1082 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value) in cirrus_write_bitblt() argument
1087 s->vga.gr[0x31] = reg_value; in cirrus_write_bitblt()
1090 ((reg_value & CIRRUS_BLT_RESET) == 0)) { in cirrus_write_bitblt()
1093 ((reg_value & CIRRUS_BLT_START) != 0)) { in cirrus_write_bitblt()
1426 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value) in cirrus_write_hidden_dac() argument
1429 s->cirrus_hidden_dac_data = reg_value; in cirrus_write_hidden_dac()
1431 printf("cirrus: outport hidden DAC, value %02x\n", reg_value); in cirrus_write_hidden_dac()
1460 static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value) in cirrus_vga_write_palette() argument
1462 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value; in cirrus_vga_write_palette()
1511 cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value) in cirrus_vga_write_gr() argument
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/openbmc/u-boot/drivers/usb/musb-new/
H A Dsunxi.c174 u32 reg_value; in USBC_ConfigFIFO_Base() local
177 reg_value = readl(SUNXI_SRAMC_BASE + 0x04); in USBC_ConfigFIFO_Base()
178 reg_value &= ~(0x03 << 0); in USBC_ConfigFIFO_Base()
179 reg_value |= BIT(0); in USBC_ConfigFIFO_Base()
180 writel(reg_value, SUNXI_SRAMC_BASE + 0x04); in USBC_ConfigFIFO_Base()
/openbmc/qemu/include/hw/timer/
H A Dcadence_ttc.h30 uint32_t reg_value; member
/openbmc/u-boot/drivers/video/sunxi/
H A Dsunxi_de2.c39 u32 reg_value; in sunxi_de2_composer_init() local
42 reg_value = readl(SUNXI_SRAMC_BASE + 0x04); in sunxi_de2_composer_init()
43 reg_value &= ~(0x01 << 24); in sunxi_de2_composer_init()
44 writel(reg_value, SUNXI_SRAMC_BASE + 0x04); in sunxi_de2_composer_init()
/openbmc/u-boot/drivers/phy/allwinner/
H A Dphy-sun4i-usb.c185 u32 bits, reg_value; in sun4i_usb_phy_passby() local
198 reg_value = readl(usb_phy->pmu); in sun4i_usb_phy_passby()
201 reg_value |= bits; in sun4i_usb_phy_passby()
203 reg_value &= ~bits; in sun4i_usb_phy_passby()
205 writel(reg_value, usb_phy->pmu); in sun4i_usb_phy_passby()
/openbmc/u-boot/include/
H A Dcortina.h76 unsigned short reg_value; member
/openbmc/qemu/tests/tcg/plugins/
H A Dinsn.c90 g_autoptr(GByteArray) reg_value = g_byte_array_new(); in vcpu_init()
96 int count = qemu_plugin_read_register(rd->handle, reg_value); in vcpu_init()
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_hw_training.h288 u32 reg_value; member
293 u32 reg_value; member
H A Dddr3_init.c792 ddr_mode->vals[j].reg_value); in ddr3_static_training_init()
890 ddr_mode->regs[j].reg_value); in ddr3_static_mc_init()
/openbmc/qemu/hw/rtc/
H A Dexynos4210_rtc.c200 uint32_t reg_value) in exynos4210_rtc_update_freq() argument
206 s->freq = RTC_BASE_FREQ / (1 << TICCKSEL(reg_value)); in exynos4210_rtc_update_freq()