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Searched refs:reg_value (Results 1 – 25 of 138) sorted by relevance

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/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dfreeze_controller.c28 u32 reg_value; in sys_mgr_frzctrl_freeze_req() local
80 reg_value = readl(&freeze_controller_base->hioctrl); in sys_mgr_frzctrl_freeze_req()
84 reg_value in sys_mgr_frzctrl_freeze_req()
85 = (reg_value & ~reg_cfg_mask) in sys_mgr_frzctrl_freeze_req()
88 writel(reg_value, &freeze_controller_base->hioctrl); in sys_mgr_frzctrl_freeze_req()
94 reg_value = readl(&freeze_controller_base->hioctrl); in sys_mgr_frzctrl_freeze_req()
95 reg_value in sys_mgr_frzctrl_freeze_req()
96 = (reg_value & in sys_mgr_frzctrl_freeze_req()
99 writel(reg_value, &freeze_controller_base->hioctrl); in sys_mgr_frzctrl_freeze_req()
110 u32 reg_value; in sys_mgr_frzctrl_thaw_req() local
[all …]
/openbmc/linux/drivers/media/spi/
H A Dgs1662.c54 u16 reg_value; member
59 u16 reg_value; member
235 if (reg_fmt[i].reg_value == std) { in gs_status_format()
251 return reg_fmt[i].reg_value | MASK_FORCE_STD; in get_register_timings()
266 int reg_value; in gs_s_dv_timings() local
268 reg_value = get_register_timings(timings); in gs_s_dv_timings()
269 if (reg_value == 0x0) in gs_s_dv_timings()
290 u16 reg_value, i; in gs_query_dv_timings() local
301 gs_read_register(gs->pdev, REG_LINES_PER_FRAME + i, &reg_value); in gs_query_dv_timings()
302 if (reg_value) in gs_query_dv_timings()
[all …]
/openbmc/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3399.c164 u32 reg_value; in set_ds_odt() local
211 reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) | in set_ds_odt()
214 clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value); in set_ds_odt()
215 clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value); in set_ds_odt()
216 clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value); in set_ds_odt()
217 clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value); in set_ds_odt()
224 clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value); in set_ds_odt()
225 clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value); in set_ds_odt()
226 clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value); in set_ds_odt()
227 clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value); in set_ds_odt()
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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmmhub_v1_8.c703 uint32_t reg_value; in mmhub_v1_8_inst_query_ras_err_status() local
710 reg_value = RREG32_SOC15_OFFSET(MMHUB, mmhub_inst, in mmhub_v1_8_inst_query_ras_err_status()
713 if (REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_STATUS) || in mmhub_v1_8_inst_query_ras_err_status()
714 REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_WRRSP_STATUS) || in mmhub_v1_8_inst_query_ras_err_status()
715 REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) { in mmhub_v1_8_inst_query_ras_err_status()
718 i, mmhub_inst, reg_value); in mmhub_v1_8_inst_query_ras_err_status()
723 reg_value = RREG32_SOC15(MMHUB, mmhub_inst, regMM_CANE_ERR_STATUS); in mmhub_v1_8_inst_query_ras_err_status()
724 if (REG_GET_FIELD(reg_value, MM_CANE_ERR_STATUS, SDPM_RDRSP_STATUS) || in mmhub_v1_8_inst_query_ras_err_status()
725 REG_GET_FIELD(reg_value, MM_CANE_ERR_STATUS, SDPM_WRRSP_STATUS) || in mmhub_v1_8_inst_query_ras_err_status()
726 REG_GET_FIELD(reg_value, MM_CANE_ERR_STATUS, SDPM_RDRSP_DATAPARITY_ERROR)) { in mmhub_v1_8_inst_query_ras_err_status()
[all …]
H A Dsdma_v4_4.c201 uint32_t reg_value = 0; in sdma_v4_4_query_ras_error_count_by_instance() local
205 reg_value = RREG32(reg_offset); in sdma_v4_4_query_ras_error_count_by_instance()
207 if (reg_value) in sdma_v4_4_query_ras_error_count_by_instance()
208 sdma_v4_4_get_ras_error_count(adev, regSDMA0_EDC_COUNTER, reg_value, in sdma_v4_4_query_ras_error_count_by_instance()
212 reg_value = RREG32(reg_offset); in sdma_v4_4_query_ras_error_count_by_instance()
214 if (reg_value) in sdma_v4_4_query_ras_error_count_by_instance()
215 sdma_v4_4_get_ras_error_count(adev, regSDMA0_EDC_COUNTER2, reg_value, in sdma_v4_4_query_ras_error_count_by_instance()
H A Dumc_v6_7.c64 uint64_t reg_value; in umc_v6_7_query_error_status_helper() local
75 reg_value = RREG64_PCIE((mc_umc_addr + umc_reg_offset) * 4); in umc_v6_7_query_error_status_helper()
76 if (reg_value) in umc_v6_7_query_error_status_helper()
77 dev_info(adev->dev, "MCA IPID 0x%llx, umc_reg_offset 0x%x\n", reg_value, umc_reg_offset); in umc_v6_7_query_error_status_helper()
82 reg_value = RREG64_PCIE((mc_umc_addr + umc_reg_offset) * 4); in umc_v6_7_query_error_status_helper()
83 if (reg_value) in umc_v6_7_query_error_status_helper()
84 dev_info(adev->dev, "MCA SYND 0x%llx, umc_reg_offset 0x%x\n", reg_value, umc_reg_offset); in umc_v6_7_query_error_status_helper()
89 reg_value = RREG64_PCIE((mc_umc_addr + umc_reg_offset) * 4); in umc_v6_7_query_error_status_helper()
90 if (reg_value) in umc_v6_7_query_error_status_helper()
91 dev_info(adev->dev, "MCA MISC0 0x%llx, umc_reg_offset 0x%x\n", reg_value, umc_reg_offset); in umc_v6_7_query_error_status_helper()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/
H A Ddm_services.h89 uint32_t reg_value, in get_reg_field_value_ex() argument
93 return (mask & reg_value) >> shift; in get_reg_field_value_ex()
96 #define get_reg_field_value(reg_value, reg_name, reg_field)\ argument
98 (reg_value),\
103 uint32_t reg_value, in set_reg_field_value_ex() argument
109 return (reg_value & ~mask) | (mask & (value << shift)); in set_reg_field_value_ex()
112 #define set_reg_field_value(reg_value, value, reg_name, reg_field)\ argument
113 (reg_value) = set_reg_field_value_ex(\
114 (reg_value),\
165 #define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\ argument
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/openbmc/linux/drivers/media/dvb-frontends/cxd2880/
H A Dcxd2880_tnrdmd_dvbt_mon.c392 u16 *reg_value) in dvbt_read_snr_reg() argument
397 if (!tnr_dmd || !reg_value) in dvbt_read_snr_reg()
428 *reg_value = (rdata[0] << 8) | rdata[1]; in dvbt_read_snr_reg()
434 u32 reg_value, int *snr) in dvbt_calc_snr() argument
439 if (reg_value == 0) in dvbt_calc_snr()
442 if (reg_value > 4996) in dvbt_calc_snr()
443 reg_value = 4996; in dvbt_calc_snr()
445 *snr = intlog10(reg_value) - intlog10(5350 - reg_value); in dvbt_calc_snr()
454 u16 reg_value = 0; in cxd2880_tnrdmd_dvbt_mon_snr() local
472 ret = dvbt_read_snr_reg(tnr_dmd, &reg_value); in cxd2880_tnrdmd_dvbt_mon_snr()
[all …]
/openbmc/qemu/hw/gpio/
H A Daspeed_gpio.c675 uint32_t reg_value = 0; in aspeed_gpio_write_index_mode() local
688 reg_value = set->data_read; in aspeed_gpio_write_index_mode()
689 reg_value = deposit32(reg_value, pin_idx, 1, in aspeed_gpio_write_index_mode()
691 reg_value &= props->output; in aspeed_gpio_write_index_mode()
692 reg_value = update_value_control_source(set, set->data_value, in aspeed_gpio_write_index_mode()
693 reg_value); in aspeed_gpio_write_index_mode()
694 set->data_read = reg_value; in aspeed_gpio_write_index_mode()
695 aspeed_gpio_update(s, set, reg_value, set->direction); in aspeed_gpio_write_index_mode()
698 reg_value = set->direction; in aspeed_gpio_write_index_mode()
699 reg_value = deposit32(reg_value, pin_idx, 1, in aspeed_gpio_write_index_mode()
[all …]
H A Dimx_gpio.c152 uint32_t reg_value = 0; in imx_gpio_read() local
160 reg_value = (s->dr & s->gdir) | (s->psr & ~s->gdir); in imx_gpio_read()
164 reg_value = s->gdir; in imx_gpio_read()
168 reg_value = s->psr & ~s->gdir; in imx_gpio_read()
172 reg_value = extract64(s->icr, 0, 32); in imx_gpio_read()
176 reg_value = extract64(s->icr, 32, 32); in imx_gpio_read()
180 reg_value = s->imr; in imx_gpio_read()
184 reg_value = s->isr; in imx_gpio_read()
189 reg_value = s->edge_sel; in imx_gpio_read()
203 DPRINTF("(%s) = 0x%" PRIx32 "\n", imx_gpio_reg_name(offset), reg_value); in imx_gpio_read()
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/openbmc/linux/drivers/clk/
H A Dclk-max9485.c36 u8 reg_value; member
80 u8 reg_value; member
96 drvdata->reg_value &= ~mask; in max9485_update_bits()
97 drvdata->reg_value |= value; in max9485_update_bits()
101 mask, value, drvdata->reg_value); in max9485_update_bits()
104 &drvdata->reg_value, in max9485_update_bits()
105 sizeof(drvdata->reg_value)); in max9485_update_bits()
144 entry->reg_value); in max9485_clkout_set_rate()
152 u8 val = drvdata->reg_value & MAX9485_FREQ_MASK; in max9485_clkout_recalc_rate()
156 if (val == entry->reg_value) in max9485_clkout_recalc_rate()
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/openbmc/u-boot/drivers/net/phy/
H A Dcortina.c214 fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) & in cs4340_upload_firmware()
216 phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value); in cs4340_upload_firmware()
226 int reg_value; in cs4340_phy_init() local
240 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS); in cs4340_phy_init()
241 if (reg_value & mseq_edc_bist_done) { in cs4340_phy_init()
242 if (0 == (reg_value & mseq_edc_bist_fail)) in cs4340_phy_init()
256 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS); in cs4340_phy_init()
257 if (reg_value) { in cs4340_phy_init()
289 int reg_value; in cs4223_phy_init() local
291 reg_value = phy_read(phydev, 0x00, CS4223_EEPROM_STATUS); in cs4223_phy_init()
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/openbmc/linux/drivers/staging/vt6655/
H A Dmac.c42 unsigned char reg_value; in vt6655_mac_reg_bits_on() local
44 reg_value = ioread8(iobase + reg_offset); in vt6655_mac_reg_bits_on()
45 iowrite8(reg_value | bit_mask, iobase + reg_offset); in vt6655_mac_reg_bits_on()
50 unsigned short reg_value; in vt6655_mac_word_reg_bits_on() local
52 reg_value = ioread16(iobase + reg_offset); in vt6655_mac_word_reg_bits_on()
53 iowrite16(reg_value | (bit_mask), iobase + reg_offset); in vt6655_mac_word_reg_bits_on()
58 unsigned char reg_value; in vt6655_mac_reg_bits_off() local
60 reg_value = ioread8(iobase + reg_offset); in vt6655_mac_reg_bits_off()
61 iowrite8(reg_value & ~(bit_mask), iobase + reg_offset); in vt6655_mac_reg_bits_off()
66 unsigned short reg_value; in vt6655_mac_word_reg_bits_off() local
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/openbmc/linux/drivers/media/dvb-frontends/
H A Dstv6111.c32 u16 reg_value; member
533 int table_size, u16 reg_value) in table_lookup() argument
542 if (reg_value <= table[0].reg_value) { in table_lookup()
544 } else if (reg_value >= table[imax].reg_value) { in table_lookup()
549 if ((table[imin].reg_value <= reg_value) && in table_lookup()
550 (reg_value <= table[i].reg_value)) in table_lookup()
555 reg_diff = table[imax].reg_value - table[imin].reg_value; in table_lookup()
558 gain += ((s32)(reg_value - table[imin].reg_value) * in table_lookup()
/openbmc/qemu/hw/timer/
H A Dimx_gpt.c259 uint32_t reg_value = 0; in imx_gpt_read() local
263 reg_value = s->cr; in imx_gpt_read()
267 reg_value = s->pr; in imx_gpt_read()
271 reg_value = s->sr; in imx_gpt_read()
275 reg_value = s->ir; in imx_gpt_read()
279 reg_value = s->ocr1; in imx_gpt_read()
283 reg_value = s->ocr2; in imx_gpt_read()
287 reg_value = s->ocr3; in imx_gpt_read()
293 reg_value = s->icr1; in imx_gpt_read()
299 reg_value = s->icr2; in imx_gpt_read()
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H A Dcadence_ttc.c140 if (is_between(cand, (uint64_t)s->reg_value, next_value)) { in cadence_timer_run()
148 event_interval = next_value - (int64_t)s->reg_value; in cadence_timer_run()
172 x = (int64_t)s->reg_value + ((s->reg_count & COUNTER_CTRL_DEC) ? -r : r); in cadence_timer_sync()
181 if (is_between(m, s->reg_value, x) || in cadence_timer_sync()
182 is_between(m + interval, s->reg_value, x) || in cadence_timer_sync()
183 is_between(m - interval, s->reg_value, x)) { in cadence_timer_sync()
194 s->reg_value = (uint32_t)(x % interval); in cadence_timer_sync()
229 return (uint16_t)(s->reg_value >> 16); in cadence_ttc_read_imp()
309 s->reg_value = 0; in cadence_ttc_write()
431 VMSTATE_UINT32(reg_value, CadenceTimerState),
H A Dimx_epit.c121 uint32_t reg_value = 0; in imx_epit_read() local
125 reg_value = s->cr; in imx_epit_read()
129 reg_value = s->sr; in imx_epit_read()
133 reg_value = s->lr; in imx_epit_read()
137 reg_value = s->cmp; in imx_epit_read()
141 reg_value = ptimer_get_count(s->timer_reload); in imx_epit_read()
150 DPRINTF("(%s) = 0x%08x\n", imx_epit_reg_name(offset >> 2), reg_value); in imx_epit_read()
152 return reg_value; in imx_epit_read()
/openbmc/linux/sound/soc/mediatek/mt8188/
H A Dmt8188-dai-pcm.c34 unsigned int reg_value; member
45 { .rate = 8000, .reg_value = 0, },
46 { .rate = 16000, .reg_value = 1, },
47 { .rate = 32000, .reg_value = 2, },
48 { .rate = 48000, .reg_value = 3, },
49 { .rate = 11025, .reg_value = 1, },
50 { .rate = 22050, .reg_value = 2, },
51 { .rate = 44100, .reg_value = 3, },
60 return mtk_dai_pcm_rates[i].reg_value; in mtk_dai_pcm_mode()
/openbmc/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-dai-pcm.c32 unsigned int reg_value; member
43 { .rate = 8000, .reg_value = 0, },
44 { .rate = 16000, .reg_value = 1, },
45 { .rate = 32000, .reg_value = 2, },
46 { .rate = 48000, .reg_value = 3, },
47 { .rate = 11025, .reg_value = 1, },
48 { .rate = 22050, .reg_value = 2, },
49 { .rate = 44100, .reg_value = 3, },
58 return mtk_dai_pcm_rates[i].reg_value; in mtk_dai_pcm_mode()
/openbmc/linux/drivers/hwtracing/coresight/
H A Dcoresight-cti-core.c344 u32 reg_value; in cti_channel_trig_op() local
375 reg_value = direction == CTI_TRIG_IN ? config->ctiinen[trigger_idx] : in cti_channel_trig_op()
378 reg_value |= chan_bitmask; in cti_channel_trig_op()
380 reg_value &= ~chan_bitmask; in cti_channel_trig_op()
384 config->ctiinen[trigger_idx] = reg_value; in cti_channel_trig_op()
386 config->ctiouten[trigger_idx] = reg_value; in cti_channel_trig_op()
390 cti_write_single_reg(drvdata, reg_offset, reg_value); in cti_channel_trig_op()
401 u32 reg_value; in cti_channel_gate_op() local
410 reg_value = config->ctigate; in cti_channel_gate_op()
413 reg_value |= chan_bitmask; in cti_channel_gate_op()
[all …]
/openbmc/linux/drivers/power/supply/
H A Dab8500_fg.c1844 u8 reg_value; in ab8500_fg_check_hw_failure_work() local
1855 &reg_value); in ab8500_fg_check_hw_failure_work()
1860 if ((reg_value & BATT_OVV) == BATT_OVV) { in ab8500_fg_check_hw_failure_work()
2583 u8 reg_value; in ab8505_powercut_flagtime_read() local
2588 AB8505_RTC_PCUT_FLAG_TIME_REG, &reg_value); in ab8505_powercut_flagtime_read()
2595 return sysfs_emit(buf, "%d\n", (reg_value & 0x7F)); in ab8505_powercut_flagtime_read()
2606 int reg_value; in ab8505_powercut_flagtime_write() local
2610 if (kstrtoint(buf, 10, &reg_value)) in ab8505_powercut_flagtime_write()
2613 if (reg_value > 0x7F) { in ab8505_powercut_flagtime_write()
2619 AB8505_RTC_PCUT_FLAG_TIME_REG, (u8)reg_value); in ab8505_powercut_flagtime_write()
[all …]
/openbmc/linux/drivers/phy/allwinner/
H A Dphy-sun9i-usb.c46 u32 bits, reg_value; in sun9i_usb_phy_passby() local
56 reg_value = readl(phy->pmu); in sun9i_usb_phy_passby()
59 reg_value |= bits; in sun9i_usb_phy_passby()
61 reg_value &= ~bits; in sun9i_usb_phy_passby()
63 writel(reg_value, phy->pmu); in sun9i_usb_phy_passby()
/openbmc/linux/drivers/ata/
H A Dahci_imx.c823 struct reg_value { struct
825 u32 reg_value; argument
830 const struct reg_value *values;
836 static const struct reg_value gpr13_tx_level[] = {
871 static const struct reg_value gpr13_tx_boost[] = {
890 static const struct reg_value gpr13_tx_atten[] = {
899 static const struct reg_value gpr13_rx_eq[] = {
942 u32 reg_value = 0; in imx_ahci_parse_props() local
950 reg_value |= prop->set_value; in imx_ahci_parse_props()
952 reg_value |= prop->def_value; in imx_ahci_parse_props()
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/openbmc/qemu/hw/acpi/
H A Derst.c176 uint64_t reg_value; member
802 s->reg_value = erst_wr_reg64(addr, s->reg_value, val, size); in erst_reg_write()
820 s->record_offset = s->reg_value; in erst_reg_write()
823 if ((uint8_t)s->reg_value == ERST_EXECUTE_OPERATION_MAGIC) { in erst_reg_write()
849 s->reg_value = s->busy_status; in erst_reg_write()
852 s->reg_value = s->command_status; in erst_reg_write()
856 &s->reg_value, false); in erst_reg_write()
859 s->record_identifier = s->reg_value; in erst_reg_write()
862 s->reg_value = le32_to_cpu(s->header->record_count); in erst_reg_write()
865 s->reg_value = (hwaddr)pci_get_bar_addr(PCI_DEVICE(s), 1); in erst_reg_write()
[all …]
/openbmc/linux/drivers/misc/
H A Dxilinx_sdfec.c264 u32 reg_value; in update_config_from_hw() local
268 reg_value = xsdfec_regread(xsdfec, XSDFEC_ORDER_ADDR); in update_config_from_hw()
269 xsdfec->config.order = reg_value; in update_config_from_hw()
279 reg_value = xsdfec_regread(xsdfec, XSDFEC_IMR_ADDR); in update_config_from_hw()
280 xsdfec->config.irq.enable_isr = (reg_value & XSDFEC_ISR_MASK) > 0; in update_config_from_hw()
282 reg_value = xsdfec_regread(xsdfec, XSDFEC_ECC_IMR_ADDR); in update_config_from_hw()
284 (reg_value & XSDFEC_ECC_ISR_MASK) > 0; in update_config_from_hw()
286 reg_value = xsdfec_regread(xsdfec, XSDFEC_AXIS_ENABLE_ADDR); in update_config_from_hw()
287 sdfec_started = (reg_value & XSDFEC_AXIS_IN_ENABLE_MASK) > 0; in update_config_from_hw()
438 u32 reg_value; in xsdfec_get_turbo() local
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