Home
last modified time | relevance | path

Searched refs:reg_val_low (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/edac/
H A Ddmc520_edac.c229 u32 reg_val_low, reg_val_high; in dmc520_get_dram_ecc_error_info() local
237 reg_val_low = dmc520_read_reg(pvt, reg_offset_low); in dmc520_get_dram_ecc_error_info()
240 valid = (FIELD_GET(REG_FIELD_ERR_INFO_LOW_VALID, reg_val_low) != 0) && in dmc520_get_dram_ecc_error_info()
244 info->col = FIELD_GET(REG_FIELD_ERR_INFO_LOW_COL, reg_val_low); in dmc520_get_dram_ecc_error_info()
245 info->row = FIELD_GET(REG_FIELD_ERR_INFO_LOW_ROW, reg_val_low); in dmc520_get_dram_ecc_error_info()
246 info->rank = FIELD_GET(REG_FIELD_ERR_INFO_LOW_RANK, reg_val_low); in dmc520_get_dram_ecc_error_info()
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1691 u32 reg_val_low, reg_val_high; in mv_ddr_rl_dqs_burst() local
1787 RD_FIFO_PTR_LOW_STAT_INDIR_ADDR, &reg_val_low); in mv_ddr_rl_dqs_burst()
1794 reg_val_low, reg_val_high)); in mv_ddr_rl_dqs_burst()
1799 if (reg_val_low == RD_FIFO_DQS_FALL_EDGE_POS_4 && in mv_ddr_rl_dqs_burst()
1807 } else if (reg_val_low == RD_FIFO_DQS_FALL_EDGE_POS_3 && in mv_ddr_rl_dqs_burst()
1810 } else if (reg_val_low == RD_FIFO_DQS_FALL_EDGE_POS_2 && in mv_ddr_rl_dqs_burst()
1813 } else if (reg_val_low == RD_FIFO_DQS_FALL_EDGE_POS_1 && in mv_ddr_rl_dqs_burst()
1816 } else if (reg_val_low == RD_FIFO_DQS_FALL_EDGE_POS_0 && in mv_ddr_rl_dqs_burst()
1824 if (reg_val_low == RD_FIFO_DQS_FALL_EDGE_POS_4 && in mv_ddr_rl_dqs_burst()
1847 if (reg_val_low != RD_FIFO_DQS_FALL_EDGE_POS_4 || in mv_ddr_rl_dqs_burst()