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Searched refs:regVPG5_VPG_MEM_PWR (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h12969 #define regVPG5_VPG_MEM_PWR … macro
H A Ddcn_3_1_5_offset.h12832 #define regVPG5_VPG_MEM_PWR … macro
H A Ddcn_3_1_4_offset.h12438 #define regVPG5_VPG_MEM_PWR … macro
H A Ddcn_3_2_1_offset.h12216 #define regVPG5_VPG_MEM_PWR … macro
H A Ddcn_3_2_0_offset.h12207 #define regVPG5_VPG_MEM_PWR … macro
H A Ddcn_3_1_6_offset.h13565 #define regVPG5_VPG_MEM_PWR … macro