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Searched refs:regVPG0_VPG_MEM_PWR (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h11287 #define regVPG0_VPG_MEM_PWR … macro
H A Ddcn_3_1_5_offset.h11032 #define regVPG0_VPG_MEM_PWR … macro
H A Ddcn_3_1_4_offset.h9122 #define regVPG0_VPG_MEM_PWR … macro
H A Ddcn_3_2_1_offset.h10448 #define regVPG0_VPG_MEM_PWR … macro
H A Ddcn_3_2_0_offset.h10449 #define regVPG0_VPG_MEM_PWR … macro
H A Ddcn_3_1_6_offset.h11511 #define regVPG0_VPG_MEM_PWR … macro