1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _vcn_2_6_0_OFFSET_HEADER 24 #define _vcn_2_6_0_OFFSET_HEADER 25 26 27 28 // addressBlock: uvd0_ecpudec 29 // base address: 0x1fd00 30 #define regUVD_VCPU_CACHE_OFFSET0 0x0140 31 #define regUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1 32 #define regUVD_VCPU_CACHE_SIZE0 0x0141 33 #define regUVD_VCPU_CACHE_SIZE0_BASE_IDX 1 34 #define regUVD_VCPU_CACHE_OFFSET1 0x0142 35 #define regUVD_VCPU_CACHE_OFFSET1_BASE_IDX 1 36 #define regUVD_VCPU_CACHE_SIZE1 0x0143 37 #define regUVD_VCPU_CACHE_SIZE1_BASE_IDX 1 38 #define regUVD_VCPU_CACHE_OFFSET2 0x0144 39 #define regUVD_VCPU_CACHE_OFFSET2_BASE_IDX 1 40 #define regUVD_VCPU_CACHE_SIZE2 0x0145 41 #define regUVD_VCPU_CACHE_SIZE2_BASE_IDX 1 42 #define regUVD_VCPU_CACHE_OFFSET3 0x0146 43 #define regUVD_VCPU_CACHE_OFFSET3_BASE_IDX 1 44 #define regUVD_VCPU_CACHE_SIZE3 0x0147 45 #define regUVD_VCPU_CACHE_SIZE3_BASE_IDX 1 46 #define regUVD_VCPU_CACHE_OFFSET4 0x0148 47 #define regUVD_VCPU_CACHE_OFFSET4_BASE_IDX 1 48 #define regUVD_VCPU_CACHE_SIZE4 0x0149 49 #define regUVD_VCPU_CACHE_SIZE4_BASE_IDX 1 50 #define regUVD_VCPU_CACHE_OFFSET5 0x014a 51 #define regUVD_VCPU_CACHE_OFFSET5_BASE_IDX 1 52 #define regUVD_VCPU_CACHE_SIZE5 0x014b 53 #define regUVD_VCPU_CACHE_SIZE5_BASE_IDX 1 54 #define regUVD_VCPU_CACHE_OFFSET6 0x014c 55 #define regUVD_VCPU_CACHE_OFFSET6_BASE_IDX 1 56 #define regUVD_VCPU_CACHE_SIZE6 0x014d 57 #define regUVD_VCPU_CACHE_SIZE6_BASE_IDX 1 58 #define regUVD_VCPU_CACHE_OFFSET7 0x014e 59 #define regUVD_VCPU_CACHE_OFFSET7_BASE_IDX 1 60 #define regUVD_VCPU_CACHE_SIZE7 0x014f 61 #define regUVD_VCPU_CACHE_SIZE7_BASE_IDX 1 62 #define regUVD_VCPU_CACHE_OFFSET8 0x0150 63 #define regUVD_VCPU_CACHE_OFFSET8_BASE_IDX 1 64 #define regUVD_VCPU_CACHE_SIZE8 0x0151 65 #define regUVD_VCPU_CACHE_SIZE8_BASE_IDX 1 66 #define regUVD_VCPU_NONCACHE_OFFSET0 0x0152 67 #define regUVD_VCPU_NONCACHE_OFFSET0_BASE_IDX 1 68 #define regUVD_VCPU_NONCACHE_SIZE0 0x0153 69 #define regUVD_VCPU_NONCACHE_SIZE0_BASE_IDX 1 70 #define regUVD_VCPU_NONCACHE_OFFSET1 0x0154 71 #define regUVD_VCPU_NONCACHE_OFFSET1_BASE_IDX 1 72 #define regUVD_VCPU_NONCACHE_SIZE1 0x0155 73 #define regUVD_VCPU_NONCACHE_SIZE1_BASE_IDX 1 74 #define regUVD_VCPU_CNTL 0x0156 75 #define regUVD_VCPU_CNTL_BASE_IDX 1 76 #define regUVD_VCPU_PRID 0x0157 77 #define regUVD_VCPU_PRID_BASE_IDX 1 78 #define regUVD_VCPU_TRCE 0x0158 79 #define regUVD_VCPU_TRCE_BASE_IDX 1 80 #define regUVD_VCPU_TRCE_RD 0x0159 81 #define regUVD_VCPU_TRCE_RD_BASE_IDX 1 82 #define regUVD_VCPU_IND_INDEX 0x015b 83 #define regUVD_VCPU_IND_INDEX_BASE_IDX 1 84 #define regUVD_VCPU_IND_DATA 0x015c 85 #define regUVD_VCPU_IND_DATA_BASE_IDX 1 86 87 88 // addressBlock: uvd0_jpegnpdec 89 // base address: 0x1e200 90 #define regUVD_JPEG_CNTL 0x0080 91 #define regUVD_JPEG_CNTL_BASE_IDX 0 92 #define regUVD_JPEG_RB_BASE 0x0081 93 #define regUVD_JPEG_RB_BASE_BASE_IDX 0 94 #define regUVD_JPEG_RB_WPTR 0x0082 95 #define regUVD_JPEG_RB_WPTR_BASE_IDX 0 96 #define regUVD_JPEG_RB_RPTR 0x0083 97 #define regUVD_JPEG_RB_RPTR_BASE_IDX 0 98 #define regUVD_JPEG_RB_SIZE 0x0084 99 #define regUVD_JPEG_RB_SIZE_BASE_IDX 0 100 #define regUVD_JPEG_DEC_CNT 0x0085 101 #define regUVD_JPEG_DEC_CNT_BASE_IDX 0 102 #define regUVD_JPEG_SPS_INFO 0x0086 103 #define regUVD_JPEG_SPS_INFO_BASE_IDX 0 104 #define regUVD_JPEG_SPS1_INFO 0x0087 105 #define regUVD_JPEG_SPS1_INFO_BASE_IDX 0 106 #define regUVD_JPEG_RE_TIMER 0x0088 107 #define regUVD_JPEG_RE_TIMER_BASE_IDX 0 108 #define regUVD_JPEG_DEC_SCRATCH0 0x0089 109 #define regUVD_JPEG_DEC_SCRATCH0_BASE_IDX 0 110 #define regUVD_JPEG_INT_EN 0x008a 111 #define regUVD_JPEG_INT_EN_BASE_IDX 0 112 #define regUVD_JPEG_INT_STAT 0x008b 113 #define regUVD_JPEG_INT_STAT_BASE_IDX 0 114 #define regUVD_JPEG_TIER_CNTL0 0x008d 115 #define regUVD_JPEG_TIER_CNTL0_BASE_IDX 0 116 #define regUVD_JPEG_TIER_CNTL1 0x008e 117 #define regUVD_JPEG_TIER_CNTL1_BASE_IDX 0 118 #define regUVD_JPEG_TIER_CNTL2 0x008f 119 #define regUVD_JPEG_TIER_CNTL2_BASE_IDX 0 120 #define regUVD_JPEG_TIER_STATUS 0x0090 121 #define regUVD_JPEG_TIER_STATUS_BASE_IDX 0 122 #define regUVD_JPEG_OUTBUF_CNTL 0x009c 123 #define regUVD_JPEG_OUTBUF_CNTL_BASE_IDX 0 124 #define regUVD_JPEG_OUTBUF_WPTR 0x009d 125 #define regUVD_JPEG_OUTBUF_WPTR_BASE_IDX 0 126 #define regUVD_JPEG_OUTBUF_RPTR 0x009e 127 #define regUVD_JPEG_OUTBUF_RPTR_BASE_IDX 0 128 #define regUVD_JPEG_PITCH 0x009f 129 #define regUVD_JPEG_PITCH_BASE_IDX 0 130 #define regUVD_JPEG_UV_PITCH 0x00a0 131 #define regUVD_JPEG_UV_PITCH_BASE_IDX 0 132 #define regJPEG_DEC_Y_GFX8_TILING_SURFACE 0x00a1 133 #define regJPEG_DEC_Y_GFX8_TILING_SURFACE_BASE_IDX 0 134 #define regJPEG_DEC_UV_GFX8_TILING_SURFACE 0x00a2 135 #define regJPEG_DEC_UV_GFX8_TILING_SURFACE_BASE_IDX 0 136 #define regJPEG_DEC_GFX8_ADDR_CONFIG 0x00a3 137 #define regJPEG_DEC_GFX8_ADDR_CONFIG_BASE_IDX 0 138 #define regJPEG_DEC_Y_GFX10_TILING_SURFACE 0x00a4 139 #define regJPEG_DEC_Y_GFX10_TILING_SURFACE_BASE_IDX 0 140 #define regJPEG_DEC_UV_GFX10_TILING_SURFACE 0x00a5 141 #define regJPEG_DEC_UV_GFX10_TILING_SURFACE_BASE_IDX 0 142 #define regJPEG_DEC_GFX10_ADDR_CONFIG 0x00a6 143 #define regJPEG_DEC_GFX10_ADDR_CONFIG_BASE_IDX 0 144 #define regJPEG_DEC_ADDR_MODE 0x00a7 145 #define regJPEG_DEC_ADDR_MODE_BASE_IDX 0 146 #define regUVD_JPEG_OUTPUT_XY 0x00a8 147 #define regUVD_JPEG_OUTPUT_XY_BASE_IDX 0 148 #define regUVD_JPEG_GPCOM_CMD 0x00a9 149 #define regUVD_JPEG_GPCOM_CMD_BASE_IDX 0 150 #define regUVD_JPEG_GPCOM_DATA0 0x00aa 151 #define regUVD_JPEG_GPCOM_DATA0_BASE_IDX 0 152 #define regUVD_JPEG_GPCOM_DATA1 0x00ab 153 #define regUVD_JPEG_GPCOM_DATA1_BASE_IDX 0 154 #define regUVD_JPEG_INDEX 0x00ac 155 #define regUVD_JPEG_INDEX_BASE_IDX 0 156 #define regUVD_JPEG_DATA 0x00ad 157 #define regUVD_JPEG_DATA_BASE_IDX 0 158 #define regUVD_JPEG_SCRATCH1 0x00ae 159 #define regUVD_JPEG_SCRATCH1_BASE_IDX 0 160 #define regUVD_JPEG_DEC_SOFT_RST 0x00af 161 #define regUVD_JPEG_DEC_SOFT_RST_BASE_IDX 0 162 163 164 // addressBlock: uvd0_lmi_adpdec 165 // base address: 0x20870 166 #define regUVD_LMI_RE_64BIT_BAR_LOW 0x041c 167 #define regUVD_LMI_RE_64BIT_BAR_LOW_BASE_IDX 1 168 #define regUVD_LMI_RE_64BIT_BAR_HIGH 0x041d 169 #define regUVD_LMI_RE_64BIT_BAR_HIGH_BASE_IDX 1 170 #define regUVD_LMI_IT_64BIT_BAR_LOW 0x041e 171 #define regUVD_LMI_IT_64BIT_BAR_LOW_BASE_IDX 1 172 #define regUVD_LMI_IT_64BIT_BAR_HIGH 0x041f 173 #define regUVD_LMI_IT_64BIT_BAR_HIGH_BASE_IDX 1 174 #define regUVD_LMI_MP_64BIT_BAR_LOW 0x0420 175 #define regUVD_LMI_MP_64BIT_BAR_LOW_BASE_IDX 1 176 #define regUVD_LMI_MP_64BIT_BAR_HIGH 0x0421 177 #define regUVD_LMI_MP_64BIT_BAR_HIGH_BASE_IDX 1 178 #define regUVD_LMI_CM_64BIT_BAR_LOW 0x0422 179 #define regUVD_LMI_CM_64BIT_BAR_LOW_BASE_IDX 1 180 #define regUVD_LMI_CM_64BIT_BAR_HIGH 0x0423 181 #define regUVD_LMI_CM_64BIT_BAR_HIGH_BASE_IDX 1 182 #define regUVD_LMI_DB_64BIT_BAR_LOW 0x0424 183 #define regUVD_LMI_DB_64BIT_BAR_LOW_BASE_IDX 1 184 #define regUVD_LMI_DB_64BIT_BAR_HIGH 0x0425 185 #define regUVD_LMI_DB_64BIT_BAR_HIGH_BASE_IDX 1 186 #define regUVD_LMI_DBW_64BIT_BAR_LOW 0x0426 187 #define regUVD_LMI_DBW_64BIT_BAR_LOW_BASE_IDX 1 188 #define regUVD_LMI_DBW_64BIT_BAR_HIGH 0x0427 189 #define regUVD_LMI_DBW_64BIT_BAR_HIGH_BASE_IDX 1 190 #define regUVD_LMI_IDCT_64BIT_BAR_LOW 0x0428 191 #define regUVD_LMI_IDCT_64BIT_BAR_LOW_BASE_IDX 1 192 #define regUVD_LMI_IDCT_64BIT_BAR_HIGH 0x0429 193 #define regUVD_LMI_IDCT_64BIT_BAR_HIGH_BASE_IDX 1 194 #define regUVD_LMI_MPRD_S0_64BIT_BAR_LOW 0x042a 195 #define regUVD_LMI_MPRD_S0_64BIT_BAR_LOW_BASE_IDX 1 196 #define regUVD_LMI_MPRD_S0_64BIT_BAR_HIGH 0x042b 197 #define regUVD_LMI_MPRD_S0_64BIT_BAR_HIGH_BASE_IDX 1 198 #define regUVD_LMI_MPRD_S1_64BIT_BAR_LOW 0x042c 199 #define regUVD_LMI_MPRD_S1_64BIT_BAR_LOW_BASE_IDX 1 200 #define regUVD_LMI_MPRD_S1_64BIT_BAR_HIGH 0x042d 201 #define regUVD_LMI_MPRD_S1_64BIT_BAR_HIGH_BASE_IDX 1 202 #define regUVD_LMI_MPRD_DBW_64BIT_BAR_LOW 0x042e 203 #define regUVD_LMI_MPRD_DBW_64BIT_BAR_LOW_BASE_IDX 1 204 #define regUVD_LMI_MPRD_DBW_64BIT_BAR_HIGH 0x042f 205 #define regUVD_LMI_MPRD_DBW_64BIT_BAR_HIGH_BASE_IDX 1 206 #define regUVD_LMI_MPC_64BIT_BAR_LOW 0x0430 207 #define regUVD_LMI_MPC_64BIT_BAR_LOW_BASE_IDX 1 208 #define regUVD_LMI_MPC_64BIT_BAR_HIGH 0x0431 209 #define regUVD_LMI_MPC_64BIT_BAR_HIGH_BASE_IDX 1 210 #define regUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x0432 211 #define regUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX 1 212 #define regUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x0433 213 #define regUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 214 #define regUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x0434 215 #define regUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX 1 216 #define regUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x0435 217 #define regUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 218 #define regUVD_LMI_LBSI_64BIT_BAR_LOW 0x0436 219 #define regUVD_LMI_LBSI_64BIT_BAR_LOW_BASE_IDX 1 220 #define regUVD_LMI_LBSI_64BIT_BAR_HIGH 0x0437 221 #define regUVD_LMI_LBSI_64BIT_BAR_HIGH_BASE_IDX 1 222 #define regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW 0x0438 223 #define regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW_BASE_IDX 1 224 #define regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 0x0439 225 #define regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH_BASE_IDX 1 226 #define regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW 0x043a 227 #define regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW_BASE_IDX 1 228 #define regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 0x043b 229 #define regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH_BASE_IDX 1 230 #define regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x043c 231 #define regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 232 #define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x043d 233 #define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 234 #define regUVD_LMI_CENC_64BIT_BAR_LOW 0x043e 235 #define regUVD_LMI_CENC_64BIT_BAR_LOW_BASE_IDX 1 236 #define regUVD_LMI_CENC_64BIT_BAR_HIGH 0x043f 237 #define regUVD_LMI_CENC_64BIT_BAR_HIGH_BASE_IDX 1 238 #define regUVD_LMI_SRE_64BIT_BAR_LOW 0x0440 239 #define regUVD_LMI_SRE_64BIT_BAR_LOW_BASE_IDX 1 240 #define regUVD_LMI_SRE_64BIT_BAR_HIGH 0x0441 241 #define regUVD_LMI_SRE_64BIT_BAR_HIGH_BASE_IDX 1 242 #define regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW 0x0442 243 #define regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW_BASE_IDX 1 244 #define regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH 0x0443 245 #define regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH_BASE_IDX 1 246 #define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW 0x0444 247 #define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW_BASE_IDX 1 248 #define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH 0x0445 249 #define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 250 #define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW 0x0446 251 #define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW_BASE_IDX 1 252 #define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH 0x0447 253 #define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1 254 #define regUVD_LMI_MIF_REF_64BIT_BAR_LOW 0x0448 255 #define regUVD_LMI_MIF_REF_64BIT_BAR_LOW_BASE_IDX 1 256 #define regUVD_LMI_MIF_REF_64BIT_BAR_HIGH 0x0449 257 #define regUVD_LMI_MIF_REF_64BIT_BAR_HIGH_BASE_IDX 1 258 #define regUVD_LMI_MIF_DBW_64BIT_BAR_LOW 0x044a 259 #define regUVD_LMI_MIF_DBW_64BIT_BAR_LOW_BASE_IDX 1 260 #define regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH 0x044b 261 #define regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH_BASE_IDX 1 262 #define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW 0x044c 263 #define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW_BASE_IDX 1 264 #define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH 0x044d 265 #define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH_BASE_IDX 1 266 #define regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW 0x044e 267 #define regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW_BASE_IDX 1 268 #define regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH 0x044f 269 #define regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH_BASE_IDX 1 270 #define regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW 0x0450 271 #define regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW_BASE_IDX 1 272 #define regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH 0x0451 273 #define regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH_BASE_IDX 1 274 #define regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW 0x0452 275 #define regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW_BASE_IDX 1 276 #define regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH 0x0453 277 #define regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH_BASE_IDX 1 278 #define regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW 0x0454 279 #define regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW_BASE_IDX 1 280 #define regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH 0x0455 281 #define regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH_BASE_IDX 1 282 #define regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW 0x0456 283 #define regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW_BASE_IDX 1 284 #define regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH 0x0457 285 #define regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH_BASE_IDX 1 286 #define regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW 0x0458 287 #define regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW_BASE_IDX 1 288 #define regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH 0x0459 289 #define regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH_BASE_IDX 1 290 #define regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW 0x045a 291 #define regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW_BASE_IDX 1 292 #define regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH 0x045b 293 #define regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH_BASE_IDX 1 294 #define regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW 0x045c 295 #define regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW_BASE_IDX 1 296 #define regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH 0x045d 297 #define regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH_BASE_IDX 1 298 #define regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW 0x045e 299 #define regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW_BASE_IDX 1 300 #define regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH 0x045f 301 #define regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH_BASE_IDX 1 302 #define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x0468 303 #define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX 1 304 #define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x0469 305 #define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX 1 306 #define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 0x046a 307 #define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW_BASE_IDX 1 308 #define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 0x046b 309 #define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH_BASE_IDX 1 310 #define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 0x046c 311 #define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX 1 312 #define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x046d 313 #define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX 1 314 #define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 0x046e 315 #define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW_BASE_IDX 1 316 #define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 0x046f 317 #define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH_BASE_IDX 1 318 #define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 0x0470 319 #define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW_BASE_IDX 1 320 #define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 0x0471 321 #define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH_BASE_IDX 1 322 #define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 0x0472 323 #define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW_BASE_IDX 1 324 #define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 0x0473 325 #define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH_BASE_IDX 1 326 #define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 0x0474 327 #define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW_BASE_IDX 1 328 #define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 0x0475 329 #define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH_BASE_IDX 1 330 #define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 0x0476 331 #define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW_BASE_IDX 1 332 #define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 0x0477 333 #define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH_BASE_IDX 1 334 #define regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW 0x0478 335 #define regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW_BASE_IDX 1 336 #define regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH 0x0479 337 #define regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH_BASE_IDX 1 338 #define regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW 0x047a 339 #define regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW_BASE_IDX 1 340 #define regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH 0x047b 341 #define regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH_BASE_IDX 1 342 #define regUVD_LMI_SPH_64BIT_BAR_HIGH 0x047c 343 #define regUVD_LMI_SPH_64BIT_BAR_HIGH_BASE_IDX 1 344 #define regUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 0x047d 345 #define regUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW_BASE_IDX 1 346 #define regUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 0x047e 347 #define regUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH_BASE_IDX 1 348 #define regUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 0x047f 349 #define regUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW_BASE_IDX 1 350 #define regUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 0x0480 351 #define regUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH_BASE_IDX 1 352 #define regUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 0x0481 353 #define regUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW_BASE_IDX 1 354 #define regUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 0x0482 355 #define regUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH_BASE_IDX 1 356 #define regUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 0x0483 357 #define regUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW_BASE_IDX 1 358 #define regUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 0x0484 359 #define regUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH_BASE_IDX 1 360 #define regUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 0x0485 361 #define regUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW_BASE_IDX 1 362 #define regUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 0x0486 363 #define regUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH_BASE_IDX 1 364 #define regUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 0x0487 365 #define regUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW_BASE_IDX 1 366 #define regUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 0x0488 367 #define regUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH_BASE_IDX 1 368 #define regUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 0x0489 369 #define regUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW_BASE_IDX 1 370 #define regUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 0x048a 371 #define regUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH_BASE_IDX 1 372 #define regUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 0x048b 373 #define regUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW_BASE_IDX 1 374 #define regUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 0x048c 375 #define regUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH_BASE_IDX 1 376 #define regUVD_LMI_MMSCH_NC_VMID 0x048d 377 #define regUVD_LMI_MMSCH_NC_VMID_BASE_IDX 1 378 #define regUVD_LMI_MMSCH_CTRL 0x048e 379 #define regUVD_LMI_MMSCH_CTRL_BASE_IDX 1 380 #define regUVD_MMSCH_LMI_STATUS 0x048f 381 #define regUVD_MMSCH_LMI_STATUS_BASE_IDX 1 382 #define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW 0x0490 383 #define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW_BASE_IDX 1 384 #define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH 0x0491 385 #define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 386 #define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW 0x0492 387 #define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW_BASE_IDX 1 388 #define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH 0x0493 389 #define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1 390 #define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW 0x0494 391 #define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW_BASE_IDX 1 392 #define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH 0x0495 393 #define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 394 #define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW 0x0496 395 #define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW_BASE_IDX 1 396 #define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH 0x0497 397 #define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1 398 #define regUVD_ADP_ATOMIC_CONFIG 0x0499 399 #define regUVD_ADP_ATOMIC_CONFIG_BASE_IDX 1 400 #define regUVD_LMI_ARB_CTRL2 0x049a 401 #define regUVD_LMI_ARB_CTRL2_BASE_IDX 1 402 #define regUVD_LMI_VCPU_CACHE_VMIDS_MULTI 0x049f 403 #define regUVD_LMI_VCPU_CACHE_VMIDS_MULTI_BASE_IDX 1 404 #define regUVD_LMI_VCPU_NC_VMIDS_MULTI 0x04a0 405 #define regUVD_LMI_VCPU_NC_VMIDS_MULTI_BASE_IDX 1 406 #define regUVD_LMI_LAT_CTRL 0x04a1 407 #define regUVD_LMI_LAT_CTRL_BASE_IDX 1 408 #define regUVD_LMI_LAT_CNTR 0x04a2 409 #define regUVD_LMI_LAT_CNTR_BASE_IDX 1 410 #define regUVD_LMI_AVG_LAT_CNTR 0x04a3 411 #define regUVD_LMI_AVG_LAT_CNTR_BASE_IDX 1 412 #define regUVD_LMI_SPH 0x04a4 413 #define regUVD_LMI_SPH_BASE_IDX 1 414 #define regUVD_LMI_VCPU_CACHE_VMID 0x04a5 415 #define regUVD_LMI_VCPU_CACHE_VMID_BASE_IDX 1 416 #define regUVD_LMI_CTRL2 0x04a6 417 #define regUVD_LMI_CTRL2_BASE_IDX 1 418 #define regUVD_LMI_URGENT_CTRL 0x04a7 419 #define regUVD_LMI_URGENT_CTRL_BASE_IDX 1 420 #define regUVD_LMI_CTRL 0x04a8 421 #define regUVD_LMI_CTRL_BASE_IDX 1 422 #define regUVD_LMI_STATUS 0x04a9 423 #define regUVD_LMI_STATUS_BASE_IDX 1 424 #define regUVD_LMI_PERFMON_CTRL 0x04ac 425 #define regUVD_LMI_PERFMON_CTRL_BASE_IDX 1 426 #define regUVD_LMI_PERFMON_COUNT_LO 0x04ad 427 #define regUVD_LMI_PERFMON_COUNT_LO_BASE_IDX 1 428 #define regUVD_LMI_PERFMON_COUNT_HI 0x04ae 429 #define regUVD_LMI_PERFMON_COUNT_HI_BASE_IDX 1 430 #define regUVD_LMI_ADP_SWAP_CNTL 0x04af 431 #define regUVD_LMI_ADP_SWAP_CNTL_BASE_IDX 1 432 #define regUVD_LMI_RBC_RB_VMID 0x04b0 433 #define regUVD_LMI_RBC_RB_VMID_BASE_IDX 1 434 #define regUVD_LMI_RBC_IB_VMID 0x04b1 435 #define regUVD_LMI_RBC_IB_VMID_BASE_IDX 1 436 #define regUVD_LMI_MC_CREDITS 0x04b2 437 #define regUVD_LMI_MC_CREDITS_BASE_IDX 1 438 #define regUVD_LMI_ADP_IND_INDEX 0x04b6 439 #define regUVD_LMI_ADP_IND_INDEX_BASE_IDX 1 440 #define regUVD_LMI_ADP_IND_DATA 0x04b7 441 #define regUVD_LMI_ADP_IND_DATA_BASE_IDX 1 442 #define regVCN_RAS_CNTL 0x04b9 443 #define regVCN_RAS_CNTL_BASE_IDX 1 444 445 446 // addressBlock: uvd0_mmsch_dec 447 // base address: 0x1e000 448 #define regMMSCH_UCODE_ADDR 0x0000 449 #define regMMSCH_UCODE_ADDR_BASE_IDX 0 450 #define regMMSCH_UCODE_DATA 0x0001 451 #define regMMSCH_UCODE_DATA_BASE_IDX 0 452 #define regMMSCH_SRAM_ADDR 0x0002 453 #define regMMSCH_SRAM_ADDR_BASE_IDX 0 454 #define regMMSCH_SRAM_DATA 0x0003 455 #define regMMSCH_SRAM_DATA_BASE_IDX 0 456 #define regMMSCH_VF_SRAM_OFFSET 0x0004 457 #define regMMSCH_VF_SRAM_OFFSET_BASE_IDX 0 458 #define regMMSCH_DB_SRAM_OFFSET 0x0005 459 #define regMMSCH_DB_SRAM_OFFSET_BASE_IDX 0 460 #define regMMSCH_CTX_SRAM_OFFSET 0x0006 461 #define regMMSCH_CTX_SRAM_OFFSET_BASE_IDX 0 462 #define regMMSCH_INTR 0x0008 463 #define regMMSCH_INTR_BASE_IDX 0 464 #define regMMSCH_INTR_ACK 0x0009 465 #define regMMSCH_INTR_ACK_BASE_IDX 0 466 #define regMMSCH_INTR_STATUS 0x000a 467 #define regMMSCH_INTR_STATUS_BASE_IDX 0 468 #define regMMSCH_VF_VMID 0x000b 469 #define regMMSCH_VF_VMID_BASE_IDX 0 470 #define regMMSCH_VF_CTX_ADDR_LO 0x000c 471 #define regMMSCH_VF_CTX_ADDR_LO_BASE_IDX 0 472 #define regMMSCH_VF_CTX_ADDR_HI 0x000d 473 #define regMMSCH_VF_CTX_ADDR_HI_BASE_IDX 0 474 #define regMMSCH_VF_CTX_SIZE 0x000e 475 #define regMMSCH_VF_CTX_SIZE_BASE_IDX 0 476 #define regMMSCH_VF_GPCOM_ADDR_LO 0x000f 477 #define regMMSCH_VF_GPCOM_ADDR_LO_BASE_IDX 0 478 #define regMMSCH_VF_GPCOM_ADDR_HI 0x0010 479 #define regMMSCH_VF_GPCOM_ADDR_HI_BASE_IDX 0 480 #define regMMSCH_VF_GPCOM_SIZE 0x0011 481 #define regMMSCH_VF_GPCOM_SIZE_BASE_IDX 0 482 #define regMMSCH_VF_MAILBOX_HOST 0x0012 483 #define regMMSCH_VF_MAILBOX_HOST_BASE_IDX 0 484 #define regMMSCH_VF_MAILBOX_RESP 0x0013 485 #define regMMSCH_VF_MAILBOX_RESP_BASE_IDX 0 486 #define regMMSCH_VF_MAILBOX_0 0x0014 487 #define regMMSCH_VF_MAILBOX_0_BASE_IDX 0 488 #define regMMSCH_VF_MAILBOX_0_RESP 0x0015 489 #define regMMSCH_VF_MAILBOX_0_RESP_BASE_IDX 0 490 #define regMMSCH_VF_MAILBOX_1 0x0016 491 #define regMMSCH_VF_MAILBOX_1_BASE_IDX 0 492 #define regMMSCH_VF_MAILBOX_1_RESP 0x0017 493 #define regMMSCH_VF_MAILBOX_1_RESP_BASE_IDX 0 494 #define regMMSCH_CNTL 0x001c 495 #define regMMSCH_CNTL_BASE_IDX 0 496 #define regMMSCH_NONCACHE_OFFSET0 0x001d 497 #define regMMSCH_NONCACHE_OFFSET0_BASE_IDX 0 498 #define regMMSCH_NONCACHE_SIZE0 0x001e 499 #define regMMSCH_NONCACHE_SIZE0_BASE_IDX 0 500 #define regMMSCH_NONCACHE_OFFSET1 0x001f 501 #define regMMSCH_NONCACHE_OFFSET1_BASE_IDX 0 502 #define regMMSCH_NONCACHE_SIZE1 0x0020 503 #define regMMSCH_NONCACHE_SIZE1_BASE_IDX 0 504 #define regMMSCH_PROC_STATE1 0x0026 505 #define regMMSCH_PROC_STATE1_BASE_IDX 0 506 #define regMMSCH_LAST_MC_ADDR 0x0027 507 #define regMMSCH_LAST_MC_ADDR_BASE_IDX 0 508 #define regMMSCH_LAST_MEM_ACCESS_HI 0x0028 509 #define regMMSCH_LAST_MEM_ACCESS_HI_BASE_IDX 0 510 #define regMMSCH_LAST_MEM_ACCESS_LO 0x0029 511 #define regMMSCH_LAST_MEM_ACCESS_LO_BASE_IDX 0 512 #define regMMSCH_SCRATCH_0 0x002b 513 #define regMMSCH_SCRATCH_0_BASE_IDX 0 514 #define regMMSCH_SCRATCH_1 0x002c 515 #define regMMSCH_SCRATCH_1_BASE_IDX 0 516 #define regMMSCH_GPUIOV_SCH_BLOCK_0 0x002d 517 #define regMMSCH_GPUIOV_SCH_BLOCK_0_BASE_IDX 0 518 #define regMMSCH_GPUIOV_CMD_CONTROL_0 0x002e 519 #define regMMSCH_GPUIOV_CMD_CONTROL_0_BASE_IDX 0 520 #define regMMSCH_GPUIOV_CMD_STATUS_0 0x002f 521 #define regMMSCH_GPUIOV_CMD_STATUS_0_BASE_IDX 0 522 #define regMMSCH_GPUIOV_VM_BUSY_STATUS_0 0x0030 523 #define regMMSCH_GPUIOV_VM_BUSY_STATUS_0_BASE_IDX 0 524 #define regMMSCH_GPUIOV_ACTIVE_FCNS_0 0x0031 525 #define regMMSCH_GPUIOV_ACTIVE_FCNS_0_BASE_IDX 0 526 #define regMMSCH_GPUIOV_ACTIVE_FCN_ID_0 0x0032 527 #define regMMSCH_GPUIOV_ACTIVE_FCN_ID_0_BASE_IDX 0 528 #define regMMSCH_GPUIOV_DW6_0 0x0033 529 #define regMMSCH_GPUIOV_DW6_0_BASE_IDX 0 530 #define regMMSCH_GPUIOV_DW7_0 0x0034 531 #define regMMSCH_GPUIOV_DW7_0_BASE_IDX 0 532 #define regMMSCH_GPUIOV_DW8_0 0x0035 533 #define regMMSCH_GPUIOV_DW8_0_BASE_IDX 0 534 #define regMMSCH_GPUIOV_SCH_BLOCK_1 0x0036 535 #define regMMSCH_GPUIOV_SCH_BLOCK_1_BASE_IDX 0 536 #define regMMSCH_GPUIOV_CMD_CONTROL_1 0x0037 537 #define regMMSCH_GPUIOV_CMD_CONTROL_1_BASE_IDX 0 538 #define regMMSCH_GPUIOV_CMD_STATUS_1 0x0038 539 #define regMMSCH_GPUIOV_CMD_STATUS_1_BASE_IDX 0 540 #define regMMSCH_GPUIOV_VM_BUSY_STATUS_1 0x0039 541 #define regMMSCH_GPUIOV_VM_BUSY_STATUS_1_BASE_IDX 0 542 #define regMMSCH_GPUIOV_ACTIVE_FCNS_1 0x003a 543 #define regMMSCH_GPUIOV_ACTIVE_FCNS_1_BASE_IDX 0 544 #define regMMSCH_GPUIOV_ACTIVE_FCN_ID_1 0x003b 545 #define regMMSCH_GPUIOV_ACTIVE_FCN_ID_1_BASE_IDX 0 546 #define regMMSCH_GPUIOV_DW6_1 0x003c 547 #define regMMSCH_GPUIOV_DW6_1_BASE_IDX 0 548 #define regMMSCH_GPUIOV_DW7_1 0x003d 549 #define regMMSCH_GPUIOV_DW7_1_BASE_IDX 0 550 #define regMMSCH_GPUIOV_DW8_1 0x003e 551 #define regMMSCH_GPUIOV_DW8_1_BASE_IDX 0 552 #define regMMSCH_GPUIOV_CNTXT 0x003f 553 #define regMMSCH_GPUIOV_CNTXT_BASE_IDX 0 554 #define regMMSCH_SCRATCH_2 0x0040 555 #define regMMSCH_SCRATCH_2_BASE_IDX 0 556 #define regMMSCH_SCRATCH_3 0x0041 557 #define regMMSCH_SCRATCH_3_BASE_IDX 0 558 #define regMMSCH_SCRATCH_4 0x0042 559 #define regMMSCH_SCRATCH_4_BASE_IDX 0 560 #define regMMSCH_SCRATCH_5 0x0043 561 #define regMMSCH_SCRATCH_5_BASE_IDX 0 562 #define regMMSCH_SCRATCH_6 0x0044 563 #define regMMSCH_SCRATCH_6_BASE_IDX 0 564 #define regMMSCH_SCRATCH_7 0x0045 565 #define regMMSCH_SCRATCH_7_BASE_IDX 0 566 #define regMMSCH_VFID_FIFO_HEAD_0 0x0046 567 #define regMMSCH_VFID_FIFO_HEAD_0_BASE_IDX 0 568 #define regMMSCH_VFID_FIFO_TAIL_0 0x0047 569 #define regMMSCH_VFID_FIFO_TAIL_0_BASE_IDX 0 570 #define regMMSCH_VFID_FIFO_HEAD_1 0x0048 571 #define regMMSCH_VFID_FIFO_HEAD_1_BASE_IDX 0 572 #define regMMSCH_VFID_FIFO_TAIL_1 0x0049 573 #define regMMSCH_VFID_FIFO_TAIL_1_BASE_IDX 0 574 #define regMMSCH_NACK_STATUS 0x004a 575 #define regMMSCH_NACK_STATUS_BASE_IDX 0 576 #define regMMSCH_VF_MAILBOX0_DATA 0x004b 577 #define regMMSCH_VF_MAILBOX0_DATA_BASE_IDX 0 578 #define regMMSCH_VF_MAILBOX1_DATA 0x004c 579 #define regMMSCH_VF_MAILBOX1_DATA_BASE_IDX 0 580 #define regMMSCH_GPUIOV_SCH_BLOCK_IP_0 0x004d 581 #define regMMSCH_GPUIOV_SCH_BLOCK_IP_0_BASE_IDX 0 582 #define regMMSCH_GPUIOV_CMD_STATUS_IP_0 0x004e 583 #define regMMSCH_GPUIOV_CMD_STATUS_IP_0_BASE_IDX 0 584 #define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0 0x004f 585 #define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0_BASE_IDX 0 586 #define regMMSCH_GPUIOV_SCH_BLOCK_IP_1 0x0050 587 #define regMMSCH_GPUIOV_SCH_BLOCK_IP_1_BASE_IDX 0 588 #define regMMSCH_GPUIOV_CMD_STATUS_IP_1 0x0051 589 #define regMMSCH_GPUIOV_CMD_STATUS_IP_1_BASE_IDX 0 590 #define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1 0x0052 591 #define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1_BASE_IDX 0 592 #define regMMSCH_GPUIOV_CNTXT_IP 0x0053 593 #define regMMSCH_GPUIOV_CNTXT_IP_BASE_IDX 0 594 #define regMMSCH_GPUIOV_SCH_BLOCK_2 0x0054 595 #define regMMSCH_GPUIOV_SCH_BLOCK_2_BASE_IDX 0 596 #define regMMSCH_GPUIOV_CMD_CONTROL_2 0x0055 597 #define regMMSCH_GPUIOV_CMD_CONTROL_2_BASE_IDX 0 598 #define regMMSCH_GPUIOV_CMD_STATUS_2 0x0056 599 #define regMMSCH_GPUIOV_CMD_STATUS_2_BASE_IDX 0 600 #define regMMSCH_GPUIOV_VM_BUSY_STATUS_2 0x0057 601 #define regMMSCH_GPUIOV_VM_BUSY_STATUS_2_BASE_IDX 0 602 #define regMMSCH_GPUIOV_ACTIVE_FCNS_2 0x0058 603 #define regMMSCH_GPUIOV_ACTIVE_FCNS_2_BASE_IDX 0 604 #define regMMSCH_GPUIOV_ACTIVE_FCN_ID_2 0x0059 605 #define regMMSCH_GPUIOV_ACTIVE_FCN_ID_2_BASE_IDX 0 606 #define regMMSCH_GPUIOV_DW6_2 0x005a 607 #define regMMSCH_GPUIOV_DW6_2_BASE_IDX 0 608 #define regMMSCH_GPUIOV_DW7_2 0x005b 609 #define regMMSCH_GPUIOV_DW7_2_BASE_IDX 0 610 #define regMMSCH_GPUIOV_DW8_2 0x005c 611 #define regMMSCH_GPUIOV_DW8_2_BASE_IDX 0 612 #define regMMSCH_GPUIOV_SCH_BLOCK_IP_2 0x005d 613 #define regMMSCH_GPUIOV_SCH_BLOCK_IP_2_BASE_IDX 0 614 #define regMMSCH_GPUIOV_CMD_STATUS_IP_2 0x005e 615 #define regMMSCH_GPUIOV_CMD_STATUS_IP_2_BASE_IDX 0 616 #define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2 0x005f 617 #define regMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2_BASE_IDX 0 618 #define regMMSCH_VFID_FIFO_HEAD_2 0x0060 619 #define regMMSCH_VFID_FIFO_HEAD_2_BASE_IDX 0 620 #define regMMSCH_VFID_FIFO_TAIL_2 0x0061 621 #define regMMSCH_VFID_FIFO_TAIL_2_BASE_IDX 0 622 #define regMMSCH_VM_BUSY_STATUS_0 0x0062 623 #define regMMSCH_VM_BUSY_STATUS_0_BASE_IDX 0 624 #define regMMSCH_VM_BUSY_STATUS_1 0x0063 625 #define regMMSCH_VM_BUSY_STATUS_1_BASE_IDX 0 626 #define regMMSCH_VM_BUSY_STATUS_2 0x0064 627 #define regMMSCH_VM_BUSY_STATUS_2_BASE_IDX 0 628 629 630 // addressBlock: uvd0_uvd_jmi_dec 631 // base address: 0x1e500 632 #define regUVD_JADP_MCIF_URGENT_CTRL 0x0141 633 #define regUVD_JADP_MCIF_URGENT_CTRL_BASE_IDX 0 634 #define regUVD_JMI_URGENT_CTRL 0x0142 635 #define regUVD_JMI_URGENT_CTRL_BASE_IDX 0 636 #define regUVD_JPEG_DEC_PF_CTRL 0x0143 637 #define regUVD_JPEG_DEC_PF_CTRL_BASE_IDX 0 638 #define regUVD_JPEG_ENC_PF_CTRL 0x0144 639 #define regUVD_JPEG_ENC_PF_CTRL_BASE_IDX 0 640 #define regUVD_JMI_CTRL 0x0145 641 #define regUVD_JMI_CTRL_BASE_IDX 0 642 #define regUVD_LMI_JRBC_CTRL 0x0146 643 #define regUVD_LMI_JRBC_CTRL_BASE_IDX 0 644 #define regUVD_LMI_JPEG_CTRL 0x0147 645 #define regUVD_LMI_JPEG_CTRL_BASE_IDX 0 646 #define regUVD_JMI_EJRBC_CTRL 0x0148 647 #define regUVD_JMI_EJRBC_CTRL_BASE_IDX 0 648 #define regUVD_LMI_EJPEG_CTRL 0x0149 649 #define regUVD_LMI_EJPEG_CTRL_BASE_IDX 0 650 #define regUVD_JMI_SCALER_CTRL 0x014a 651 #define regUVD_JMI_SCALER_CTRL_BASE_IDX 0 652 #define regJPEG_LMI_DROP 0x014b 653 #define regJPEG_LMI_DROP_BASE_IDX 0 654 #define regUVD_JMI_EJPEG_DROP 0x014c 655 #define regUVD_JMI_EJPEG_DROP_BASE_IDX 0 656 #define regJPEG_MEMCHECK_CLAMPING 0x014d 657 #define regJPEG_MEMCHECK_CLAMPING_BASE_IDX 0 658 #define regUVD_JMI_EJPEG_MEMCHECK_CLAMPING 0x014e 659 #define regUVD_JMI_EJPEG_MEMCHECK_CLAMPING_BASE_IDX 0 660 #define regUVD_LMI_JRBC_IB_VMID 0x014f 661 #define regUVD_LMI_JRBC_IB_VMID_BASE_IDX 0 662 #define regUVD_LMI_JRBC_RB_VMID 0x0150 663 #define regUVD_LMI_JRBC_RB_VMID_BASE_IDX 0 664 #define regUVD_LMI_JPEG_VMID 0x0151 665 #define regUVD_LMI_JPEG_VMID_BASE_IDX 0 666 #define regUVD_JMI_ENC_JRBC_IB_VMID 0x0152 667 #define regUVD_JMI_ENC_JRBC_IB_VMID_BASE_IDX 0 668 #define regUVD_JMI_ENC_JRBC_RB_VMID 0x0153 669 #define regUVD_JMI_ENC_JRBC_RB_VMID_BASE_IDX 0 670 #define regUVD_JMI_ENC_JPEG_VMID 0x0154 671 #define regUVD_JMI_ENC_JPEG_VMID_BASE_IDX 0 672 #define regUVD_JMI_EJPEG_RAS_CNTL 0x0156 673 #define regUVD_JMI_EJPEG_RAS_CNTL_BASE_IDX 0 674 #define regJPEG_MEMCHECK_SAFE_ADDR 0x0157 675 #define regJPEG_MEMCHECK_SAFE_ADDR_BASE_IDX 0 676 #define regJPEG_MEMCHECK_SAFE_ADDR_64BIT 0x0158 677 #define regJPEG_MEMCHECK_SAFE_ADDR_64BIT_BASE_IDX 0 678 #define regUVD_JMI_LAT_CTRL 0x0159 679 #define regUVD_JMI_LAT_CTRL_BASE_IDX 0 680 #define regUVD_JMI_LAT_CNTR 0x015a 681 #define regUVD_JMI_LAT_CNTR_BASE_IDX 0 682 #define regUVD_JMI_AVG_LAT_CNTR 0x015b 683 #define regUVD_JMI_AVG_LAT_CNTR_BASE_IDX 0 684 #define regUVD_JMI_PERFMON_CTRL 0x015c 685 #define regUVD_JMI_PERFMON_CTRL_BASE_IDX 0 686 #define regUVD_JMI_PERFMON_COUNT_LO 0x015d 687 #define regUVD_JMI_PERFMON_COUNT_LO_BASE_IDX 0 688 #define regUVD_JMI_PERFMON_COUNT_HI 0x015e 689 #define regUVD_JMI_PERFMON_COUNT_HI_BASE_IDX 0 690 #define regUVD_JMI_CLEAN_STATUS 0x015f 691 #define regUVD_JMI_CLEAN_STATUS_BASE_IDX 0 692 #define regUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x0160 693 #define regUVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 0 694 #define regUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x0161 695 #define regUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX 0 696 #define regUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0162 697 #define regUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX 0 698 #define regUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x0163 699 #define regUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 700 #define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x0164 701 #define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0 702 #define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x0165 703 #define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 704 #define regUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0166 705 #define regUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 0 706 #define regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x0167 707 #define regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0 708 #define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW 0x0168 709 #define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX 0 710 #define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0x0169 711 #define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0 712 #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x016a 713 #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 714 #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x016b 715 #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 716 #define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 0x016c 717 #define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 718 #define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x016d 719 #define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 720 #define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 0x016e 721 #define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 722 #define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x016f 723 #define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 724 #define regUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW 0x0170 725 #define regUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 726 #define regUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH 0x0171 727 #define regUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 728 #define regUVD_JMI_PEL_RD_64BIT_BAR_LOW 0x0172 729 #define regUVD_JMI_PEL_RD_64BIT_BAR_LOW_BASE_IDX 0 730 #define regUVD_JMI_PEL_RD_64BIT_BAR_HIGH 0x0173 731 #define regUVD_JMI_PEL_RD_64BIT_BAR_HIGH_BASE_IDX 0 732 #define regUVD_JMI_BS_WR_64BIT_BAR_LOW 0x0174 733 #define regUVD_JMI_BS_WR_64BIT_BAR_LOW_BASE_IDX 0 734 #define regUVD_JMI_BS_WR_64BIT_BAR_HIGH 0x0175 735 #define regUVD_JMI_BS_WR_64BIT_BAR_HIGH_BASE_IDX 0 736 #define regUVD_JMI_SCALAR_RD_64BIT_BAR_LOW 0x0176 737 #define regUVD_JMI_SCALAR_RD_64BIT_BAR_LOW_BASE_IDX 0 738 #define regUVD_JMI_SCALAR_RD_64BIT_BAR_HIGH 0x0177 739 #define regUVD_JMI_SCALAR_RD_64BIT_BAR_HIGH_BASE_IDX 0 740 #define regUVD_JMI_SCALAR_WR_64BIT_BAR_LOW 0x0178 741 #define regUVD_JMI_SCALAR_WR_64BIT_BAR_LOW_BASE_IDX 0 742 #define regUVD_JMI_SCALAR_WR_64BIT_BAR_HIGH 0x0179 743 #define regUVD_JMI_SCALAR_WR_64BIT_BAR_HIGH_BASE_IDX 0 744 #define regUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x017a 745 #define regUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0 746 #define regUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x017b 747 #define regUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 748 #define regUVD_LMI_EJRBC_RB_64BIT_BAR_LOW 0x017c 749 #define regUVD_LMI_EJRBC_RB_64BIT_BAR_LOW_BASE_IDX 0 750 #define regUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH 0x017d 751 #define regUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0 752 #define regUVD_LMI_EJRBC_IB_64BIT_BAR_LOW 0x017e 753 #define regUVD_LMI_EJRBC_IB_64BIT_BAR_LOW_BASE_IDX 0 754 #define regUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH 0x017f 755 #define regUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0 756 #define regUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW 0x0180 757 #define regUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 758 #define regUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x0181 759 #define regUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 760 #define regUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW 0x0182 761 #define regUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 762 #define regUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x0183 763 #define regUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 764 #define regUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW 0x0184 765 #define regUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 766 #define regUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x0185 767 #define regUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 768 #define regUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW 0x0186 769 #define regUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 770 #define regUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH 0x0187 771 #define regUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 772 #define regUVD_LMI_JPEG_PREEMPT_VMID 0x0188 773 #define regUVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX 0 774 #define regUVD_LMI_ENC_JPEG_PREEMPT_VMID 0x0189 775 #define regUVD_LMI_ENC_JPEG_PREEMPT_VMID_BASE_IDX 0 776 #define regUVD_LMI_JPEG2_VMID 0x018a 777 #define regUVD_LMI_JPEG2_VMID_BASE_IDX 0 778 #define regUVD_LMI_JPEG2_READ_64BIT_BAR_LOW 0x018b 779 #define regUVD_LMI_JPEG2_READ_64BIT_BAR_LOW_BASE_IDX 0 780 #define regUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH 0x018c 781 #define regUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH_BASE_IDX 0 782 #define regUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW 0x018d 783 #define regUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW_BASE_IDX 0 784 #define regUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH 0x018e 785 #define regUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 786 #define regUVD_LMI_JPEG_CTRL2 0x018f 787 #define regUVD_LMI_JPEG_CTRL2_BASE_IDX 0 788 #define regUVD_JMI_DEC_SWAP_CNTL 0x0190 789 #define regUVD_JMI_DEC_SWAP_CNTL_BASE_IDX 0 790 #define regUVD_JMI_ENC_SWAP_CNTL 0x0191 791 #define regUVD_JMI_ENC_SWAP_CNTL_BASE_IDX 0 792 #define regUVD_JMI_CNTL 0x0192 793 #define regUVD_JMI_CNTL_BASE_IDX 0 794 #define regUVD_JMI_ATOMIC_CNTL 0x0193 795 #define regUVD_JMI_ATOMIC_CNTL_BASE_IDX 0 796 #define regUVD_JMI_ATOMIC_CNTL2 0x0194 797 #define regUVD_JMI_ATOMIC_CNTL2_BASE_IDX 0 798 #define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 0x0195 799 #define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX 0 800 #define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 0x0196 801 #define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 802 #define regUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW 0x0197 803 #define regUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW_BASE_IDX 0 804 #define regUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH 0x0198 805 #define regUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 806 #define regJPEG2_LMI_DROP 0x0199 807 #define regJPEG2_LMI_DROP_BASE_IDX 0 808 #define regUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW 0x019a 809 #define regUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW_BASE_IDX 0 810 #define regUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH 0x019b 811 #define regUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 812 #define regUVD_JMI_DEC_SWAP_CNTL2 0x019c 813 #define regUVD_JMI_DEC_SWAP_CNTL2_BASE_IDX 0 814 #define regUVD_JMI_DJPEG_RAS_CNTL 0x019f 815 #define regUVD_JMI_DJPEG_RAS_CNTL_BASE_IDX 0 816 817 818 // addressBlock: uvd0_uvd_jpeg_common_dec 819 // base address: 0x1e700 820 #define regJPEG_SOFT_RESET_STATUS 0x01c0 821 #define regJPEG_SOFT_RESET_STATUS_BASE_IDX 0 822 #define regJPEG_SYS_INT_EN 0x01c1 823 #define regJPEG_SYS_INT_EN_BASE_IDX 0 824 #define regJPEG_SYS_INT_STATUS 0x01c2 825 #define regJPEG_SYS_INT_STATUS_BASE_IDX 0 826 #define regJPEG_SYS_INT_ACK 0x01c3 827 #define regJPEG_SYS_INT_ACK_BASE_IDX 0 828 #define regJPEG_MEMCHECK_SYS_INT_EN 0x01c4 829 #define regJPEG_MEMCHECK_SYS_INT_EN_BASE_IDX 0 830 #define regJPEG_MEMCHECK_SYS_INT_STAT 0x01c5 831 #define regJPEG_MEMCHECK_SYS_INT_STAT_BASE_IDX 0 832 #define regJPEG_MEMCHECK_SYS_INT_ACK 0x01c6 833 #define regJPEG_MEMCHECK_SYS_INT_ACK_BASE_IDX 0 834 #define regJPEG_MASTINT_EN 0x01c8 835 #define regJPEG_MASTINT_EN_BASE_IDX 0 836 #define regJPEG_IH_CTRL 0x01c9 837 #define regJPEG_IH_CTRL_BASE_IDX 0 838 #define regJRBBM_ARB_CTRL 0x01cb 839 #define regJRBBM_ARB_CTRL_BASE_IDX 0 840 841 842 // addressBlock: uvd0_uvd_jpeg_common_sclk_dec 843 // base address: 0x1e780 844 #define regJPEG_CGC_GATE 0x01e0 845 #define regJPEG_CGC_GATE_BASE_IDX 0 846 #define regJPEG_CGC_CTRL 0x01e1 847 #define regJPEG_CGC_CTRL_BASE_IDX 0 848 #define regJPEG_CGC_STATUS 0x01e2 849 #define regJPEG_CGC_STATUS_BASE_IDX 0 850 #define regJPEG_COMN_CGC_MEM_CTRL 0x01e3 851 #define regJPEG_COMN_CGC_MEM_CTRL_BASE_IDX 0 852 #define regJPEG_DEC_CGC_MEM_CTRL 0x01e4 853 #define regJPEG_DEC_CGC_MEM_CTRL_BASE_IDX 0 854 #define regJPEG2_DEC_CGC_MEM_CTRL 0x01e5 855 #define regJPEG2_DEC_CGC_MEM_CTRL_BASE_IDX 0 856 #define regJPEG_ENC_CGC_MEM_CTRL 0x01e6 857 #define regJPEG_ENC_CGC_MEM_CTRL_BASE_IDX 0 858 #define regJPEG_SOFT_RESET2 0x01e7 859 #define regJPEG_SOFT_RESET2_BASE_IDX 0 860 #define regJPEG_PERF_BANK_CONF 0x01e8 861 #define regJPEG_PERF_BANK_CONF_BASE_IDX 0 862 #define regJPEG_PERF_BANK_EVENT_SEL 0x01e9 863 #define regJPEG_PERF_BANK_EVENT_SEL_BASE_IDX 0 864 #define regJPEG_PERF_BANK_COUNT0 0x01ea 865 #define regJPEG_PERF_BANK_COUNT0_BASE_IDX 0 866 #define regJPEG_PERF_BANK_COUNT1 0x01eb 867 #define regJPEG_PERF_BANK_COUNT1_BASE_IDX 0 868 #define regJPEG_PERF_BANK_COUNT2 0x01ec 869 #define regJPEG_PERF_BANK_COUNT2_BASE_IDX 0 870 #define regJPEG_PERF_BANK_COUNT3 0x01ed 871 #define regJPEG_PERF_BANK_COUNT3_BASE_IDX 0 872 873 874 // addressBlock: uvd0_uvd_jpeg_enc_dec 875 // base address: 0x1e300 876 #define regUVD_JPEG_ENC_INT_EN 0x00c1 877 #define regUVD_JPEG_ENC_INT_EN_BASE_IDX 0 878 #define regUVD_JPEG_ENC_INT_STATUS 0x00c2 879 #define regUVD_JPEG_ENC_INT_STATUS_BASE_IDX 0 880 #define regUVD_JPEG_ENC_ENGINE_CNTL 0x00c5 881 #define regUVD_JPEG_ENC_ENGINE_CNTL_BASE_IDX 0 882 #define regUVD_JPEG_ENC_SCRATCH1 0x00ce 883 #define regUVD_JPEG_ENC_SCRATCH1_BASE_IDX 0 884 885 886 // addressBlock: uvd0_uvd_jpeg_enc_sclk_dec 887 // base address: 0x1e380 888 #define regUVD_JPEG_ENC_SPS_INFO 0x00e0 889 #define regUVD_JPEG_ENC_SPS_INFO_BASE_IDX 0 890 #define regUVD_JPEG_ENC_SPS_INFO1 0x00e1 891 #define regUVD_JPEG_ENC_SPS_INFO1_BASE_IDX 0 892 #define regUVD_JPEG_ENC_TBL_SIZE 0x00e2 893 #define regUVD_JPEG_ENC_TBL_SIZE_BASE_IDX 0 894 #define regUVD_JPEG_ENC_TBL_CNTL 0x00e3 895 #define regUVD_JPEG_ENC_TBL_CNTL_BASE_IDX 0 896 #define regUVD_JPEG_ENC_MC_REQ_CNTL 0x00e4 897 #define regUVD_JPEG_ENC_MC_REQ_CNTL_BASE_IDX 0 898 #define regUVD_JPEG_ENC_STATUS 0x00e5 899 #define regUVD_JPEG_ENC_STATUS_BASE_IDX 0 900 #define regUVD_JPEG_ENC_PITCH 0x00e6 901 #define regUVD_JPEG_ENC_PITCH_BASE_IDX 0 902 #define regUVD_JPEG_ENC_LUMA_BASE 0x00e7 903 #define regUVD_JPEG_ENC_LUMA_BASE_BASE_IDX 0 904 #define regUVD_JPEG_ENC_CHROMAU_BASE 0x00e8 905 #define regUVD_JPEG_ENC_CHROMAU_BASE_BASE_IDX 0 906 #define regUVD_JPEG_ENC_CHROMAV_BASE 0x00e9 907 #define regUVD_JPEG_ENC_CHROMAV_BASE_BASE_IDX 0 908 #define regJPEG_ENC_Y_GFX10_TILING_SURFACE 0x00ea 909 #define regJPEG_ENC_Y_GFX10_TILING_SURFACE_BASE_IDX 0 910 #define regJPEG_ENC_UV_GFX10_TILING_SURFACE 0x00eb 911 #define regJPEG_ENC_UV_GFX10_TILING_SURFACE_BASE_IDX 0 912 #define regJPEG_ENC_GFX10_ADDR_CONFIG 0x00ec 913 #define regJPEG_ENC_GFX10_ADDR_CONFIG_BASE_IDX 0 914 #define regJPEG_ENC_ADDR_MODE 0x00ed 915 #define regJPEG_ENC_ADDR_MODE_BASE_IDX 0 916 #define regUVD_JPEG_ENC_GPCOM_CMD 0x00ee 917 #define regUVD_JPEG_ENC_GPCOM_CMD_BASE_IDX 0 918 #define regUVD_JPEG_ENC_GPCOM_DATA0 0x00ef 919 #define regUVD_JPEG_ENC_GPCOM_DATA0_BASE_IDX 0 920 #define regUVD_JPEG_ENC_GPCOM_DATA1 0x00f0 921 #define regUVD_JPEG_ENC_GPCOM_DATA1_BASE_IDX 0 922 #define regUVD_JPEG_TBL_DAT0 0x00f1 923 #define regUVD_JPEG_TBL_DAT0_BASE_IDX 0 924 #define regUVD_JPEG_TBL_DAT1 0x00f2 925 #define regUVD_JPEG_TBL_DAT1_BASE_IDX 0 926 #define regUVD_JPEG_TBL_IDX 0x00f3 927 #define regUVD_JPEG_TBL_IDX_BASE_IDX 0 928 #define regUVD_JPEG_ENC_CGC_CNTL 0x00f5 929 #define regUVD_JPEG_ENC_CGC_CNTL_BASE_IDX 0 930 #define regUVD_JPEG_ENC_SCRATCH0 0x00f6 931 #define regUVD_JPEG_ENC_SCRATCH0_BASE_IDX 0 932 #define regUVD_JPEG_ENC_SOFT_RST 0x00f7 933 #define regUVD_JPEG_ENC_SOFT_RST_BASE_IDX 0 934 935 936 // addressBlock: uvd0_uvd_jrbc_dec 937 // base address: 0x1e400 938 #define regUVD_JRBC_RB_WPTR 0x0100 939 #define regUVD_JRBC_RB_WPTR_BASE_IDX 0 940 #define regUVD_JRBC_RB_CNTL 0x0101 941 #define regUVD_JRBC_RB_CNTL_BASE_IDX 0 942 #define regUVD_JRBC_IB_SIZE 0x0102 943 #define regUVD_JRBC_IB_SIZE_BASE_IDX 0 944 #define regUVD_JRBC_URGENT_CNTL 0x0103 945 #define regUVD_JRBC_URGENT_CNTL_BASE_IDX 0 946 #define regUVD_JRBC_RB_REF_DATA 0x0104 947 #define regUVD_JRBC_RB_REF_DATA_BASE_IDX 0 948 #define regUVD_JRBC_RB_COND_RD_TIMER 0x0105 949 #define regUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 0 950 #define regUVD_JRBC_SOFT_RESET 0x0108 951 #define regUVD_JRBC_SOFT_RESET_BASE_IDX 0 952 #define regUVD_JRBC_STATUS 0x0109 953 #define regUVD_JRBC_STATUS_BASE_IDX 0 954 #define regUVD_JRBC_RB_RPTR 0x010a 955 #define regUVD_JRBC_RB_RPTR_BASE_IDX 0 956 #define regUVD_JRBC_RB_BUF_STATUS 0x010b 957 #define regUVD_JRBC_RB_BUF_STATUS_BASE_IDX 0 958 #define regUVD_JRBC_IB_BUF_STATUS 0x010c 959 #define regUVD_JRBC_IB_BUF_STATUS_BASE_IDX 0 960 #define regUVD_JRBC_IB_SIZE_UPDATE 0x010d 961 #define regUVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 0 962 #define regUVD_JRBC_IB_COND_RD_TIMER 0x010e 963 #define regUVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 0 964 #define regUVD_JRBC_IB_REF_DATA 0x010f 965 #define regUVD_JRBC_IB_REF_DATA_BASE_IDX 0 966 #define regUVD_JPEG_PREEMPT_CMD 0x0110 967 #define regUVD_JPEG_PREEMPT_CMD_BASE_IDX 0 968 #define regUVD_JPEG_PREEMPT_FENCE_DATA0 0x0111 969 #define regUVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 0 970 #define regUVD_JPEG_PREEMPT_FENCE_DATA1 0x0112 971 #define regUVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 0 972 #define regUVD_JRBC_RB_SIZE 0x0113 973 #define regUVD_JRBC_RB_SIZE_BASE_IDX 0 974 #define regUVD_JRBC_SCRATCH0 0x0114 975 #define regUVD_JRBC_SCRATCH0_BASE_IDX 0 976 977 978 // addressBlock: uvd0_uvd_jrbc_enc_dec 979 // base address: 0x1e480 980 #define regUVD_JRBC_ENC_RB_WPTR 0x0120 981 #define regUVD_JRBC_ENC_RB_WPTR_BASE_IDX 0 982 #define regUVD_JRBC_ENC_RB_CNTL 0x0121 983 #define regUVD_JRBC_ENC_RB_CNTL_BASE_IDX 0 984 #define regUVD_JRBC_ENC_IB_SIZE 0x0122 985 #define regUVD_JRBC_ENC_IB_SIZE_BASE_IDX 0 986 #define regUVD_JRBC_ENC_URGENT_CNTL 0x0123 987 #define regUVD_JRBC_ENC_URGENT_CNTL_BASE_IDX 0 988 #define regUVD_JRBC_ENC_RB_REF_DATA 0x0124 989 #define regUVD_JRBC_ENC_RB_REF_DATA_BASE_IDX 0 990 #define regUVD_JRBC_ENC_RB_COND_RD_TIMER 0x0125 991 #define regUVD_JRBC_ENC_RB_COND_RD_TIMER_BASE_IDX 0 992 #define regUVD_JRBC_ENC_SOFT_RESET 0x0128 993 #define regUVD_JRBC_ENC_SOFT_RESET_BASE_IDX 0 994 #define regUVD_JRBC_ENC_STATUS 0x0129 995 #define regUVD_JRBC_ENC_STATUS_BASE_IDX 0 996 #define regUVD_JRBC_ENC_RB_RPTR 0x012a 997 #define regUVD_JRBC_ENC_RB_RPTR_BASE_IDX 0 998 #define regUVD_JRBC_ENC_RB_BUF_STATUS 0x012b 999 #define regUVD_JRBC_ENC_RB_BUF_STATUS_BASE_IDX 0 1000 #define regUVD_JRBC_ENC_IB_BUF_STATUS 0x012c 1001 #define regUVD_JRBC_ENC_IB_BUF_STATUS_BASE_IDX 0 1002 #define regUVD_JRBC_ENC_IB_SIZE_UPDATE 0x012d 1003 #define regUVD_JRBC_ENC_IB_SIZE_UPDATE_BASE_IDX 0 1004 #define regUVD_JRBC_ENC_IB_COND_RD_TIMER 0x012e 1005 #define regUVD_JRBC_ENC_IB_COND_RD_TIMER_BASE_IDX 0 1006 #define regUVD_JRBC_ENC_IB_REF_DATA 0x012f 1007 #define regUVD_JRBC_ENC_IB_REF_DATA_BASE_IDX 0 1008 #define regUVD_JPEG_ENC_PREEMPT_CMD 0x0130 1009 #define regUVD_JPEG_ENC_PREEMPT_CMD_BASE_IDX 0 1010 #define regUVD_JPEG_ENC_PREEMPT_FENCE_DATA0 0x0131 1011 #define regUVD_JPEG_ENC_PREEMPT_FENCE_DATA0_BASE_IDX 0 1012 #define regUVD_JPEG_ENC_PREEMPT_FENCE_DATA1 0x0132 1013 #define regUVD_JPEG_ENC_PREEMPT_FENCE_DATA1_BASE_IDX 0 1014 #define regUVD_JRBC_ENC_RB_SIZE 0x0133 1015 #define regUVD_JRBC_ENC_RB_SIZE_BASE_IDX 0 1016 #define regUVD_JRBC_ENC_SCRATCH0 0x0134 1017 #define regUVD_JRBC_ENC_SCRATCH0_BASE_IDX 0 1018 1019 1020 // addressBlock: uvd0_uvd_mpcdec 1021 // base address: 0x20310 1022 #define regUVD_MP_SWAP_CNTL 0x02c4 1023 #define regUVD_MP_SWAP_CNTL_BASE_IDX 1 1024 #define regUVD_MP_SWAP_CNTL2 0x02c5 1025 #define regUVD_MP_SWAP_CNTL2_BASE_IDX 1 1026 #define regUVD_MPC_LUMA_SRCH 0x02c6 1027 #define regUVD_MPC_LUMA_SRCH_BASE_IDX 1 1028 #define regUVD_MPC_LUMA_HIT 0x02c7 1029 #define regUVD_MPC_LUMA_HIT_BASE_IDX 1 1030 #define regUVD_MPC_LUMA_HITPEND 0x02c8 1031 #define regUVD_MPC_LUMA_HITPEND_BASE_IDX 1 1032 #define regUVD_MPC_CHROMA_SRCH 0x02c9 1033 #define regUVD_MPC_CHROMA_SRCH_BASE_IDX 1 1034 #define regUVD_MPC_CHROMA_HIT 0x02ca 1035 #define regUVD_MPC_CHROMA_HIT_BASE_IDX 1 1036 #define regUVD_MPC_CHROMA_HITPEND 0x02cb 1037 #define regUVD_MPC_CHROMA_HITPEND_BASE_IDX 1 1038 #define regUVD_MPC_CNTL 0x02cc 1039 #define regUVD_MPC_CNTL_BASE_IDX 1 1040 #define regUVD_MPC_PITCH 0x02cd 1041 #define regUVD_MPC_PITCH_BASE_IDX 1 1042 #define regUVD_MPC_SET_MUXA0 0x02ce 1043 #define regUVD_MPC_SET_MUXA0_BASE_IDX 1 1044 #define regUVD_MPC_SET_MUXA1 0x02cf 1045 #define regUVD_MPC_SET_MUXA1_BASE_IDX 1 1046 #define regUVD_MPC_SET_MUXB0 0x02d0 1047 #define regUVD_MPC_SET_MUXB0_BASE_IDX 1 1048 #define regUVD_MPC_SET_MUXB1 0x02d1 1049 #define regUVD_MPC_SET_MUXB1_BASE_IDX 1 1050 #define regUVD_MPC_SET_MUX 0x02d2 1051 #define regUVD_MPC_SET_MUX_BASE_IDX 1 1052 #define regUVD_MPC_SET_ALU 0x02d3 1053 #define regUVD_MPC_SET_ALU_BASE_IDX 1 1054 #define regUVD_MPC_PERF0 0x02d4 1055 #define regUVD_MPC_PERF0_BASE_IDX 1 1056 #define regUVD_MPC_PERF1 0x02d5 1057 #define regUVD_MPC_PERF1_BASE_IDX 1 1058 #define regUVD_MPC_IND_INDEX 0x02d6 1059 #define regUVD_MPC_IND_INDEX_BASE_IDX 1 1060 #define regUVD_MPC_IND_DATA 0x02d7 1061 #define regUVD_MPC_IND_DATA_BASE_IDX 1 1062 1063 1064 // addressBlock: uvd0_uvd_pg_dec 1065 // base address: 0x1f800 1066 #define regUVD_PGFSM_CONFIG 0x0000 1067 #define regUVD_PGFSM_CONFIG_BASE_IDX 1 1068 #define regUVD_PGFSM_STATUS 0x0001 1069 #define regUVD_PGFSM_STATUS_BASE_IDX 1 1070 #define regUVD_POWER_STATUS 0x0004 1071 #define regUVD_POWER_STATUS_BASE_IDX 1 1072 #define regUVD_PG_IND_INDEX 0x0005 1073 #define regUVD_PG_IND_INDEX_BASE_IDX 1 1074 #define regUVD_PG_IND_DATA 0x0006 1075 #define regUVD_PG_IND_DATA_BASE_IDX 1 1076 #define regCC_UVD_HARVESTING 0x0007 1077 #define regCC_UVD_HARVESTING_BASE_IDX 1 1078 #define regUVD_JPEG_POWER_STATUS 0x000a 1079 #define regUVD_JPEG_POWER_STATUS_BASE_IDX 1 1080 #define regUVD_DPG_LMA_CTL 0x0011 1081 #define regUVD_DPG_LMA_CTL_BASE_IDX 1 1082 #define regUVD_DPG_LMA_DATA 0x0012 1083 #define regUVD_DPG_LMA_DATA_BASE_IDX 1 1084 #define regUVD_DPG_LMA_MASK 0x0013 1085 #define regUVD_DPG_LMA_MASK_BASE_IDX 1 1086 #define regUVD_DPG_PAUSE 0x0014 1087 #define regUVD_DPG_PAUSE_BASE_IDX 1 1088 #define regUVD_SCRATCH1 0x0015 1089 #define regUVD_SCRATCH1_BASE_IDX 1 1090 #define regUVD_SCRATCH2 0x0016 1091 #define regUVD_SCRATCH2_BASE_IDX 1 1092 #define regUVD_SCRATCH3 0x0017 1093 #define regUVD_SCRATCH3_BASE_IDX 1 1094 #define regUVD_SCRATCH4 0x0018 1095 #define regUVD_SCRATCH4_BASE_IDX 1 1096 #define regUVD_SCRATCH5 0x0019 1097 #define regUVD_SCRATCH5_BASE_IDX 1 1098 #define regUVD_SCRATCH6 0x001a 1099 #define regUVD_SCRATCH6_BASE_IDX 1 1100 #define regUVD_SCRATCH7 0x001b 1101 #define regUVD_SCRATCH7_BASE_IDX 1 1102 #define regUVD_SCRATCH8 0x001c 1103 #define regUVD_SCRATCH8_BASE_IDX 1 1104 #define regUVD_SCRATCH9 0x001d 1105 #define regUVD_SCRATCH9_BASE_IDX 1 1106 #define regUVD_SCRATCH10 0x001e 1107 #define regUVD_SCRATCH10_BASE_IDX 1 1108 #define regUVD_SCRATCH11 0x001f 1109 #define regUVD_SCRATCH11_BASE_IDX 1 1110 #define regUVD_SCRATCH12 0x0020 1111 #define regUVD_SCRATCH12_BASE_IDX 1 1112 #define regUVD_SCRATCH13 0x0021 1113 #define regUVD_SCRATCH13_BASE_IDX 1 1114 #define regUVD_SCRATCH14 0x0022 1115 #define regUVD_SCRATCH14_BASE_IDX 1 1116 #define regUVD_FREE_COUNTER_REG 0x0024 1117 #define regUVD_FREE_COUNTER_REG_BASE_IDX 1 1118 #define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x0025 1119 #define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 1120 #define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x0026 1121 #define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 1122 #define regUVD_DPG_VCPU_CACHE_OFFSET0 0x0027 1123 #define regUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX 1 1124 #define regUVD_DPG_LMI_VCPU_CACHE_VMID 0x0028 1125 #define regUVD_DPG_LMI_VCPU_CACHE_VMID_BASE_IDX 1 1126 #define regUVD_PF_STATUS 0x0039 1127 #define regUVD_PF_STATUS_BASE_IDX 1 1128 #define regUVD_FW_VERSION 0x003a 1129 #define regUVD_FW_VERSION_BASE_IDX 1 1130 #define regUVD_DPG_CLK_EN_VCPU_REPORT 0x003c 1131 #define regUVD_DPG_CLK_EN_VCPU_REPORT_BASE_IDX 1 1132 #define regUVD_GFX8_ADDR_CONFIG 0x0049 1133 #define regUVD_GFX8_ADDR_CONFIG_BASE_IDX 1 1134 #define regUVD_GFX10_ADDR_CONFIG 0x004a 1135 #define regUVD_GFX10_ADDR_CONFIG_BASE_IDX 1 1136 #define regUVD_GPCNT2_CNTL 0x004b 1137 #define regUVD_GPCNT2_CNTL_BASE_IDX 1 1138 #define regUVD_GPCNT2_TARGET_LOWER 0x004c 1139 #define regUVD_GPCNT2_TARGET_LOWER_BASE_IDX 1 1140 #define regUVD_GPCNT2_STATUS_LOWER 0x004d 1141 #define regUVD_GPCNT2_STATUS_LOWER_BASE_IDX 1 1142 #define regUVD_GPCNT2_TARGET_UPPER 0x004e 1143 #define regUVD_GPCNT2_TARGET_UPPER_BASE_IDX 1 1144 #define regUVD_GPCNT2_STATUS_UPPER 0x004f 1145 #define regUVD_GPCNT2_STATUS_UPPER_BASE_IDX 1 1146 #define regUVD_GPCNT3_CNTL 0x0050 1147 #define regUVD_GPCNT3_CNTL_BASE_IDX 1 1148 #define regUVD_GPCNT3_TARGET_LOWER 0x0051 1149 #define regUVD_GPCNT3_TARGET_LOWER_BASE_IDX 1 1150 #define regUVD_GPCNT3_STATUS_LOWER 0x0052 1151 #define regUVD_GPCNT3_STATUS_LOWER_BASE_IDX 1 1152 #define regUVD_GPCNT3_TARGET_UPPER 0x0053 1153 #define regUVD_GPCNT3_TARGET_UPPER_BASE_IDX 1 1154 #define regUVD_GPCNT3_STATUS_UPPER 0x0054 1155 #define regUVD_GPCNT3_STATUS_UPPER_BASE_IDX 1 1156 #define regUVD_VCLK_DS_CNTL 0x0055 1157 #define regUVD_VCLK_DS_CNTL_BASE_IDX 1 1158 #define regUVD_DCLK_DS_CNTL 0x0056 1159 #define regUVD_DCLK_DS_CNTL_BASE_IDX 1 1160 #define regUVD_RAS_VCPU_VCODEC_STATUS 0x0057 1161 #define regUVD_RAS_VCPU_VCODEC_STATUS_BASE_IDX 1 1162 #define regUVD_RAS_MMSCH_FATAL_ERROR 0x0058 1163 #define regUVD_RAS_MMSCH_FATAL_ERROR_BASE_IDX 1 1164 #define regUVD_RAS_JPEG0_STATUS 0x0059 1165 #define regUVD_RAS_JPEG0_STATUS_BASE_IDX 1 1166 #define regUVD_RAS_JPEG1_STATUS 0x005a 1167 #define regUVD_RAS_JPEG1_STATUS_BASE_IDX 1 1168 #define regUVD_RAS_CNTL_PMI_ARB 0x005b 1169 #define regUVD_RAS_CNTL_PMI_ARB_BASE_IDX 1 1170 1171 1172 // addressBlock: uvd0_uvd_rbcdec 1173 // base address: 0x20370 1174 #define regUVD_RBC_IB_SIZE 0x02dc 1175 #define regUVD_RBC_IB_SIZE_BASE_IDX 1 1176 #define regUVD_RBC_IB_SIZE_UPDATE 0x02dd 1177 #define regUVD_RBC_IB_SIZE_UPDATE_BASE_IDX 1 1178 #define regUVD_RBC_RB_CNTL 0x02de 1179 #define regUVD_RBC_RB_CNTL_BASE_IDX 1 1180 #define regUVD_RBC_RB_RPTR_ADDR 0x02df 1181 #define regUVD_RBC_RB_RPTR_ADDR_BASE_IDX 1 1182 #define regUVD_RBC_RB_RPTR 0x02e0 1183 #define regUVD_RBC_RB_RPTR_BASE_IDX 1 1184 #define regUVD_RBC_RB_WPTR 0x02e1 1185 #define regUVD_RBC_RB_WPTR_BASE_IDX 1 1186 #define regUVD_RBC_VCPU_ACCESS 0x02e2 1187 #define regUVD_RBC_VCPU_ACCESS_BASE_IDX 1 1188 #define regUVD_FW_SEMAPHORE_CNTL 0x02e3 1189 #define regUVD_FW_SEMAPHORE_CNTL_BASE_IDX 1 1190 #define regUVD_RBC_READ_REQ_URGENT_CNTL 0x02e5 1191 #define regUVD_RBC_READ_REQ_URGENT_CNTL_BASE_IDX 1 1192 #define regUVD_RBC_RB_WPTR_CNTL 0x02e6 1193 #define regUVD_RBC_RB_WPTR_CNTL_BASE_IDX 1 1194 #define regUVD_RBC_WPTR_STATUS 0x02e7 1195 #define regUVD_RBC_WPTR_STATUS_BASE_IDX 1 1196 #define regUVD_RBC_WPTR_POLL_CNTL 0x02e8 1197 #define regUVD_RBC_WPTR_POLL_CNTL_BASE_IDX 1 1198 #define regUVD_RBC_WPTR_POLL_ADDR 0x02e9 1199 #define regUVD_RBC_WPTR_POLL_ADDR_BASE_IDX 1 1200 #define regUVD_SEMA_CMD 0x02ea 1201 #define regUVD_SEMA_CMD_BASE_IDX 1 1202 #define regUVD_SEMA_ADDR_LOW 0x02eb 1203 #define regUVD_SEMA_ADDR_LOW_BASE_IDX 1 1204 #define regUVD_SEMA_ADDR_HIGH 0x02ec 1205 #define regUVD_SEMA_ADDR_HIGH_BASE_IDX 1 1206 #define regUVD_ENGINE_CNTL 0x02ed 1207 #define regUVD_ENGINE_CNTL_BASE_IDX 1 1208 #define regUVD_SEMA_TIMEOUT_STATUS 0x02ee 1209 #define regUVD_SEMA_TIMEOUT_STATUS_BASE_IDX 1 1210 #define regUVD_SEMA_CNTL 0x02ef 1211 #define regUVD_SEMA_CNTL_BASE_IDX 1 1212 #define regUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x02f0 1213 #define regUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 1214 #define regUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x02f1 1215 #define regUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX 1 1216 #define regUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x02f2 1217 #define regUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 1218 #define regUVD_JOB_START 0x02f3 1219 #define regUVD_JOB_START_BASE_IDX 1 1220 #define regUVD_RBC_BUF_STATUS 0x02f4 1221 #define regUVD_RBC_BUF_STATUS_BASE_IDX 1 1222 #define regUVD_RBC_SWAP_CNTL 0x02f5 1223 #define regUVD_RBC_SWAP_CNTL_BASE_IDX 1 1224 1225 1226 // addressBlock: uvd0_uvddec 1227 // base address: 0x1fa00 1228 #define regUVD_STATUS 0x0080 1229 #define regUVD_STATUS_BASE_IDX 1 1230 #define regUVD_ENC_PIPE_BUSY 0x0081 1231 #define regUVD_ENC_PIPE_BUSY_BASE_IDX 1 1232 #define regUVD_FW_POWER_STATUS 0x0082 1233 #define regUVD_FW_POWER_STATUS_BASE_IDX 1 1234 #define regUVD_CNTL 0x0083 1235 #define regUVD_CNTL_BASE_IDX 1 1236 #define regUVD_SOFT_RESET 0x0084 1237 #define regUVD_SOFT_RESET_BASE_IDX 1 1238 #define regUVD_SOFT_RESET2 0x0085 1239 #define regUVD_SOFT_RESET2_BASE_IDX 1 1240 #define regUVD_MMSCH_SOFT_RESET 0x0086 1241 #define regUVD_MMSCH_SOFT_RESET_BASE_IDX 1 1242 #define regUVD_WIG_CTRL 0x0087 1243 #define regUVD_WIG_CTRL_BASE_IDX 1 1244 #define regUVD_CGC_GATE 0x0088 1245 #define regUVD_CGC_GATE_BASE_IDX 1 1246 #define regUVD_CGC_STATUS 0x0089 1247 #define regUVD_CGC_STATUS_BASE_IDX 1 1248 #define regUVD_CGC_CTRL 0x008a 1249 #define regUVD_CGC_CTRL_BASE_IDX 1 1250 #define regUVD_CGC_UDEC_STATUS 0x008b 1251 #define regUVD_CGC_UDEC_STATUS_BASE_IDX 1 1252 #define regUVD_SUVD_CGC_GATE 0x008c 1253 #define regUVD_SUVD_CGC_GATE_BASE_IDX 1 1254 #define regUVD_SUVD_CGC_STATUS 0x008d 1255 #define regUVD_SUVD_CGC_STATUS_BASE_IDX 1 1256 #define regUVD_SUVD_CGC_CTRL 0x008e 1257 #define regUVD_SUVD_CGC_CTRL_BASE_IDX 1 1258 #define regUVD_GPCOM_VCPU_CMD 0x008f 1259 #define regUVD_GPCOM_VCPU_CMD_BASE_IDX 1 1260 #define regUVD_GPCOM_VCPU_DATA0 0x0090 1261 #define regUVD_GPCOM_VCPU_DATA0_BASE_IDX 1 1262 #define regUVD_GPCOM_VCPU_DATA1 0x0091 1263 #define regUVD_GPCOM_VCPU_DATA1_BASE_IDX 1 1264 #define regUVD_GPCOM_SYS_CMD 0x0092 1265 #define regUVD_GPCOM_SYS_CMD_BASE_IDX 1 1266 #define regUVD_GPCOM_SYS_DATA0 0x0093 1267 #define regUVD_GPCOM_SYS_DATA0_BASE_IDX 1 1268 #define regUVD_GPCOM_SYS_DATA1 0x0094 1269 #define regUVD_GPCOM_SYS_DATA1_BASE_IDX 1 1270 #define regUVD_VCPU_INT_EN 0x0095 1271 #define regUVD_VCPU_INT_EN_BASE_IDX 1 1272 #define regUVD_VCPU_INT_STATUS 0x0096 1273 #define regUVD_VCPU_INT_STATUS_BASE_IDX 1 1274 #define regUVD_VCPU_INT_ACK 0x0097 1275 #define regUVD_VCPU_INT_ACK_BASE_IDX 1 1276 #define regUVD_VCPU_INT_ROUTE 0x0098 1277 #define regUVD_VCPU_INT_ROUTE_BASE_IDX 1 1278 #define regUVD_DRV_FW_MSG 0x0099 1279 #define regUVD_DRV_FW_MSG_BASE_IDX 1 1280 #define regUVD_FW_DRV_MSG_ACK 0x009a 1281 #define regUVD_FW_DRV_MSG_ACK_BASE_IDX 1 1282 #define regUVD_SUVD_INT_EN 0x009b 1283 #define regUVD_SUVD_INT_EN_BASE_IDX 1 1284 #define regUVD_SUVD_INT_STATUS 0x009c 1285 #define regUVD_SUVD_INT_STATUS_BASE_IDX 1 1286 #define regUVD_SUVD_INT_ACK 0x009d 1287 #define regUVD_SUVD_INT_ACK_BASE_IDX 1 1288 #define regUVD_ENC_VCPU_INT_EN 0x009e 1289 #define regUVD_ENC_VCPU_INT_EN_BASE_IDX 1 1290 #define regUVD_ENC_VCPU_INT_STATUS 0x009f 1291 #define regUVD_ENC_VCPU_INT_STATUS_BASE_IDX 1 1292 #define regUVD_ENC_VCPU_INT_ACK 0x00a0 1293 #define regUVD_ENC_VCPU_INT_ACK_BASE_IDX 1 1294 #define regUVD_MASTINT_EN 0x00a1 1295 #define regUVD_MASTINT_EN_BASE_IDX 1 1296 #define regUVD_SYS_INT_EN 0x00a2 1297 #define regUVD_SYS_INT_EN_BASE_IDX 1 1298 #define regUVD_SYS_INT_STATUS 0x00a3 1299 #define regUVD_SYS_INT_STATUS_BASE_IDX 1 1300 #define regUVD_SYS_INT_ACK 0x00a4 1301 #define regUVD_SYS_INT_ACK_BASE_IDX 1 1302 #define regUVD_JOB_DONE 0x00a5 1303 #define regUVD_JOB_DONE_BASE_IDX 1 1304 #define regUVD_CBUF_ID 0x00a6 1305 #define regUVD_CBUF_ID_BASE_IDX 1 1306 #define regUVD_CONTEXT_ID 0x00a7 1307 #define regUVD_CONTEXT_ID_BASE_IDX 1 1308 #define regUVD_CONTEXT_ID2 0x00a8 1309 #define regUVD_CONTEXT_ID2_BASE_IDX 1 1310 #define regUVD_NO_OP 0x00a9 1311 #define regUVD_NO_OP_BASE_IDX 1 1312 #define regUVD_RB_BASE_LO 0x00aa 1313 #define regUVD_RB_BASE_LO_BASE_IDX 1 1314 #define regUVD_RB_BASE_HI 0x00ab 1315 #define regUVD_RB_BASE_HI_BASE_IDX 1 1316 #define regUVD_RB_SIZE 0x00ac 1317 #define regUVD_RB_SIZE_BASE_IDX 1 1318 #define regUVD_RB_RPTR 0x00ad 1319 #define regUVD_RB_RPTR_BASE_IDX 1 1320 #define regUVD_RB_WPTR 0x00ae 1321 #define regUVD_RB_WPTR_BASE_IDX 1 1322 #define regUVD_RB_BASE_LO2 0x00af 1323 #define regUVD_RB_BASE_LO2_BASE_IDX 1 1324 #define regUVD_RB_BASE_HI2 0x00b0 1325 #define regUVD_RB_BASE_HI2_BASE_IDX 1 1326 #define regUVD_RB_SIZE2 0x00b1 1327 #define regUVD_RB_SIZE2_BASE_IDX 1 1328 #define regUVD_RB_RPTR2 0x00b2 1329 #define regUVD_RB_RPTR2_BASE_IDX 1 1330 #define regUVD_RB_WPTR2 0x00b3 1331 #define regUVD_RB_WPTR2_BASE_IDX 1 1332 #define regUVD_RB_BASE_LO3 0x00b4 1333 #define regUVD_RB_BASE_LO3_BASE_IDX 1 1334 #define regUVD_RB_BASE_HI3 0x00b5 1335 #define regUVD_RB_BASE_HI3_BASE_IDX 1 1336 #define regUVD_RB_SIZE3 0x00b6 1337 #define regUVD_RB_SIZE3_BASE_IDX 1 1338 #define regUVD_RB_RPTR3 0x00b7 1339 #define regUVD_RB_RPTR3_BASE_IDX 1 1340 #define regUVD_RB_WPTR3 0x00b8 1341 #define regUVD_RB_WPTR3_BASE_IDX 1 1342 #define regUVD_RB_BASE_LO4 0x00b9 1343 #define regUVD_RB_BASE_LO4_BASE_IDX 1 1344 #define regUVD_RB_BASE_HI4 0x00ba 1345 #define regUVD_RB_BASE_HI4_BASE_IDX 1 1346 #define regUVD_RB_SIZE4 0x00bb 1347 #define regUVD_RB_SIZE4_BASE_IDX 1 1348 #define regUVD_RB_RPTR4 0x00bc 1349 #define regUVD_RB_RPTR4_BASE_IDX 1 1350 #define regUVD_RB_WPTR4 0x00bd 1351 #define regUVD_RB_WPTR4_BASE_IDX 1 1352 #define regUVD_OUT_RB_BASE_LO 0x00be 1353 #define regUVD_OUT_RB_BASE_LO_BASE_IDX 1 1354 #define regUVD_OUT_RB_BASE_HI 0x00bf 1355 #define regUVD_OUT_RB_BASE_HI_BASE_IDX 1 1356 #define regUVD_OUT_RB_SIZE 0x00c0 1357 #define regUVD_OUT_RB_SIZE_BASE_IDX 1 1358 #define regUVD_OUT_RB_RPTR 0x00c1 1359 #define regUVD_OUT_RB_RPTR_BASE_IDX 1 1360 #define regUVD_OUT_RB_WPTR 0x00c2 1361 #define regUVD_OUT_RB_WPTR_BASE_IDX 1 1362 #define regUVD_IOV_MAILBOX 0x00c4 1363 #define regUVD_IOV_MAILBOX_BASE_IDX 1 1364 #define regUVD_IOV_MAILBOX_RESP 0x00c5 1365 #define regUVD_IOV_MAILBOX_RESP_BASE_IDX 1 1366 #define regUVD_RB_ARB_CTRL 0x00c6 1367 #define regUVD_RB_ARB_CTRL_BASE_IDX 1 1368 #define regUVD_CTX_INDEX 0x00c7 1369 #define regUVD_CTX_INDEX_BASE_IDX 1 1370 #define regUVD_CTX_DATA 0x00c8 1371 #define regUVD_CTX_DATA_BASE_IDX 1 1372 #define regUVD_CXW_WR 0x00c9 1373 #define regUVD_CXW_WR_BASE_IDX 1 1374 #define regUVD_CXW_WR_INT_ID 0x00ca 1375 #define regUVD_CXW_WR_INT_ID_BASE_IDX 1 1376 #define regUVD_CXW_WR_INT_CTX_ID 0x00cb 1377 #define regUVD_CXW_WR_INT_CTX_ID_BASE_IDX 1 1378 #define regUVD_CXW_INT_ID 0x00cc 1379 #define regUVD_CXW_INT_ID_BASE_IDX 1 1380 #define regUVD_MPEG2_ERROR 0x00cd 1381 #define regUVD_MPEG2_ERROR_BASE_IDX 1 1382 #define regUVD_TOP_CTRL 0x00cf 1383 #define regUVD_TOP_CTRL_BASE_IDX 1 1384 #define regUVD_YBASE 0x00d0 1385 #define regUVD_YBASE_BASE_IDX 1 1386 #define regUVD_UVBASE 0x00d1 1387 #define regUVD_UVBASE_BASE_IDX 1 1388 #define regUVD_PITCH 0x00d2 1389 #define regUVD_PITCH_BASE_IDX 1 1390 #define regUVD_WIDTH 0x00d3 1391 #define regUVD_WIDTH_BASE_IDX 1 1392 #define regUVD_HEIGHT 0x00d4 1393 #define regUVD_HEIGHT_BASE_IDX 1 1394 #define regUVD_PICCOUNT 0x00d5 1395 #define regUVD_PICCOUNT_BASE_IDX 1 1396 #define regUVD_MPRD_INITIAL_XY 0x00d6 1397 #define regUVD_MPRD_INITIAL_XY_BASE_IDX 1 1398 #define regUVD_MPEG2_CTRL 0x00d7 1399 #define regUVD_MPEG2_CTRL_BASE_IDX 1 1400 #define regUVD_MB_CTL_BUF_BASE 0x00d8 1401 #define regUVD_MB_CTL_BUF_BASE_BASE_IDX 1 1402 #define regUVD_PIC_CTL_BUF_BASE 0x00d9 1403 #define regUVD_PIC_CTL_BUF_BASE_BASE_IDX 1 1404 #define regUVD_DXVA_BUF_SIZE 0x00da 1405 #define regUVD_DXVA_BUF_SIZE_BASE_IDX 1 1406 #define regUVD_SCRATCH_NP 0x00db 1407 #define regUVD_SCRATCH_NP_BASE_IDX 1 1408 #define regUVD_CLK_SWT_HANDSHAKE 0x00dc 1409 #define regUVD_CLK_SWT_HANDSHAKE_BASE_IDX 1 1410 #define regUVD_VERSION 0x00dd 1411 #define regUVD_VERSION_BASE_IDX 1 1412 #define regUVD_GP_SCRATCH0 0x00de 1413 #define regUVD_GP_SCRATCH0_BASE_IDX 1 1414 #define regUVD_GP_SCRATCH1 0x00df 1415 #define regUVD_GP_SCRATCH1_BASE_IDX 1 1416 #define regUVD_GP_SCRATCH2 0x00e0 1417 #define regUVD_GP_SCRATCH2_BASE_IDX 1 1418 #define regUVD_GP_SCRATCH3 0x00e1 1419 #define regUVD_GP_SCRATCH3_BASE_IDX 1 1420 #define regUVD_GP_SCRATCH4 0x00e2 1421 #define regUVD_GP_SCRATCH4_BASE_IDX 1 1422 #define regUVD_GP_SCRATCH5 0x00e3 1423 #define regUVD_GP_SCRATCH5_BASE_IDX 1 1424 #define regUVD_GP_SCRATCH6 0x00e4 1425 #define regUVD_GP_SCRATCH6_BASE_IDX 1 1426 #define regUVD_GP_SCRATCH7 0x00e5 1427 #define regUVD_GP_SCRATCH7_BASE_IDX 1 1428 #define regUVD_GP_SCRATCH8 0x00e6 1429 #define regUVD_GP_SCRATCH8_BASE_IDX 1 1430 #define regUVD_GP_SCRATCH9 0x00e7 1431 #define regUVD_GP_SCRATCH9_BASE_IDX 1 1432 #define regUVD_GP_SCRATCH10 0x00e8 1433 #define regUVD_GP_SCRATCH10_BASE_IDX 1 1434 #define regUVD_GP_SCRATCH11 0x00e9 1435 #define regUVD_GP_SCRATCH11_BASE_IDX 1 1436 #define regUVD_GP_SCRATCH12 0x00ea 1437 #define regUVD_GP_SCRATCH12_BASE_IDX 1 1438 #define regUVD_GP_SCRATCH13 0x00eb 1439 #define regUVD_GP_SCRATCH13_BASE_IDX 1 1440 #define regUVD_GP_SCRATCH14 0x00ec 1441 #define regUVD_GP_SCRATCH14_BASE_IDX 1 1442 #define regUVD_GP_SCRATCH15 0x00ed 1443 #define regUVD_GP_SCRATCH15_BASE_IDX 1 1444 #define regUVD_GP_SCRATCH16 0x00ee 1445 #define regUVD_GP_SCRATCH16_BASE_IDX 1 1446 #define regUVD_GP_SCRATCH17 0x00ef 1447 #define regUVD_GP_SCRATCH17_BASE_IDX 1 1448 #define regUVD_GP_SCRATCH18 0x00f0 1449 #define regUVD_GP_SCRATCH18_BASE_IDX 1 1450 #define regUVD_GP_SCRATCH19 0x00f1 1451 #define regUVD_GP_SCRATCH19_BASE_IDX 1 1452 #define regUVD_GP_SCRATCH20 0x00f2 1453 #define regUVD_GP_SCRATCH20_BASE_IDX 1 1454 #define regUVD_GP_SCRATCH21 0x00f3 1455 #define regUVD_GP_SCRATCH21_BASE_IDX 1 1456 #define regUVD_GP_SCRATCH22 0x00f4 1457 #define regUVD_GP_SCRATCH22_BASE_IDX 1 1458 #define regUVD_GP_SCRATCH23 0x00f5 1459 #define regUVD_GP_SCRATCH23_BASE_IDX 1 1460 1461 1462 #endif 1463