Home
last modified time | relevance | path

Searched refs:regSMU_INTERRUPT_CONTROL_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h820 #define regSMU_INTERRUPT_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h1793 #define regSMU_INTERRUPT_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h407 #define regSMU_INTERRUPT_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h407 #define regSMU_INTERRUPT_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h1024 #define regSMU_INTERRUPT_CONTROL_BASE_IDX … macro