1 /*
2  * Copyright 2021 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef _sdma_4_4_2_OFFSET_HEADER
24 #define _sdma_4_4_2_OFFSET_HEADER
25 
26 
27 
28 // addressBlock: aid_sdma_insts_sdma0_sdmadec
29 // base address: 0x4980
30 #define regSDMA_UCODE_ADDR                                                                              0x0000
31 #define regSDMA_UCODE_ADDR_BASE_IDX                                                                     0
32 #define regSDMA_UCODE_DATA                                                                              0x0001
33 #define regSDMA_UCODE_DATA_BASE_IDX                                                                     0
34 #define regSDMA_F32_CNTL                                                                                0x0002
35 #define regSDMA_F32_CNTL_BASE_IDX                                                                       0
36 #define regSDMA_MMHUB_CNTL                                                                              0x0005
37 #define regSDMA_MMHUB_CNTL_BASE_IDX                                                                     0
38 #define regSDMA_MMHUB_TRUSTLVL                                                                          0x0006
39 #define regSDMA_MMHUB_TRUSTLVL_BASE_IDX                                                                 0
40 #define regSDMA_VM_CNTL                                                                                 0x0010
41 #define regSDMA_VM_CNTL_BASE_IDX                                                                        0
42 #define regSDMA_VM_CTX_LO                                                                               0x0011
43 #define regSDMA_VM_CTX_LO_BASE_IDX                                                                      0
44 #define regSDMA_VM_CTX_HI                                                                               0x0012
45 #define regSDMA_VM_CTX_HI_BASE_IDX                                                                      0
46 #define regSDMA_ACTIVE_FCN_ID                                                                           0x0013
47 #define regSDMA_ACTIVE_FCN_ID_BASE_IDX                                                                  0
48 #define regSDMA_VM_CTX_CNTL                                                                             0x0014
49 #define regSDMA_VM_CTX_CNTL_BASE_IDX                                                                    0
50 #define regSDMA_VIRT_RESET_REQ                                                                          0x0015
51 #define regSDMA_VIRT_RESET_REQ_BASE_IDX                                                                 0
52 #define regSDMA_VF_ENABLE                                                                               0x0016
53 #define regSDMA_VF_ENABLE_BASE_IDX                                                                      0
54 #define regSDMA_CONTEXT_REG_TYPE0                                                                       0x0017
55 #define regSDMA_CONTEXT_REG_TYPE0_BASE_IDX                                                              0
56 #define regSDMA_CONTEXT_REG_TYPE1                                                                       0x0018
57 #define regSDMA_CONTEXT_REG_TYPE1_BASE_IDX                                                              0
58 #define regSDMA_CONTEXT_REG_TYPE2                                                                       0x0019
59 #define regSDMA_CONTEXT_REG_TYPE2_BASE_IDX                                                              0
60 #define regSDMA_CONTEXT_REG_TYPE3                                                                       0x001a
61 #define regSDMA_CONTEXT_REG_TYPE3_BASE_IDX                                                              0
62 #define regSDMA_PUB_REG_TYPE0                                                                           0x001b
63 #define regSDMA_PUB_REG_TYPE0_BASE_IDX                                                                  0
64 #define regSDMA_PUB_REG_TYPE1                                                                           0x001c
65 #define regSDMA_PUB_REG_TYPE1_BASE_IDX                                                                  0
66 #define regSDMA_PUB_REG_TYPE2                                                                           0x001d
67 #define regSDMA_PUB_REG_TYPE2_BASE_IDX                                                                  0
68 #define regSDMA_PUB_REG_TYPE3                                                                           0x001e
69 #define regSDMA_PUB_REG_TYPE3_BASE_IDX                                                                  0
70 #define regSDMA_CONTEXT_GROUP_BOUNDARY                                                                  0x001f
71 #define regSDMA_CONTEXT_GROUP_BOUNDARY_BASE_IDX                                                         0
72 #define regSDMA_RB_RPTR_FETCH_HI                                                                        0x0020
73 #define regSDMA_RB_RPTR_FETCH_HI_BASE_IDX                                                               0
74 #define regSDMA_SEM_WAIT_FAIL_TIMER_CNTL                                                                0x0021
75 #define regSDMA_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX                                                       0
76 #define regSDMA_RB_RPTR_FETCH                                                                           0x0022
77 #define regSDMA_RB_RPTR_FETCH_BASE_IDX                                                                  0
78 #define regSDMA_IB_OFFSET_FETCH                                                                         0x0023
79 #define regSDMA_IB_OFFSET_FETCH_BASE_IDX                                                                0
80 #define regSDMA_PROGRAM                                                                                 0x0024
81 #define regSDMA_PROGRAM_BASE_IDX                                                                        0
82 #define regSDMA_STATUS_REG                                                                              0x0025
83 #define regSDMA_STATUS_REG_BASE_IDX                                                                     0
84 #define regSDMA_STATUS1_REG                                                                             0x0026
85 #define regSDMA_STATUS1_REG_BASE_IDX                                                                    0
86 #define regSDMA_RD_BURST_CNTL                                                                           0x0027
87 #define regSDMA_RD_BURST_CNTL_BASE_IDX                                                                  0
88 #define regSDMA_HBM_PAGE_CONFIG                                                                         0x0028
89 #define regSDMA_HBM_PAGE_CONFIG_BASE_IDX                                                                0
90 #define regSDMA_UCODE_CHECKSUM                                                                          0x0029
91 #define regSDMA_UCODE_CHECKSUM_BASE_IDX                                                                 0
92 #define regSDMA_FREEZE                                                                                  0x002b
93 #define regSDMA_FREEZE_BASE_IDX                                                                         0
94 #define regSDMA_PHASE0_QUANTUM                                                                          0x002c
95 #define regSDMA_PHASE0_QUANTUM_BASE_IDX                                                                 0
96 #define regSDMA_PHASE1_QUANTUM                                                                          0x002d
97 #define regSDMA_PHASE1_QUANTUM_BASE_IDX                                                                 0
98 #define regSDMA_POWER_GATING                                                                            0x002e
99 #define regSDMA_POWER_GATING_BASE_IDX                                                                   0
100 #define regSDMA_PGFSM_CONFIG                                                                            0x002f
101 #define regSDMA_PGFSM_CONFIG_BASE_IDX                                                                   0
102 #define regSDMA_PGFSM_WRITE                                                                             0x0030
103 #define regSDMA_PGFSM_WRITE_BASE_IDX                                                                    0
104 #define regSDMA_PGFSM_READ                                                                              0x0031
105 #define regSDMA_PGFSM_READ_BASE_IDX                                                                     0
106 #define regCC_SDMA_EDC_CONFIG                                                                           0x0032
107 #define regCC_SDMA_EDC_CONFIG_BASE_IDX                                                                  0
108 #define regSDMA_BA_THRESHOLD                                                                            0x0033
109 #define regSDMA_BA_THRESHOLD_BASE_IDX                                                                   0
110 #define regSDMA_ID                                                                                      0x0034
111 #define regSDMA_ID_BASE_IDX                                                                             0
112 #define regSDMA_VERSION                                                                                 0x0035
113 #define regSDMA_VERSION_BASE_IDX                                                                        0
114 #define regSDMA_EDC_COUNTER                                                                             0x0036
115 #define regSDMA_EDC_COUNTER_BASE_IDX                                                                    0
116 #define regSDMA_EDC_COUNTER2                                                                            0x0037
117 #define regSDMA_EDC_COUNTER2_BASE_IDX                                                                   0
118 #define regSDMA_STATUS2_REG                                                                             0x0038
119 #define regSDMA_STATUS2_REG_BASE_IDX                                                                    0
120 #define regSDMA_ATOMIC_CNTL                                                                             0x0039
121 #define regSDMA_ATOMIC_CNTL_BASE_IDX                                                                    0
122 #define regSDMA_ATOMIC_PREOP_LO                                                                         0x003a
123 #define regSDMA_ATOMIC_PREOP_LO_BASE_IDX                                                                0
124 #define regSDMA_ATOMIC_PREOP_HI                                                                         0x003b
125 #define regSDMA_ATOMIC_PREOP_HI_BASE_IDX                                                                0
126 #define regSDMA_UTCL1_CNTL                                                                              0x003c
127 #define regSDMA_UTCL1_CNTL_BASE_IDX                                                                     0
128 #define regSDMA_UTCL1_WATERMK                                                                           0x003d
129 #define regSDMA_UTCL1_WATERMK_BASE_IDX                                                                  0
130 #define regSDMA_UTCL1_RD_STATUS                                                                         0x003e
131 #define regSDMA_UTCL1_RD_STATUS_BASE_IDX                                                                0
132 #define regSDMA_UTCL1_WR_STATUS                                                                         0x003f
133 #define regSDMA_UTCL1_WR_STATUS_BASE_IDX                                                                0
134 #define regSDMA_UTCL1_INV0                                                                              0x0040
135 #define regSDMA_UTCL1_INV0_BASE_IDX                                                                     0
136 #define regSDMA_UTCL1_INV1                                                                              0x0041
137 #define regSDMA_UTCL1_INV1_BASE_IDX                                                                     0
138 #define regSDMA_UTCL1_INV2                                                                              0x0042
139 #define regSDMA_UTCL1_INV2_BASE_IDX                                                                     0
140 #define regSDMA_UTCL1_RD_XNACK0                                                                         0x0043
141 #define regSDMA_UTCL1_RD_XNACK0_BASE_IDX                                                                0
142 #define regSDMA_UTCL1_RD_XNACK1                                                                         0x0044
143 #define regSDMA_UTCL1_RD_XNACK1_BASE_IDX                                                                0
144 #define regSDMA_UTCL1_WR_XNACK0                                                                         0x0045
145 #define regSDMA_UTCL1_WR_XNACK0_BASE_IDX                                                                0
146 #define regSDMA_UTCL1_WR_XNACK1                                                                         0x0046
147 #define regSDMA_UTCL1_WR_XNACK1_BASE_IDX                                                                0
148 #define regSDMA_UTCL1_TIMEOUT                                                                           0x0047
149 #define regSDMA_UTCL1_TIMEOUT_BASE_IDX                                                                  0
150 #define regSDMA_UTCL1_PAGE                                                                              0x0048
151 #define regSDMA_UTCL1_PAGE_BASE_IDX                                                                     0
152 #define regSDMA_POWER_CNTL_IDLE                                                                         0x0049
153 #define regSDMA_POWER_CNTL_IDLE_BASE_IDX                                                                0
154 #define regSDMA_RELAX_ORDERING_LUT                                                                      0x004a
155 #define regSDMA_RELAX_ORDERING_LUT_BASE_IDX                                                             0
156 #define regSDMA_CHICKEN_BITS_2                                                                          0x004b
157 #define regSDMA_CHICKEN_BITS_2_BASE_IDX                                                                 0
158 #define regSDMA_STATUS3_REG                                                                             0x004c
159 #define regSDMA_STATUS3_REG_BASE_IDX                                                                    0
160 #define regSDMA_PHYSICAL_ADDR_LO                                                                        0x004d
161 #define regSDMA_PHYSICAL_ADDR_LO_BASE_IDX                                                               0
162 #define regSDMA_PHYSICAL_ADDR_HI                                                                        0x004e
163 #define regSDMA_PHYSICAL_ADDR_HI_BASE_IDX                                                               0
164 #define regSDMA_PHASE2_QUANTUM                                                                          0x004f
165 #define regSDMA_PHASE2_QUANTUM_BASE_IDX                                                                 0
166 #define regSDMA_ERROR_LOG                                                                               0x0050
167 #define regSDMA_ERROR_LOG_BASE_IDX                                                                      0
168 #define regSDMA_PUB_DUMMY_REG0                                                                          0x0051
169 #define regSDMA_PUB_DUMMY_REG0_BASE_IDX                                                                 0
170 #define regSDMA_PUB_DUMMY_REG1                                                                          0x0052
171 #define regSDMA_PUB_DUMMY_REG1_BASE_IDX                                                                 0
172 #define regSDMA_PUB_DUMMY_REG2                                                                          0x0053
173 #define regSDMA_PUB_DUMMY_REG2_BASE_IDX                                                                 0
174 #define regSDMA_PUB_DUMMY_REG3                                                                          0x0054
175 #define regSDMA_PUB_DUMMY_REG3_BASE_IDX                                                                 0
176 #define regSDMA_F32_COUNTER                                                                             0x0055
177 #define regSDMA_F32_COUNTER_BASE_IDX                                                                    0
178 #define regSDMA_PERFCNT_PERFCOUNTER0_CFG                                                                0x0057
179 #define regSDMA_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX                                                       0
180 #define regSDMA_PERFCNT_PERFCOUNTER1_CFG                                                                0x0058
181 #define regSDMA_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX                                                       0
182 #define regSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL                                                           0x0059
183 #define regSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                  0
184 #define regSDMA_PERFCNT_MISC_CNTL                                                                       0x005a
185 #define regSDMA_PERFCNT_MISC_CNTL_BASE_IDX                                                              0
186 #define regSDMA_PERFCNT_PERFCOUNTER_LO                                                                  0x005b
187 #define regSDMA_PERFCNT_PERFCOUNTER_LO_BASE_IDX                                                         0
188 #define regSDMA_PERFCNT_PERFCOUNTER_HI                                                                  0x005c
189 #define regSDMA_PERFCNT_PERFCOUNTER_HI_BASE_IDX                                                         0
190 #define regSDMA_CRD_CNTL                                                                                0x005d
191 #define regSDMA_CRD_CNTL_BASE_IDX                                                                       0
192 #define regSDMA_GPU_IOV_VIOLATION_LOG                                                                   0x005e
193 #define regSDMA_GPU_IOV_VIOLATION_LOG_BASE_IDX                                                          0
194 #define regSDMA_ULV_CNTL                                                                                0x005f
195 #define regSDMA_ULV_CNTL_BASE_IDX                                                                       0
196 #define regSDMA_EA_DBIT_ADDR_DATA                                                                       0x0060
197 #define regSDMA_EA_DBIT_ADDR_DATA_BASE_IDX                                                              0
198 #define regSDMA_EA_DBIT_ADDR_INDEX                                                                      0x0061
199 #define regSDMA_EA_DBIT_ADDR_INDEX_BASE_IDX                                                             0
200 #define regSDMA_GPU_IOV_VIOLATION_LOG2                                                                  0x0062
201 #define regSDMA_GPU_IOV_VIOLATION_LOG2_BASE_IDX                                                         0
202 #define regSDMA_STATUS4_REG                                                                             0x0063
203 #define regSDMA_STATUS4_REG_BASE_IDX                                                                    0
204 #define regSDMA_SCRATCH_RAM_DATA                                                                        0x0064
205 #define regSDMA_SCRATCH_RAM_DATA_BASE_IDX                                                               0
206 #define regSDMA_SCRATCH_RAM_ADDR                                                                        0x0065
207 #define regSDMA_SCRATCH_RAM_ADDR_BASE_IDX                                                               0
208 #define regSDMA_CE_CTRL                                                                                 0x0066
209 #define regSDMA_CE_CTRL_BASE_IDX                                                                        0
210 #define regSDMA_RAS_STATUS                                                                              0x0067
211 #define regSDMA_RAS_STATUS_BASE_IDX                                                                     0
212 #define regSDMA_CLK_STATUS                                                                              0x0068
213 #define regSDMA_CLK_STATUS_BASE_IDX                                                                     0
214 #define regSDMA_UE_ERR_STATUS_LO                                                                        0x0069
215 #define regSDMA_UE_ERR_STATUS_LO_BASE_IDX                                                               0
216 #define regSDMA_UE_ERR_STATUS_HI                                                                        0x006a
217 #define regSDMA_UE_ERR_STATUS_HI_BASE_IDX                                                               0
218 #define regSDMA_POWER_CNTL                                                                              0x006b
219 #define regSDMA_POWER_CNTL_BASE_IDX                                                                     0
220 #define regSDMA_CLK_CTRL                                                                                0x006c
221 #define regSDMA_CLK_CTRL_BASE_IDX                                                                       0
222 #define regSDMA_CNTL                                                                                    0x006d
223 #define regSDMA_CNTL_BASE_IDX                                                                           0
224 #define regSDMA_CHICKEN_BITS                                                                            0x006e
225 #define regSDMA_CHICKEN_BITS_BASE_IDX                                                                   0
226 #define regSDMA_GB_ADDR_CONFIG                                                                          0x006f
227 #define regSDMA_GB_ADDR_CONFIG_BASE_IDX                                                                 0
228 #define regSDMA_GB_ADDR_CONFIG_READ                                                                     0x0070
229 #define regSDMA_GB_ADDR_CONFIG_READ_BASE_IDX                                                            0
230 #define regSDMA_GFX_RB_CNTL                                                                             0x0080
231 #define regSDMA_GFX_RB_CNTL_BASE_IDX                                                                    0
232 #define regSDMA_GFX_RB_BASE                                                                             0x0081
233 #define regSDMA_GFX_RB_BASE_BASE_IDX                                                                    0
234 #define regSDMA_GFX_RB_BASE_HI                                                                          0x0082
235 #define regSDMA_GFX_RB_BASE_HI_BASE_IDX                                                                 0
236 #define regSDMA_GFX_RB_RPTR                                                                             0x0083
237 #define regSDMA_GFX_RB_RPTR_BASE_IDX                                                                    0
238 #define regSDMA_GFX_RB_RPTR_HI                                                                          0x0084
239 #define regSDMA_GFX_RB_RPTR_HI_BASE_IDX                                                                 0
240 #define regSDMA_GFX_RB_WPTR                                                                             0x0085
241 #define regSDMA_GFX_RB_WPTR_BASE_IDX                                                                    0
242 #define regSDMA_GFX_RB_WPTR_HI                                                                          0x0086
243 #define regSDMA_GFX_RB_WPTR_HI_BASE_IDX                                                                 0
244 #define regSDMA_GFX_RB_WPTR_POLL_CNTL                                                                   0x0087
245 #define regSDMA_GFX_RB_WPTR_POLL_CNTL_BASE_IDX                                                          0
246 #define regSDMA_GFX_RB_RPTR_ADDR_HI                                                                     0x0088
247 #define regSDMA_GFX_RB_RPTR_ADDR_HI_BASE_IDX                                                            0
248 #define regSDMA_GFX_RB_RPTR_ADDR_LO                                                                     0x0089
249 #define regSDMA_GFX_RB_RPTR_ADDR_LO_BASE_IDX                                                            0
250 #define regSDMA_GFX_IB_CNTL                                                                             0x008a
251 #define regSDMA_GFX_IB_CNTL_BASE_IDX                                                                    0
252 #define regSDMA_GFX_IB_RPTR                                                                             0x008b
253 #define regSDMA_GFX_IB_RPTR_BASE_IDX                                                                    0
254 #define regSDMA_GFX_IB_OFFSET                                                                           0x008c
255 #define regSDMA_GFX_IB_OFFSET_BASE_IDX                                                                  0
256 #define regSDMA_GFX_IB_BASE_LO                                                                          0x008d
257 #define regSDMA_GFX_IB_BASE_LO_BASE_IDX                                                                 0
258 #define regSDMA_GFX_IB_BASE_HI                                                                          0x008e
259 #define regSDMA_GFX_IB_BASE_HI_BASE_IDX                                                                 0
260 #define regSDMA_GFX_IB_SIZE                                                                             0x008f
261 #define regSDMA_GFX_IB_SIZE_BASE_IDX                                                                    0
262 #define regSDMA_GFX_SKIP_CNTL                                                                           0x0090
263 #define regSDMA_GFX_SKIP_CNTL_BASE_IDX                                                                  0
264 #define regSDMA_GFX_CONTEXT_STATUS                                                                      0x0091
265 #define regSDMA_GFX_CONTEXT_STATUS_BASE_IDX                                                             0
266 #define regSDMA_GFX_DOORBELL                                                                            0x0092
267 #define regSDMA_GFX_DOORBELL_BASE_IDX                                                                   0
268 #define regSDMA_GFX_CONTEXT_CNTL                                                                        0x0093
269 #define regSDMA_GFX_CONTEXT_CNTL_BASE_IDX                                                               0
270 #define regSDMA_GFX_STATUS                                                                              0x00a8
271 #define regSDMA_GFX_STATUS_BASE_IDX                                                                     0
272 #define regSDMA_GFX_DOORBELL_LOG                                                                        0x00a9
273 #define regSDMA_GFX_DOORBELL_LOG_BASE_IDX                                                               0
274 #define regSDMA_GFX_WATERMARK                                                                           0x00aa
275 #define regSDMA_GFX_WATERMARK_BASE_IDX                                                                  0
276 #define regSDMA_GFX_DOORBELL_OFFSET                                                                     0x00ab
277 #define regSDMA_GFX_DOORBELL_OFFSET_BASE_IDX                                                            0
278 #define regSDMA_GFX_CSA_ADDR_LO                                                                         0x00ac
279 #define regSDMA_GFX_CSA_ADDR_LO_BASE_IDX                                                                0
280 #define regSDMA_GFX_CSA_ADDR_HI                                                                         0x00ad
281 #define regSDMA_GFX_CSA_ADDR_HI_BASE_IDX                                                                0
282 #define regSDMA_GFX_IB_SUB_REMAIN                                                                       0x00af
283 #define regSDMA_GFX_IB_SUB_REMAIN_BASE_IDX                                                              0
284 #define regSDMA_GFX_PREEMPT                                                                             0x00b0
285 #define regSDMA_GFX_PREEMPT_BASE_IDX                                                                    0
286 #define regSDMA_GFX_DUMMY_REG                                                                           0x00b1
287 #define regSDMA_GFX_DUMMY_REG_BASE_IDX                                                                  0
288 #define regSDMA_GFX_RB_WPTR_POLL_ADDR_HI                                                                0x00b2
289 #define regSDMA_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                       0
290 #define regSDMA_GFX_RB_WPTR_POLL_ADDR_LO                                                                0x00b3
291 #define regSDMA_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                       0
292 #define regSDMA_GFX_RB_AQL_CNTL                                                                         0x00b4
293 #define regSDMA_GFX_RB_AQL_CNTL_BASE_IDX                                                                0
294 #define regSDMA_GFX_MINOR_PTR_UPDATE                                                                    0x00b5
295 #define regSDMA_GFX_MINOR_PTR_UPDATE_BASE_IDX                                                           0
296 #define regSDMA_GFX_MIDCMD_DATA0                                                                        0x00c0
297 #define regSDMA_GFX_MIDCMD_DATA0_BASE_IDX                                                               0
298 #define regSDMA_GFX_MIDCMD_DATA1                                                                        0x00c1
299 #define regSDMA_GFX_MIDCMD_DATA1_BASE_IDX                                                               0
300 #define regSDMA_GFX_MIDCMD_DATA2                                                                        0x00c2
301 #define regSDMA_GFX_MIDCMD_DATA2_BASE_IDX                                                               0
302 #define regSDMA_GFX_MIDCMD_DATA3                                                                        0x00c3
303 #define regSDMA_GFX_MIDCMD_DATA3_BASE_IDX                                                               0
304 #define regSDMA_GFX_MIDCMD_DATA4                                                                        0x00c4
305 #define regSDMA_GFX_MIDCMD_DATA4_BASE_IDX                                                               0
306 #define regSDMA_GFX_MIDCMD_DATA5                                                                        0x00c5
307 #define regSDMA_GFX_MIDCMD_DATA5_BASE_IDX                                                               0
308 #define regSDMA_GFX_MIDCMD_DATA6                                                                        0x00c6
309 #define regSDMA_GFX_MIDCMD_DATA6_BASE_IDX                                                               0
310 #define regSDMA_GFX_MIDCMD_DATA7                                                                        0x00c7
311 #define regSDMA_GFX_MIDCMD_DATA7_BASE_IDX                                                               0
312 #define regSDMA_GFX_MIDCMD_DATA8                                                                        0x00c8
313 #define regSDMA_GFX_MIDCMD_DATA8_BASE_IDX                                                               0
314 #define regSDMA_GFX_MIDCMD_DATA9                                                                        0x00c9
315 #define regSDMA_GFX_MIDCMD_DATA9_BASE_IDX                                                               0
316 #define regSDMA_GFX_MIDCMD_DATA10                                                                       0x00ca
317 #define regSDMA_GFX_MIDCMD_DATA10_BASE_IDX                                                              0
318 #define regSDMA_GFX_MIDCMD_CNTL                                                                         0x00cb
319 #define regSDMA_GFX_MIDCMD_CNTL_BASE_IDX                                                                0
320 #define regSDMA_PAGE_RB_CNTL                                                                            0x00d8
321 #define regSDMA_PAGE_RB_CNTL_BASE_IDX                                                                   0
322 #define regSDMA_PAGE_RB_BASE                                                                            0x00d9
323 #define regSDMA_PAGE_RB_BASE_BASE_IDX                                                                   0
324 #define regSDMA_PAGE_RB_BASE_HI                                                                         0x00da
325 #define regSDMA_PAGE_RB_BASE_HI_BASE_IDX                                                                0
326 #define regSDMA_PAGE_RB_RPTR                                                                            0x00db
327 #define regSDMA_PAGE_RB_RPTR_BASE_IDX                                                                   0
328 #define regSDMA_PAGE_RB_RPTR_HI                                                                         0x00dc
329 #define regSDMA_PAGE_RB_RPTR_HI_BASE_IDX                                                                0
330 #define regSDMA_PAGE_RB_WPTR                                                                            0x00dd
331 #define regSDMA_PAGE_RB_WPTR_BASE_IDX                                                                   0
332 #define regSDMA_PAGE_RB_WPTR_HI                                                                         0x00de
333 #define regSDMA_PAGE_RB_WPTR_HI_BASE_IDX                                                                0
334 #define regSDMA_PAGE_RB_WPTR_POLL_CNTL                                                                  0x00df
335 #define regSDMA_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX                                                         0
336 #define regSDMA_PAGE_RB_RPTR_ADDR_HI                                                                    0x00e0
337 #define regSDMA_PAGE_RB_RPTR_ADDR_HI_BASE_IDX                                                           0
338 #define regSDMA_PAGE_RB_RPTR_ADDR_LO                                                                    0x00e1
339 #define regSDMA_PAGE_RB_RPTR_ADDR_LO_BASE_IDX                                                           0
340 #define regSDMA_PAGE_IB_CNTL                                                                            0x00e2
341 #define regSDMA_PAGE_IB_CNTL_BASE_IDX                                                                   0
342 #define regSDMA_PAGE_IB_RPTR                                                                            0x00e3
343 #define regSDMA_PAGE_IB_RPTR_BASE_IDX                                                                   0
344 #define regSDMA_PAGE_IB_OFFSET                                                                          0x00e4
345 #define regSDMA_PAGE_IB_OFFSET_BASE_IDX                                                                 0
346 #define regSDMA_PAGE_IB_BASE_LO                                                                         0x00e5
347 #define regSDMA_PAGE_IB_BASE_LO_BASE_IDX                                                                0
348 #define regSDMA_PAGE_IB_BASE_HI                                                                         0x00e6
349 #define regSDMA_PAGE_IB_BASE_HI_BASE_IDX                                                                0
350 #define regSDMA_PAGE_IB_SIZE                                                                            0x00e7
351 #define regSDMA_PAGE_IB_SIZE_BASE_IDX                                                                   0
352 #define regSDMA_PAGE_SKIP_CNTL                                                                          0x00e8
353 #define regSDMA_PAGE_SKIP_CNTL_BASE_IDX                                                                 0
354 #define regSDMA_PAGE_CONTEXT_STATUS                                                                     0x00e9
355 #define regSDMA_PAGE_CONTEXT_STATUS_BASE_IDX                                                            0
356 #define regSDMA_PAGE_DOORBELL                                                                           0x00ea
357 #define regSDMA_PAGE_DOORBELL_BASE_IDX                                                                  0
358 #define regSDMA_PAGE_STATUS                                                                             0x0100
359 #define regSDMA_PAGE_STATUS_BASE_IDX                                                                    0
360 #define regSDMA_PAGE_DOORBELL_LOG                                                                       0x0101
361 #define regSDMA_PAGE_DOORBELL_LOG_BASE_IDX                                                              0
362 #define regSDMA_PAGE_WATERMARK                                                                          0x0102
363 #define regSDMA_PAGE_WATERMARK_BASE_IDX                                                                 0
364 #define regSDMA_PAGE_DOORBELL_OFFSET                                                                    0x0103
365 #define regSDMA_PAGE_DOORBELL_OFFSET_BASE_IDX                                                           0
366 #define regSDMA_PAGE_CSA_ADDR_LO                                                                        0x0104
367 #define regSDMA_PAGE_CSA_ADDR_LO_BASE_IDX                                                               0
368 #define regSDMA_PAGE_CSA_ADDR_HI                                                                        0x0105
369 #define regSDMA_PAGE_CSA_ADDR_HI_BASE_IDX                                                               0
370 #define regSDMA_PAGE_IB_SUB_REMAIN                                                                      0x0107
371 #define regSDMA_PAGE_IB_SUB_REMAIN_BASE_IDX                                                             0
372 #define regSDMA_PAGE_PREEMPT                                                                            0x0108
373 #define regSDMA_PAGE_PREEMPT_BASE_IDX                                                                   0
374 #define regSDMA_PAGE_DUMMY_REG                                                                          0x0109
375 #define regSDMA_PAGE_DUMMY_REG_BASE_IDX                                                                 0
376 #define regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI                                                               0x010a
377 #define regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                      0
378 #define regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO                                                               0x010b
379 #define regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                      0
380 #define regSDMA_PAGE_RB_AQL_CNTL                                                                        0x010c
381 #define regSDMA_PAGE_RB_AQL_CNTL_BASE_IDX                                                               0
382 #define regSDMA_PAGE_MINOR_PTR_UPDATE                                                                   0x010d
383 #define regSDMA_PAGE_MINOR_PTR_UPDATE_BASE_IDX                                                          0
384 #define regSDMA_PAGE_MIDCMD_DATA0                                                                       0x0118
385 #define regSDMA_PAGE_MIDCMD_DATA0_BASE_IDX                                                              0
386 #define regSDMA_PAGE_MIDCMD_DATA1                                                                       0x0119
387 #define regSDMA_PAGE_MIDCMD_DATA1_BASE_IDX                                                              0
388 #define regSDMA_PAGE_MIDCMD_DATA2                                                                       0x011a
389 #define regSDMA_PAGE_MIDCMD_DATA2_BASE_IDX                                                              0
390 #define regSDMA_PAGE_MIDCMD_DATA3                                                                       0x011b
391 #define regSDMA_PAGE_MIDCMD_DATA3_BASE_IDX                                                              0
392 #define regSDMA_PAGE_MIDCMD_DATA4                                                                       0x011c
393 #define regSDMA_PAGE_MIDCMD_DATA4_BASE_IDX                                                              0
394 #define regSDMA_PAGE_MIDCMD_DATA5                                                                       0x011d
395 #define regSDMA_PAGE_MIDCMD_DATA5_BASE_IDX                                                              0
396 #define regSDMA_PAGE_MIDCMD_DATA6                                                                       0x011e
397 #define regSDMA_PAGE_MIDCMD_DATA6_BASE_IDX                                                              0
398 #define regSDMA_PAGE_MIDCMD_DATA7                                                                       0x011f
399 #define regSDMA_PAGE_MIDCMD_DATA7_BASE_IDX                                                              0
400 #define regSDMA_PAGE_MIDCMD_DATA8                                                                       0x0120
401 #define regSDMA_PAGE_MIDCMD_DATA8_BASE_IDX                                                              0
402 #define regSDMA_PAGE_MIDCMD_DATA9                                                                       0x0121
403 #define regSDMA_PAGE_MIDCMD_DATA9_BASE_IDX                                                              0
404 #define regSDMA_PAGE_MIDCMD_DATA10                                                                      0x0122
405 #define regSDMA_PAGE_MIDCMD_DATA10_BASE_IDX                                                             0
406 #define regSDMA_PAGE_MIDCMD_CNTL                                                                        0x0123
407 #define regSDMA_PAGE_MIDCMD_CNTL_BASE_IDX                                                               0
408 #define regSDMA_RLC0_RB_CNTL                                                                            0x0130
409 #define regSDMA_RLC0_RB_CNTL_BASE_IDX                                                                   0
410 #define regSDMA_RLC0_RB_BASE                                                                            0x0131
411 #define regSDMA_RLC0_RB_BASE_BASE_IDX                                                                   0
412 #define regSDMA_RLC0_RB_BASE_HI                                                                         0x0132
413 #define regSDMA_RLC0_RB_BASE_HI_BASE_IDX                                                                0
414 #define regSDMA_RLC0_RB_RPTR                                                                            0x0133
415 #define regSDMA_RLC0_RB_RPTR_BASE_IDX                                                                   0
416 #define regSDMA_RLC0_RB_RPTR_HI                                                                         0x0134
417 #define regSDMA_RLC0_RB_RPTR_HI_BASE_IDX                                                                0
418 #define regSDMA_RLC0_RB_WPTR                                                                            0x0135
419 #define regSDMA_RLC0_RB_WPTR_BASE_IDX                                                                   0
420 #define regSDMA_RLC0_RB_WPTR_HI                                                                         0x0136
421 #define regSDMA_RLC0_RB_WPTR_HI_BASE_IDX                                                                0
422 #define regSDMA_RLC0_RB_WPTR_POLL_CNTL                                                                  0x0137
423 #define regSDMA_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX                                                         0
424 #define regSDMA_RLC0_RB_RPTR_ADDR_HI                                                                    0x0138
425 #define regSDMA_RLC0_RB_RPTR_ADDR_HI_BASE_IDX                                                           0
426 #define regSDMA_RLC0_RB_RPTR_ADDR_LO                                                                    0x0139
427 #define regSDMA_RLC0_RB_RPTR_ADDR_LO_BASE_IDX                                                           0
428 #define regSDMA_RLC0_IB_CNTL                                                                            0x013a
429 #define regSDMA_RLC0_IB_CNTL_BASE_IDX                                                                   0
430 #define regSDMA_RLC0_IB_RPTR                                                                            0x013b
431 #define regSDMA_RLC0_IB_RPTR_BASE_IDX                                                                   0
432 #define regSDMA_RLC0_IB_OFFSET                                                                          0x013c
433 #define regSDMA_RLC0_IB_OFFSET_BASE_IDX                                                                 0
434 #define regSDMA_RLC0_IB_BASE_LO                                                                         0x013d
435 #define regSDMA_RLC0_IB_BASE_LO_BASE_IDX                                                                0
436 #define regSDMA_RLC0_IB_BASE_HI                                                                         0x013e
437 #define regSDMA_RLC0_IB_BASE_HI_BASE_IDX                                                                0
438 #define regSDMA_RLC0_IB_SIZE                                                                            0x013f
439 #define regSDMA_RLC0_IB_SIZE_BASE_IDX                                                                   0
440 #define regSDMA_RLC0_SKIP_CNTL                                                                          0x0140
441 #define regSDMA_RLC0_SKIP_CNTL_BASE_IDX                                                                 0
442 #define regSDMA_RLC0_CONTEXT_STATUS                                                                     0x0141
443 #define regSDMA_RLC0_CONTEXT_STATUS_BASE_IDX                                                            0
444 #define regSDMA_RLC0_DOORBELL                                                                           0x0142
445 #define regSDMA_RLC0_DOORBELL_BASE_IDX                                                                  0
446 #define regSDMA_RLC0_STATUS                                                                             0x0158
447 #define regSDMA_RLC0_STATUS_BASE_IDX                                                                    0
448 #define regSDMA_RLC0_DOORBELL_LOG                                                                       0x0159
449 #define regSDMA_RLC0_DOORBELL_LOG_BASE_IDX                                                              0
450 #define regSDMA_RLC0_WATERMARK                                                                          0x015a
451 #define regSDMA_RLC0_WATERMARK_BASE_IDX                                                                 0
452 #define regSDMA_RLC0_DOORBELL_OFFSET                                                                    0x015b
453 #define regSDMA_RLC0_DOORBELL_OFFSET_BASE_IDX                                                           0
454 #define regSDMA_RLC0_CSA_ADDR_LO                                                                        0x015c
455 #define regSDMA_RLC0_CSA_ADDR_LO_BASE_IDX                                                               0
456 #define regSDMA_RLC0_CSA_ADDR_HI                                                                        0x015d
457 #define regSDMA_RLC0_CSA_ADDR_HI_BASE_IDX                                                               0
458 #define regSDMA_RLC0_IB_SUB_REMAIN                                                                      0x015f
459 #define regSDMA_RLC0_IB_SUB_REMAIN_BASE_IDX                                                             0
460 #define regSDMA_RLC0_PREEMPT                                                                            0x0160
461 #define regSDMA_RLC0_PREEMPT_BASE_IDX                                                                   0
462 #define regSDMA_RLC0_DUMMY_REG                                                                          0x0161
463 #define regSDMA_RLC0_DUMMY_REG_BASE_IDX                                                                 0
464 #define regSDMA_RLC0_RB_WPTR_POLL_ADDR_HI                                                               0x0162
465 #define regSDMA_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                      0
466 #define regSDMA_RLC0_RB_WPTR_POLL_ADDR_LO                                                               0x0163
467 #define regSDMA_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                      0
468 #define regSDMA_RLC0_RB_AQL_CNTL                                                                        0x0164
469 #define regSDMA_RLC0_RB_AQL_CNTL_BASE_IDX                                                               0
470 #define regSDMA_RLC0_MINOR_PTR_UPDATE                                                                   0x0165
471 #define regSDMA_RLC0_MINOR_PTR_UPDATE_BASE_IDX                                                          0
472 #define regSDMA_RLC0_MIDCMD_DATA0                                                                       0x0170
473 #define regSDMA_RLC0_MIDCMD_DATA0_BASE_IDX                                                              0
474 #define regSDMA_RLC0_MIDCMD_DATA1                                                                       0x0171
475 #define regSDMA_RLC0_MIDCMD_DATA1_BASE_IDX                                                              0
476 #define regSDMA_RLC0_MIDCMD_DATA2                                                                       0x0172
477 #define regSDMA_RLC0_MIDCMD_DATA2_BASE_IDX                                                              0
478 #define regSDMA_RLC0_MIDCMD_DATA3                                                                       0x0173
479 #define regSDMA_RLC0_MIDCMD_DATA3_BASE_IDX                                                              0
480 #define regSDMA_RLC0_MIDCMD_DATA4                                                                       0x0174
481 #define regSDMA_RLC0_MIDCMD_DATA4_BASE_IDX                                                              0
482 #define regSDMA_RLC0_MIDCMD_DATA5                                                                       0x0175
483 #define regSDMA_RLC0_MIDCMD_DATA5_BASE_IDX                                                              0
484 #define regSDMA_RLC0_MIDCMD_DATA6                                                                       0x0176
485 #define regSDMA_RLC0_MIDCMD_DATA6_BASE_IDX                                                              0
486 #define regSDMA_RLC0_MIDCMD_DATA7                                                                       0x0177
487 #define regSDMA_RLC0_MIDCMD_DATA7_BASE_IDX                                                              0
488 #define regSDMA_RLC0_MIDCMD_DATA8                                                                       0x0178
489 #define regSDMA_RLC0_MIDCMD_DATA8_BASE_IDX                                                              0
490 #define regSDMA_RLC0_MIDCMD_DATA9                                                                       0x0179
491 #define regSDMA_RLC0_MIDCMD_DATA9_BASE_IDX                                                              0
492 #define regSDMA_RLC0_MIDCMD_DATA10                                                                      0x017a
493 #define regSDMA_RLC0_MIDCMD_DATA10_BASE_IDX                                                             0
494 #define regSDMA_RLC0_MIDCMD_CNTL                                                                        0x017b
495 #define regSDMA_RLC0_MIDCMD_CNTL_BASE_IDX                                                               0
496 #define regSDMA_RLC1_RB_CNTL                                                                            0x0188
497 #define regSDMA_RLC1_RB_CNTL_BASE_IDX                                                                   0
498 #define regSDMA_RLC1_RB_BASE                                                                            0x0189
499 #define regSDMA_RLC1_RB_BASE_BASE_IDX                                                                   0
500 #define regSDMA_RLC1_RB_BASE_HI                                                                         0x018a
501 #define regSDMA_RLC1_RB_BASE_HI_BASE_IDX                                                                0
502 #define regSDMA_RLC1_RB_RPTR                                                                            0x018b
503 #define regSDMA_RLC1_RB_RPTR_BASE_IDX                                                                   0
504 #define regSDMA_RLC1_RB_RPTR_HI                                                                         0x018c
505 #define regSDMA_RLC1_RB_RPTR_HI_BASE_IDX                                                                0
506 #define regSDMA_RLC1_RB_WPTR                                                                            0x018d
507 #define regSDMA_RLC1_RB_WPTR_BASE_IDX                                                                   0
508 #define regSDMA_RLC1_RB_WPTR_HI                                                                         0x018e
509 #define regSDMA_RLC1_RB_WPTR_HI_BASE_IDX                                                                0
510 #define regSDMA_RLC1_RB_WPTR_POLL_CNTL                                                                  0x018f
511 #define regSDMA_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX                                                         0
512 #define regSDMA_RLC1_RB_RPTR_ADDR_HI                                                                    0x0190
513 #define regSDMA_RLC1_RB_RPTR_ADDR_HI_BASE_IDX                                                           0
514 #define regSDMA_RLC1_RB_RPTR_ADDR_LO                                                                    0x0191
515 #define regSDMA_RLC1_RB_RPTR_ADDR_LO_BASE_IDX                                                           0
516 #define regSDMA_RLC1_IB_CNTL                                                                            0x0192
517 #define regSDMA_RLC1_IB_CNTL_BASE_IDX                                                                   0
518 #define regSDMA_RLC1_IB_RPTR                                                                            0x0193
519 #define regSDMA_RLC1_IB_RPTR_BASE_IDX                                                                   0
520 #define regSDMA_RLC1_IB_OFFSET                                                                          0x0194
521 #define regSDMA_RLC1_IB_OFFSET_BASE_IDX                                                                 0
522 #define regSDMA_RLC1_IB_BASE_LO                                                                         0x0195
523 #define regSDMA_RLC1_IB_BASE_LO_BASE_IDX                                                                0
524 #define regSDMA_RLC1_IB_BASE_HI                                                                         0x0196
525 #define regSDMA_RLC1_IB_BASE_HI_BASE_IDX                                                                0
526 #define regSDMA_RLC1_IB_SIZE                                                                            0x0197
527 #define regSDMA_RLC1_IB_SIZE_BASE_IDX                                                                   0
528 #define regSDMA_RLC1_SKIP_CNTL                                                                          0x0198
529 #define regSDMA_RLC1_SKIP_CNTL_BASE_IDX                                                                 0
530 #define regSDMA_RLC1_CONTEXT_STATUS                                                                     0x0199
531 #define regSDMA_RLC1_CONTEXT_STATUS_BASE_IDX                                                            0
532 #define regSDMA_RLC1_DOORBELL                                                                           0x019a
533 #define regSDMA_RLC1_DOORBELL_BASE_IDX                                                                  0
534 #define regSDMA_RLC1_STATUS                                                                             0x01b0
535 #define regSDMA_RLC1_STATUS_BASE_IDX                                                                    0
536 #define regSDMA_RLC1_DOORBELL_LOG                                                                       0x01b1
537 #define regSDMA_RLC1_DOORBELL_LOG_BASE_IDX                                                              0
538 #define regSDMA_RLC1_WATERMARK                                                                          0x01b2
539 #define regSDMA_RLC1_WATERMARK_BASE_IDX                                                                 0
540 #define regSDMA_RLC1_DOORBELL_OFFSET                                                                    0x01b3
541 #define regSDMA_RLC1_DOORBELL_OFFSET_BASE_IDX                                                           0
542 #define regSDMA_RLC1_CSA_ADDR_LO                                                                        0x01b4
543 #define regSDMA_RLC1_CSA_ADDR_LO_BASE_IDX                                                               0
544 #define regSDMA_RLC1_CSA_ADDR_HI                                                                        0x01b5
545 #define regSDMA_RLC1_CSA_ADDR_HI_BASE_IDX                                                               0
546 #define regSDMA_RLC1_IB_SUB_REMAIN                                                                      0x01b7
547 #define regSDMA_RLC1_IB_SUB_REMAIN_BASE_IDX                                                             0
548 #define regSDMA_RLC1_PREEMPT                                                                            0x01b8
549 #define regSDMA_RLC1_PREEMPT_BASE_IDX                                                                   0
550 #define regSDMA_RLC1_DUMMY_REG                                                                          0x01b9
551 #define regSDMA_RLC1_DUMMY_REG_BASE_IDX                                                                 0
552 #define regSDMA_RLC1_RB_WPTR_POLL_ADDR_HI                                                               0x01ba
553 #define regSDMA_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                      0
554 #define regSDMA_RLC1_RB_WPTR_POLL_ADDR_LO                                                               0x01bb
555 #define regSDMA_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                      0
556 #define regSDMA_RLC1_RB_AQL_CNTL                                                                        0x01bc
557 #define regSDMA_RLC1_RB_AQL_CNTL_BASE_IDX                                                               0
558 #define regSDMA_RLC1_MINOR_PTR_UPDATE                                                                   0x01bd
559 #define regSDMA_RLC1_MINOR_PTR_UPDATE_BASE_IDX                                                          0
560 #define regSDMA_RLC1_MIDCMD_DATA0                                                                       0x01c8
561 #define regSDMA_RLC1_MIDCMD_DATA0_BASE_IDX                                                              0
562 #define regSDMA_RLC1_MIDCMD_DATA1                                                                       0x01c9
563 #define regSDMA_RLC1_MIDCMD_DATA1_BASE_IDX                                                              0
564 #define regSDMA_RLC1_MIDCMD_DATA2                                                                       0x01ca
565 #define regSDMA_RLC1_MIDCMD_DATA2_BASE_IDX                                                              0
566 #define regSDMA_RLC1_MIDCMD_DATA3                                                                       0x01cb
567 #define regSDMA_RLC1_MIDCMD_DATA3_BASE_IDX                                                              0
568 #define regSDMA_RLC1_MIDCMD_DATA4                                                                       0x01cc
569 #define regSDMA_RLC1_MIDCMD_DATA4_BASE_IDX                                                              0
570 #define regSDMA_RLC1_MIDCMD_DATA5                                                                       0x01cd
571 #define regSDMA_RLC1_MIDCMD_DATA5_BASE_IDX                                                              0
572 #define regSDMA_RLC1_MIDCMD_DATA6                                                                       0x01ce
573 #define regSDMA_RLC1_MIDCMD_DATA6_BASE_IDX                                                              0
574 #define regSDMA_RLC1_MIDCMD_DATA7                                                                       0x01cf
575 #define regSDMA_RLC1_MIDCMD_DATA7_BASE_IDX                                                              0
576 #define regSDMA_RLC1_MIDCMD_DATA8                                                                       0x01d0
577 #define regSDMA_RLC1_MIDCMD_DATA8_BASE_IDX                                                              0
578 #define regSDMA_RLC1_MIDCMD_DATA9                                                                       0x01d1
579 #define regSDMA_RLC1_MIDCMD_DATA9_BASE_IDX                                                              0
580 #define regSDMA_RLC1_MIDCMD_DATA10                                                                      0x01d2
581 #define regSDMA_RLC1_MIDCMD_DATA10_BASE_IDX                                                             0
582 #define regSDMA_RLC1_MIDCMD_CNTL                                                                        0x01d3
583 #define regSDMA_RLC1_MIDCMD_CNTL_BASE_IDX                                                               0
584 #define regSDMA_RLC2_RB_CNTL                                                                            0x01e0
585 #define regSDMA_RLC2_RB_CNTL_BASE_IDX                                                                   0
586 #define regSDMA_RLC2_RB_BASE                                                                            0x01e1
587 #define regSDMA_RLC2_RB_BASE_BASE_IDX                                                                   0
588 #define regSDMA_RLC2_RB_BASE_HI                                                                         0x01e2
589 #define regSDMA_RLC2_RB_BASE_HI_BASE_IDX                                                                0
590 #define regSDMA_RLC2_RB_RPTR                                                                            0x01e3
591 #define regSDMA_RLC2_RB_RPTR_BASE_IDX                                                                   0
592 #define regSDMA_RLC2_RB_RPTR_HI                                                                         0x01e4
593 #define regSDMA_RLC2_RB_RPTR_HI_BASE_IDX                                                                0
594 #define regSDMA_RLC2_RB_WPTR                                                                            0x01e5
595 #define regSDMA_RLC2_RB_WPTR_BASE_IDX                                                                   0
596 #define regSDMA_RLC2_RB_WPTR_HI                                                                         0x01e6
597 #define regSDMA_RLC2_RB_WPTR_HI_BASE_IDX                                                                0
598 #define regSDMA_RLC2_RB_WPTR_POLL_CNTL                                                                  0x01e7
599 #define regSDMA_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX                                                         0
600 #define regSDMA_RLC2_RB_RPTR_ADDR_HI                                                                    0x01e8
601 #define regSDMA_RLC2_RB_RPTR_ADDR_HI_BASE_IDX                                                           0
602 #define regSDMA_RLC2_RB_RPTR_ADDR_LO                                                                    0x01e9
603 #define regSDMA_RLC2_RB_RPTR_ADDR_LO_BASE_IDX                                                           0
604 #define regSDMA_RLC2_IB_CNTL                                                                            0x01ea
605 #define regSDMA_RLC2_IB_CNTL_BASE_IDX                                                                   0
606 #define regSDMA_RLC2_IB_RPTR                                                                            0x01eb
607 #define regSDMA_RLC2_IB_RPTR_BASE_IDX                                                                   0
608 #define regSDMA_RLC2_IB_OFFSET                                                                          0x01ec
609 #define regSDMA_RLC2_IB_OFFSET_BASE_IDX                                                                 0
610 #define regSDMA_RLC2_IB_BASE_LO                                                                         0x01ed
611 #define regSDMA_RLC2_IB_BASE_LO_BASE_IDX                                                                0
612 #define regSDMA_RLC2_IB_BASE_HI                                                                         0x01ee
613 #define regSDMA_RLC2_IB_BASE_HI_BASE_IDX                                                                0
614 #define regSDMA_RLC2_IB_SIZE                                                                            0x01ef
615 #define regSDMA_RLC2_IB_SIZE_BASE_IDX                                                                   0
616 #define regSDMA_RLC2_SKIP_CNTL                                                                          0x01f0
617 #define regSDMA_RLC2_SKIP_CNTL_BASE_IDX                                                                 0
618 #define regSDMA_RLC2_CONTEXT_STATUS                                                                     0x01f1
619 #define regSDMA_RLC2_CONTEXT_STATUS_BASE_IDX                                                            0
620 #define regSDMA_RLC2_DOORBELL                                                                           0x01f2
621 #define regSDMA_RLC2_DOORBELL_BASE_IDX                                                                  0
622 #define regSDMA_RLC2_STATUS                                                                             0x0208
623 #define regSDMA_RLC2_STATUS_BASE_IDX                                                                    0
624 #define regSDMA_RLC2_DOORBELL_LOG                                                                       0x0209
625 #define regSDMA_RLC2_DOORBELL_LOG_BASE_IDX                                                              0
626 #define regSDMA_RLC2_WATERMARK                                                                          0x020a
627 #define regSDMA_RLC2_WATERMARK_BASE_IDX                                                                 0
628 #define regSDMA_RLC2_DOORBELL_OFFSET                                                                    0x020b
629 #define regSDMA_RLC2_DOORBELL_OFFSET_BASE_IDX                                                           0
630 #define regSDMA_RLC2_CSA_ADDR_LO                                                                        0x020c
631 #define regSDMA_RLC2_CSA_ADDR_LO_BASE_IDX                                                               0
632 #define regSDMA_RLC2_CSA_ADDR_HI                                                                        0x020d
633 #define regSDMA_RLC2_CSA_ADDR_HI_BASE_IDX                                                               0
634 #define regSDMA_RLC2_IB_SUB_REMAIN                                                                      0x020f
635 #define regSDMA_RLC2_IB_SUB_REMAIN_BASE_IDX                                                             0
636 #define regSDMA_RLC2_PREEMPT                                                                            0x0210
637 #define regSDMA_RLC2_PREEMPT_BASE_IDX                                                                   0
638 #define regSDMA_RLC2_DUMMY_REG                                                                          0x0211
639 #define regSDMA_RLC2_DUMMY_REG_BASE_IDX                                                                 0
640 #define regSDMA_RLC2_RB_WPTR_POLL_ADDR_HI                                                               0x0212
641 #define regSDMA_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                      0
642 #define regSDMA_RLC2_RB_WPTR_POLL_ADDR_LO                                                               0x0213
643 #define regSDMA_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                      0
644 #define regSDMA_RLC2_RB_AQL_CNTL                                                                        0x0214
645 #define regSDMA_RLC2_RB_AQL_CNTL_BASE_IDX                                                               0
646 #define regSDMA_RLC2_MINOR_PTR_UPDATE                                                                   0x0215
647 #define regSDMA_RLC2_MINOR_PTR_UPDATE_BASE_IDX                                                          0
648 #define regSDMA_RLC2_MIDCMD_DATA0                                                                       0x0220
649 #define regSDMA_RLC2_MIDCMD_DATA0_BASE_IDX                                                              0
650 #define regSDMA_RLC2_MIDCMD_DATA1                                                                       0x0221
651 #define regSDMA_RLC2_MIDCMD_DATA1_BASE_IDX                                                              0
652 #define regSDMA_RLC2_MIDCMD_DATA2                                                                       0x0222
653 #define regSDMA_RLC2_MIDCMD_DATA2_BASE_IDX                                                              0
654 #define regSDMA_RLC2_MIDCMD_DATA3                                                                       0x0223
655 #define regSDMA_RLC2_MIDCMD_DATA3_BASE_IDX                                                              0
656 #define regSDMA_RLC2_MIDCMD_DATA4                                                                       0x0224
657 #define regSDMA_RLC2_MIDCMD_DATA4_BASE_IDX                                                              0
658 #define regSDMA_RLC2_MIDCMD_DATA5                                                                       0x0225
659 #define regSDMA_RLC2_MIDCMD_DATA5_BASE_IDX                                                              0
660 #define regSDMA_RLC2_MIDCMD_DATA6                                                                       0x0226
661 #define regSDMA_RLC2_MIDCMD_DATA6_BASE_IDX                                                              0
662 #define regSDMA_RLC2_MIDCMD_DATA7                                                                       0x0227
663 #define regSDMA_RLC2_MIDCMD_DATA7_BASE_IDX                                                              0
664 #define regSDMA_RLC2_MIDCMD_DATA8                                                                       0x0228
665 #define regSDMA_RLC2_MIDCMD_DATA8_BASE_IDX                                                              0
666 #define regSDMA_RLC2_MIDCMD_DATA9                                                                       0x0229
667 #define regSDMA_RLC2_MIDCMD_DATA9_BASE_IDX                                                              0
668 #define regSDMA_RLC2_MIDCMD_DATA10                                                                      0x022a
669 #define regSDMA_RLC2_MIDCMD_DATA10_BASE_IDX                                                             0
670 #define regSDMA_RLC2_MIDCMD_CNTL                                                                        0x022b
671 #define regSDMA_RLC2_MIDCMD_CNTL_BASE_IDX                                                               0
672 #define regSDMA_RLC3_RB_CNTL                                                                            0x0238
673 #define regSDMA_RLC3_RB_CNTL_BASE_IDX                                                                   0
674 #define regSDMA_RLC3_RB_BASE                                                                            0x0239
675 #define regSDMA_RLC3_RB_BASE_BASE_IDX                                                                   0
676 #define regSDMA_RLC3_RB_BASE_HI                                                                         0x023a
677 #define regSDMA_RLC3_RB_BASE_HI_BASE_IDX                                                                0
678 #define regSDMA_RLC3_RB_RPTR                                                                            0x023b
679 #define regSDMA_RLC3_RB_RPTR_BASE_IDX                                                                   0
680 #define regSDMA_RLC3_RB_RPTR_HI                                                                         0x023c
681 #define regSDMA_RLC3_RB_RPTR_HI_BASE_IDX                                                                0
682 #define regSDMA_RLC3_RB_WPTR                                                                            0x023d
683 #define regSDMA_RLC3_RB_WPTR_BASE_IDX                                                                   0
684 #define regSDMA_RLC3_RB_WPTR_HI                                                                         0x023e
685 #define regSDMA_RLC3_RB_WPTR_HI_BASE_IDX                                                                0
686 #define regSDMA_RLC3_RB_WPTR_POLL_CNTL                                                                  0x023f
687 #define regSDMA_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX                                                         0
688 #define regSDMA_RLC3_RB_RPTR_ADDR_HI                                                                    0x0240
689 #define regSDMA_RLC3_RB_RPTR_ADDR_HI_BASE_IDX                                                           0
690 #define regSDMA_RLC3_RB_RPTR_ADDR_LO                                                                    0x0241
691 #define regSDMA_RLC3_RB_RPTR_ADDR_LO_BASE_IDX                                                           0
692 #define regSDMA_RLC3_IB_CNTL                                                                            0x0242
693 #define regSDMA_RLC3_IB_CNTL_BASE_IDX                                                                   0
694 #define regSDMA_RLC3_IB_RPTR                                                                            0x0243
695 #define regSDMA_RLC3_IB_RPTR_BASE_IDX                                                                   0
696 #define regSDMA_RLC3_IB_OFFSET                                                                          0x0244
697 #define regSDMA_RLC3_IB_OFFSET_BASE_IDX                                                                 0
698 #define regSDMA_RLC3_IB_BASE_LO                                                                         0x0245
699 #define regSDMA_RLC3_IB_BASE_LO_BASE_IDX                                                                0
700 #define regSDMA_RLC3_IB_BASE_HI                                                                         0x0246
701 #define regSDMA_RLC3_IB_BASE_HI_BASE_IDX                                                                0
702 #define regSDMA_RLC3_IB_SIZE                                                                            0x0247
703 #define regSDMA_RLC3_IB_SIZE_BASE_IDX                                                                   0
704 #define regSDMA_RLC3_SKIP_CNTL                                                                          0x0248
705 #define regSDMA_RLC3_SKIP_CNTL_BASE_IDX                                                                 0
706 #define regSDMA_RLC3_CONTEXT_STATUS                                                                     0x0249
707 #define regSDMA_RLC3_CONTEXT_STATUS_BASE_IDX                                                            0
708 #define regSDMA_RLC3_DOORBELL                                                                           0x024a
709 #define regSDMA_RLC3_DOORBELL_BASE_IDX                                                                  0
710 #define regSDMA_RLC3_STATUS                                                                             0x0260
711 #define regSDMA_RLC3_STATUS_BASE_IDX                                                                    0
712 #define regSDMA_RLC3_DOORBELL_LOG                                                                       0x0261
713 #define regSDMA_RLC3_DOORBELL_LOG_BASE_IDX                                                              0
714 #define regSDMA_RLC3_WATERMARK                                                                          0x0262
715 #define regSDMA_RLC3_WATERMARK_BASE_IDX                                                                 0
716 #define regSDMA_RLC3_DOORBELL_OFFSET                                                                    0x0263
717 #define regSDMA_RLC3_DOORBELL_OFFSET_BASE_IDX                                                           0
718 #define regSDMA_RLC3_CSA_ADDR_LO                                                                        0x0264
719 #define regSDMA_RLC3_CSA_ADDR_LO_BASE_IDX                                                               0
720 #define regSDMA_RLC3_CSA_ADDR_HI                                                                        0x0265
721 #define regSDMA_RLC3_CSA_ADDR_HI_BASE_IDX                                                               0
722 #define regSDMA_RLC3_IB_SUB_REMAIN                                                                      0x0267
723 #define regSDMA_RLC3_IB_SUB_REMAIN_BASE_IDX                                                             0
724 #define regSDMA_RLC3_PREEMPT                                                                            0x0268
725 #define regSDMA_RLC3_PREEMPT_BASE_IDX                                                                   0
726 #define regSDMA_RLC3_DUMMY_REG                                                                          0x0269
727 #define regSDMA_RLC3_DUMMY_REG_BASE_IDX                                                                 0
728 #define regSDMA_RLC3_RB_WPTR_POLL_ADDR_HI                                                               0x026a
729 #define regSDMA_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                      0
730 #define regSDMA_RLC3_RB_WPTR_POLL_ADDR_LO                                                               0x026b
731 #define regSDMA_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                      0
732 #define regSDMA_RLC3_RB_AQL_CNTL                                                                        0x026c
733 #define regSDMA_RLC3_RB_AQL_CNTL_BASE_IDX                                                               0
734 #define regSDMA_RLC3_MINOR_PTR_UPDATE                                                                   0x026d
735 #define regSDMA_RLC3_MINOR_PTR_UPDATE_BASE_IDX                                                          0
736 #define regSDMA_RLC3_MIDCMD_DATA0                                                                       0x0278
737 #define regSDMA_RLC3_MIDCMD_DATA0_BASE_IDX                                                              0
738 #define regSDMA_RLC3_MIDCMD_DATA1                                                                       0x0279
739 #define regSDMA_RLC3_MIDCMD_DATA1_BASE_IDX                                                              0
740 #define regSDMA_RLC3_MIDCMD_DATA2                                                                       0x027a
741 #define regSDMA_RLC3_MIDCMD_DATA2_BASE_IDX                                                              0
742 #define regSDMA_RLC3_MIDCMD_DATA3                                                                       0x027b
743 #define regSDMA_RLC3_MIDCMD_DATA3_BASE_IDX                                                              0
744 #define regSDMA_RLC3_MIDCMD_DATA4                                                                       0x027c
745 #define regSDMA_RLC3_MIDCMD_DATA4_BASE_IDX                                                              0
746 #define regSDMA_RLC3_MIDCMD_DATA5                                                                       0x027d
747 #define regSDMA_RLC3_MIDCMD_DATA5_BASE_IDX                                                              0
748 #define regSDMA_RLC3_MIDCMD_DATA6                                                                       0x027e
749 #define regSDMA_RLC3_MIDCMD_DATA6_BASE_IDX                                                              0
750 #define regSDMA_RLC3_MIDCMD_DATA7                                                                       0x027f
751 #define regSDMA_RLC3_MIDCMD_DATA7_BASE_IDX                                                              0
752 #define regSDMA_RLC3_MIDCMD_DATA8                                                                       0x0280
753 #define regSDMA_RLC3_MIDCMD_DATA8_BASE_IDX                                                              0
754 #define regSDMA_RLC3_MIDCMD_DATA9                                                                       0x0281
755 #define regSDMA_RLC3_MIDCMD_DATA9_BASE_IDX                                                              0
756 #define regSDMA_RLC3_MIDCMD_DATA10                                                                      0x0282
757 #define regSDMA_RLC3_MIDCMD_DATA10_BASE_IDX                                                             0
758 #define regSDMA_RLC3_MIDCMD_CNTL                                                                        0x0283
759 #define regSDMA_RLC3_MIDCMD_CNTL_BASE_IDX                                                               0
760 #define regSDMA_RLC4_RB_CNTL                                                                            0x0290
761 #define regSDMA_RLC4_RB_CNTL_BASE_IDX                                                                   0
762 #define regSDMA_RLC4_RB_BASE                                                                            0x0291
763 #define regSDMA_RLC4_RB_BASE_BASE_IDX                                                                   0
764 #define regSDMA_RLC4_RB_BASE_HI                                                                         0x0292
765 #define regSDMA_RLC4_RB_BASE_HI_BASE_IDX                                                                0
766 #define regSDMA_RLC4_RB_RPTR                                                                            0x0293
767 #define regSDMA_RLC4_RB_RPTR_BASE_IDX                                                                   0
768 #define regSDMA_RLC4_RB_RPTR_HI                                                                         0x0294
769 #define regSDMA_RLC4_RB_RPTR_HI_BASE_IDX                                                                0
770 #define regSDMA_RLC4_RB_WPTR                                                                            0x0295
771 #define regSDMA_RLC4_RB_WPTR_BASE_IDX                                                                   0
772 #define regSDMA_RLC4_RB_WPTR_HI                                                                         0x0296
773 #define regSDMA_RLC4_RB_WPTR_HI_BASE_IDX                                                                0
774 #define regSDMA_RLC4_RB_WPTR_POLL_CNTL                                                                  0x0297
775 #define regSDMA_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX                                                         0
776 #define regSDMA_RLC4_RB_RPTR_ADDR_HI                                                                    0x0298
777 #define regSDMA_RLC4_RB_RPTR_ADDR_HI_BASE_IDX                                                           0
778 #define regSDMA_RLC4_RB_RPTR_ADDR_LO                                                                    0x0299
779 #define regSDMA_RLC4_RB_RPTR_ADDR_LO_BASE_IDX                                                           0
780 #define regSDMA_RLC4_IB_CNTL                                                                            0x029a
781 #define regSDMA_RLC4_IB_CNTL_BASE_IDX                                                                   0
782 #define regSDMA_RLC4_IB_RPTR                                                                            0x029b
783 #define regSDMA_RLC4_IB_RPTR_BASE_IDX                                                                   0
784 #define regSDMA_RLC4_IB_OFFSET                                                                          0x029c
785 #define regSDMA_RLC4_IB_OFFSET_BASE_IDX                                                                 0
786 #define regSDMA_RLC4_IB_BASE_LO                                                                         0x029d
787 #define regSDMA_RLC4_IB_BASE_LO_BASE_IDX                                                                0
788 #define regSDMA_RLC4_IB_BASE_HI                                                                         0x029e
789 #define regSDMA_RLC4_IB_BASE_HI_BASE_IDX                                                                0
790 #define regSDMA_RLC4_IB_SIZE                                                                            0x029f
791 #define regSDMA_RLC4_IB_SIZE_BASE_IDX                                                                   0
792 #define regSDMA_RLC4_SKIP_CNTL                                                                          0x02a0
793 #define regSDMA_RLC4_SKIP_CNTL_BASE_IDX                                                                 0
794 #define regSDMA_RLC4_CONTEXT_STATUS                                                                     0x02a1
795 #define regSDMA_RLC4_CONTEXT_STATUS_BASE_IDX                                                            0
796 #define regSDMA_RLC4_DOORBELL                                                                           0x02a2
797 #define regSDMA_RLC4_DOORBELL_BASE_IDX                                                                  0
798 #define regSDMA_RLC4_STATUS                                                                             0x02b8
799 #define regSDMA_RLC4_STATUS_BASE_IDX                                                                    0
800 #define regSDMA_RLC4_DOORBELL_LOG                                                                       0x02b9
801 #define regSDMA_RLC4_DOORBELL_LOG_BASE_IDX                                                              0
802 #define regSDMA_RLC4_WATERMARK                                                                          0x02ba
803 #define regSDMA_RLC4_WATERMARK_BASE_IDX                                                                 0
804 #define regSDMA_RLC4_DOORBELL_OFFSET                                                                    0x02bb
805 #define regSDMA_RLC4_DOORBELL_OFFSET_BASE_IDX                                                           0
806 #define regSDMA_RLC4_CSA_ADDR_LO                                                                        0x02bc
807 #define regSDMA_RLC4_CSA_ADDR_LO_BASE_IDX                                                               0
808 #define regSDMA_RLC4_CSA_ADDR_HI                                                                        0x02bd
809 #define regSDMA_RLC4_CSA_ADDR_HI_BASE_IDX                                                               0
810 #define regSDMA_RLC4_IB_SUB_REMAIN                                                                      0x02bf
811 #define regSDMA_RLC4_IB_SUB_REMAIN_BASE_IDX                                                             0
812 #define regSDMA_RLC4_PREEMPT                                                                            0x02c0
813 #define regSDMA_RLC4_PREEMPT_BASE_IDX                                                                   0
814 #define regSDMA_RLC4_DUMMY_REG                                                                          0x02c1
815 #define regSDMA_RLC4_DUMMY_REG_BASE_IDX                                                                 0
816 #define regSDMA_RLC4_RB_WPTR_POLL_ADDR_HI                                                               0x02c2
817 #define regSDMA_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                      0
818 #define regSDMA_RLC4_RB_WPTR_POLL_ADDR_LO                                                               0x02c3
819 #define regSDMA_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                      0
820 #define regSDMA_RLC4_RB_AQL_CNTL                                                                        0x02c4
821 #define regSDMA_RLC4_RB_AQL_CNTL_BASE_IDX                                                               0
822 #define regSDMA_RLC4_MINOR_PTR_UPDATE                                                                   0x02c5
823 #define regSDMA_RLC4_MINOR_PTR_UPDATE_BASE_IDX                                                          0
824 #define regSDMA_RLC4_MIDCMD_DATA0                                                                       0x02d0
825 #define regSDMA_RLC4_MIDCMD_DATA0_BASE_IDX                                                              0
826 #define regSDMA_RLC4_MIDCMD_DATA1                                                                       0x02d1
827 #define regSDMA_RLC4_MIDCMD_DATA1_BASE_IDX                                                              0
828 #define regSDMA_RLC4_MIDCMD_DATA2                                                                       0x02d2
829 #define regSDMA_RLC4_MIDCMD_DATA2_BASE_IDX                                                              0
830 #define regSDMA_RLC4_MIDCMD_DATA3                                                                       0x02d3
831 #define regSDMA_RLC4_MIDCMD_DATA3_BASE_IDX                                                              0
832 #define regSDMA_RLC4_MIDCMD_DATA4                                                                       0x02d4
833 #define regSDMA_RLC4_MIDCMD_DATA4_BASE_IDX                                                              0
834 #define regSDMA_RLC4_MIDCMD_DATA5                                                                       0x02d5
835 #define regSDMA_RLC4_MIDCMD_DATA5_BASE_IDX                                                              0
836 #define regSDMA_RLC4_MIDCMD_DATA6                                                                       0x02d6
837 #define regSDMA_RLC4_MIDCMD_DATA6_BASE_IDX                                                              0
838 #define regSDMA_RLC4_MIDCMD_DATA7                                                                       0x02d7
839 #define regSDMA_RLC4_MIDCMD_DATA7_BASE_IDX                                                              0
840 #define regSDMA_RLC4_MIDCMD_DATA8                                                                       0x02d8
841 #define regSDMA_RLC4_MIDCMD_DATA8_BASE_IDX                                                              0
842 #define regSDMA_RLC4_MIDCMD_DATA9                                                                       0x02d9
843 #define regSDMA_RLC4_MIDCMD_DATA9_BASE_IDX                                                              0
844 #define regSDMA_RLC4_MIDCMD_DATA10                                                                      0x02da
845 #define regSDMA_RLC4_MIDCMD_DATA10_BASE_IDX                                                             0
846 #define regSDMA_RLC4_MIDCMD_CNTL                                                                        0x02db
847 #define regSDMA_RLC4_MIDCMD_CNTL_BASE_IDX                                                               0
848 #define regSDMA_RLC5_RB_CNTL                                                                            0x02e8
849 #define regSDMA_RLC5_RB_CNTL_BASE_IDX                                                                   0
850 #define regSDMA_RLC5_RB_BASE                                                                            0x02e9
851 #define regSDMA_RLC5_RB_BASE_BASE_IDX                                                                   0
852 #define regSDMA_RLC5_RB_BASE_HI                                                                         0x02ea
853 #define regSDMA_RLC5_RB_BASE_HI_BASE_IDX                                                                0
854 #define regSDMA_RLC5_RB_RPTR                                                                            0x02eb
855 #define regSDMA_RLC5_RB_RPTR_BASE_IDX                                                                   0
856 #define regSDMA_RLC5_RB_RPTR_HI                                                                         0x02ec
857 #define regSDMA_RLC5_RB_RPTR_HI_BASE_IDX                                                                0
858 #define regSDMA_RLC5_RB_WPTR                                                                            0x02ed
859 #define regSDMA_RLC5_RB_WPTR_BASE_IDX                                                                   0
860 #define regSDMA_RLC5_RB_WPTR_HI                                                                         0x02ee
861 #define regSDMA_RLC5_RB_WPTR_HI_BASE_IDX                                                                0
862 #define regSDMA_RLC5_RB_WPTR_POLL_CNTL                                                                  0x02ef
863 #define regSDMA_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX                                                         0
864 #define regSDMA_RLC5_RB_RPTR_ADDR_HI                                                                    0x02f0
865 #define regSDMA_RLC5_RB_RPTR_ADDR_HI_BASE_IDX                                                           0
866 #define regSDMA_RLC5_RB_RPTR_ADDR_LO                                                                    0x02f1
867 #define regSDMA_RLC5_RB_RPTR_ADDR_LO_BASE_IDX                                                           0
868 #define regSDMA_RLC5_IB_CNTL                                                                            0x02f2
869 #define regSDMA_RLC5_IB_CNTL_BASE_IDX                                                                   0
870 #define regSDMA_RLC5_IB_RPTR                                                                            0x02f3
871 #define regSDMA_RLC5_IB_RPTR_BASE_IDX                                                                   0
872 #define regSDMA_RLC5_IB_OFFSET                                                                          0x02f4
873 #define regSDMA_RLC5_IB_OFFSET_BASE_IDX                                                                 0
874 #define regSDMA_RLC5_IB_BASE_LO                                                                         0x02f5
875 #define regSDMA_RLC5_IB_BASE_LO_BASE_IDX                                                                0
876 #define regSDMA_RLC5_IB_BASE_HI                                                                         0x02f6
877 #define regSDMA_RLC5_IB_BASE_HI_BASE_IDX                                                                0
878 #define regSDMA_RLC5_IB_SIZE                                                                            0x02f7
879 #define regSDMA_RLC5_IB_SIZE_BASE_IDX                                                                   0
880 #define regSDMA_RLC5_SKIP_CNTL                                                                          0x02f8
881 #define regSDMA_RLC5_SKIP_CNTL_BASE_IDX                                                                 0
882 #define regSDMA_RLC5_CONTEXT_STATUS                                                                     0x02f9
883 #define regSDMA_RLC5_CONTEXT_STATUS_BASE_IDX                                                            0
884 #define regSDMA_RLC5_DOORBELL                                                                           0x02fa
885 #define regSDMA_RLC5_DOORBELL_BASE_IDX                                                                  0
886 #define regSDMA_RLC5_STATUS                                                                             0x0310
887 #define regSDMA_RLC5_STATUS_BASE_IDX                                                                    0
888 #define regSDMA_RLC5_DOORBELL_LOG                                                                       0x0311
889 #define regSDMA_RLC5_DOORBELL_LOG_BASE_IDX                                                              0
890 #define regSDMA_RLC5_WATERMARK                                                                          0x0312
891 #define regSDMA_RLC5_WATERMARK_BASE_IDX                                                                 0
892 #define regSDMA_RLC5_DOORBELL_OFFSET                                                                    0x0313
893 #define regSDMA_RLC5_DOORBELL_OFFSET_BASE_IDX                                                           0
894 #define regSDMA_RLC5_CSA_ADDR_LO                                                                        0x0314
895 #define regSDMA_RLC5_CSA_ADDR_LO_BASE_IDX                                                               0
896 #define regSDMA_RLC5_CSA_ADDR_HI                                                                        0x0315
897 #define regSDMA_RLC5_CSA_ADDR_HI_BASE_IDX                                                               0
898 #define regSDMA_RLC5_IB_SUB_REMAIN                                                                      0x0317
899 #define regSDMA_RLC5_IB_SUB_REMAIN_BASE_IDX                                                             0
900 #define regSDMA_RLC5_PREEMPT                                                                            0x0318
901 #define regSDMA_RLC5_PREEMPT_BASE_IDX                                                                   0
902 #define regSDMA_RLC5_DUMMY_REG                                                                          0x0319
903 #define regSDMA_RLC5_DUMMY_REG_BASE_IDX                                                                 0
904 #define regSDMA_RLC5_RB_WPTR_POLL_ADDR_HI                                                               0x031a
905 #define regSDMA_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                      0
906 #define regSDMA_RLC5_RB_WPTR_POLL_ADDR_LO                                                               0x031b
907 #define regSDMA_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                      0
908 #define regSDMA_RLC5_RB_AQL_CNTL                                                                        0x031c
909 #define regSDMA_RLC5_RB_AQL_CNTL_BASE_IDX                                                               0
910 #define regSDMA_RLC5_MINOR_PTR_UPDATE                                                                   0x031d
911 #define regSDMA_RLC5_MINOR_PTR_UPDATE_BASE_IDX                                                          0
912 #define regSDMA_RLC5_MIDCMD_DATA0                                                                       0x0328
913 #define regSDMA_RLC5_MIDCMD_DATA0_BASE_IDX                                                              0
914 #define regSDMA_RLC5_MIDCMD_DATA1                                                                       0x0329
915 #define regSDMA_RLC5_MIDCMD_DATA1_BASE_IDX                                                              0
916 #define regSDMA_RLC5_MIDCMD_DATA2                                                                       0x032a
917 #define regSDMA_RLC5_MIDCMD_DATA2_BASE_IDX                                                              0
918 #define regSDMA_RLC5_MIDCMD_DATA3                                                                       0x032b
919 #define regSDMA_RLC5_MIDCMD_DATA3_BASE_IDX                                                              0
920 #define regSDMA_RLC5_MIDCMD_DATA4                                                                       0x032c
921 #define regSDMA_RLC5_MIDCMD_DATA4_BASE_IDX                                                              0
922 #define regSDMA_RLC5_MIDCMD_DATA5                                                                       0x032d
923 #define regSDMA_RLC5_MIDCMD_DATA5_BASE_IDX                                                              0
924 #define regSDMA_RLC5_MIDCMD_DATA6                                                                       0x032e
925 #define regSDMA_RLC5_MIDCMD_DATA6_BASE_IDX                                                              0
926 #define regSDMA_RLC5_MIDCMD_DATA7                                                                       0x032f
927 #define regSDMA_RLC5_MIDCMD_DATA7_BASE_IDX                                                              0
928 #define regSDMA_RLC5_MIDCMD_DATA8                                                                       0x0330
929 #define regSDMA_RLC5_MIDCMD_DATA8_BASE_IDX                                                              0
930 #define regSDMA_RLC5_MIDCMD_DATA9                                                                       0x0331
931 #define regSDMA_RLC5_MIDCMD_DATA9_BASE_IDX                                                              0
932 #define regSDMA_RLC5_MIDCMD_DATA10                                                                      0x0332
933 #define regSDMA_RLC5_MIDCMD_DATA10_BASE_IDX                                                             0
934 #define regSDMA_RLC5_MIDCMD_CNTL                                                                        0x0333
935 #define regSDMA_RLC5_MIDCMD_CNTL_BASE_IDX                                                               0
936 #define regSDMA_RLC6_RB_CNTL                                                                            0x0340
937 #define regSDMA_RLC6_RB_CNTL_BASE_IDX                                                                   0
938 #define regSDMA_RLC6_RB_BASE                                                                            0x0341
939 #define regSDMA_RLC6_RB_BASE_BASE_IDX                                                                   0
940 #define regSDMA_RLC6_RB_BASE_HI                                                                         0x0342
941 #define regSDMA_RLC6_RB_BASE_HI_BASE_IDX                                                                0
942 #define regSDMA_RLC6_RB_RPTR                                                                            0x0343
943 #define regSDMA_RLC6_RB_RPTR_BASE_IDX                                                                   0
944 #define regSDMA_RLC6_RB_RPTR_HI                                                                         0x0344
945 #define regSDMA_RLC6_RB_RPTR_HI_BASE_IDX                                                                0
946 #define regSDMA_RLC6_RB_WPTR                                                                            0x0345
947 #define regSDMA_RLC6_RB_WPTR_BASE_IDX                                                                   0
948 #define regSDMA_RLC6_RB_WPTR_HI                                                                         0x0346
949 #define regSDMA_RLC6_RB_WPTR_HI_BASE_IDX                                                                0
950 #define regSDMA_RLC6_RB_WPTR_POLL_CNTL                                                                  0x0347
951 #define regSDMA_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX                                                         0
952 #define regSDMA_RLC6_RB_RPTR_ADDR_HI                                                                    0x0348
953 #define regSDMA_RLC6_RB_RPTR_ADDR_HI_BASE_IDX                                                           0
954 #define regSDMA_RLC6_RB_RPTR_ADDR_LO                                                                    0x0349
955 #define regSDMA_RLC6_RB_RPTR_ADDR_LO_BASE_IDX                                                           0
956 #define regSDMA_RLC6_IB_CNTL                                                                            0x034a
957 #define regSDMA_RLC6_IB_CNTL_BASE_IDX                                                                   0
958 #define regSDMA_RLC6_IB_RPTR                                                                            0x034b
959 #define regSDMA_RLC6_IB_RPTR_BASE_IDX                                                                   0
960 #define regSDMA_RLC6_IB_OFFSET                                                                          0x034c
961 #define regSDMA_RLC6_IB_OFFSET_BASE_IDX                                                                 0
962 #define regSDMA_RLC6_IB_BASE_LO                                                                         0x034d
963 #define regSDMA_RLC6_IB_BASE_LO_BASE_IDX                                                                0
964 #define regSDMA_RLC6_IB_BASE_HI                                                                         0x034e
965 #define regSDMA_RLC6_IB_BASE_HI_BASE_IDX                                                                0
966 #define regSDMA_RLC6_IB_SIZE                                                                            0x034f
967 #define regSDMA_RLC6_IB_SIZE_BASE_IDX                                                                   0
968 #define regSDMA_RLC6_SKIP_CNTL                                                                          0x0350
969 #define regSDMA_RLC6_SKIP_CNTL_BASE_IDX                                                                 0
970 #define regSDMA_RLC6_CONTEXT_STATUS                                                                     0x0351
971 #define regSDMA_RLC6_CONTEXT_STATUS_BASE_IDX                                                            0
972 #define regSDMA_RLC6_DOORBELL                                                                           0x0352
973 #define regSDMA_RLC6_DOORBELL_BASE_IDX                                                                  0
974 #define regSDMA_RLC6_STATUS                                                                             0x0368
975 #define regSDMA_RLC6_STATUS_BASE_IDX                                                                    0
976 #define regSDMA_RLC6_DOORBELL_LOG                                                                       0x0369
977 #define regSDMA_RLC6_DOORBELL_LOG_BASE_IDX                                                              0
978 #define regSDMA_RLC6_WATERMARK                                                                          0x036a
979 #define regSDMA_RLC6_WATERMARK_BASE_IDX                                                                 0
980 #define regSDMA_RLC6_DOORBELL_OFFSET                                                                    0x036b
981 #define regSDMA_RLC6_DOORBELL_OFFSET_BASE_IDX                                                           0
982 #define regSDMA_RLC6_CSA_ADDR_LO                                                                        0x036c
983 #define regSDMA_RLC6_CSA_ADDR_LO_BASE_IDX                                                               0
984 #define regSDMA_RLC6_CSA_ADDR_HI                                                                        0x036d
985 #define regSDMA_RLC6_CSA_ADDR_HI_BASE_IDX                                                               0
986 #define regSDMA_RLC6_IB_SUB_REMAIN                                                                      0x036f
987 #define regSDMA_RLC6_IB_SUB_REMAIN_BASE_IDX                                                             0
988 #define regSDMA_RLC6_PREEMPT                                                                            0x0370
989 #define regSDMA_RLC6_PREEMPT_BASE_IDX                                                                   0
990 #define regSDMA_RLC6_DUMMY_REG                                                                          0x0371
991 #define regSDMA_RLC6_DUMMY_REG_BASE_IDX                                                                 0
992 #define regSDMA_RLC6_RB_WPTR_POLL_ADDR_HI                                                               0x0372
993 #define regSDMA_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                      0
994 #define regSDMA_RLC6_RB_WPTR_POLL_ADDR_LO                                                               0x0373
995 #define regSDMA_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                      0
996 #define regSDMA_RLC6_RB_AQL_CNTL                                                                        0x0374
997 #define regSDMA_RLC6_RB_AQL_CNTL_BASE_IDX                                                               0
998 #define regSDMA_RLC6_MINOR_PTR_UPDATE                                                                   0x0375
999 #define regSDMA_RLC6_MINOR_PTR_UPDATE_BASE_IDX                                                          0
1000 #define regSDMA_RLC6_MIDCMD_DATA0                                                                       0x0380
1001 #define regSDMA_RLC6_MIDCMD_DATA0_BASE_IDX                                                              0
1002 #define regSDMA_RLC6_MIDCMD_DATA1                                                                       0x0381
1003 #define regSDMA_RLC6_MIDCMD_DATA1_BASE_IDX                                                              0
1004 #define regSDMA_RLC6_MIDCMD_DATA2                                                                       0x0382
1005 #define regSDMA_RLC6_MIDCMD_DATA2_BASE_IDX                                                              0
1006 #define regSDMA_RLC6_MIDCMD_DATA3                                                                       0x0383
1007 #define regSDMA_RLC6_MIDCMD_DATA3_BASE_IDX                                                              0
1008 #define regSDMA_RLC6_MIDCMD_DATA4                                                                       0x0384
1009 #define regSDMA_RLC6_MIDCMD_DATA4_BASE_IDX                                                              0
1010 #define regSDMA_RLC6_MIDCMD_DATA5                                                                       0x0385
1011 #define regSDMA_RLC6_MIDCMD_DATA5_BASE_IDX                                                              0
1012 #define regSDMA_RLC6_MIDCMD_DATA6                                                                       0x0386
1013 #define regSDMA_RLC6_MIDCMD_DATA6_BASE_IDX                                                              0
1014 #define regSDMA_RLC6_MIDCMD_DATA7                                                                       0x0387
1015 #define regSDMA_RLC6_MIDCMD_DATA7_BASE_IDX                                                              0
1016 #define regSDMA_RLC6_MIDCMD_DATA8                                                                       0x0388
1017 #define regSDMA_RLC6_MIDCMD_DATA8_BASE_IDX                                                              0
1018 #define regSDMA_RLC6_MIDCMD_DATA9                                                                       0x0389
1019 #define regSDMA_RLC6_MIDCMD_DATA9_BASE_IDX                                                              0
1020 #define regSDMA_RLC6_MIDCMD_DATA10                                                                      0x038a
1021 #define regSDMA_RLC6_MIDCMD_DATA10_BASE_IDX                                                             0
1022 #define regSDMA_RLC6_MIDCMD_CNTL                                                                        0x038b
1023 #define regSDMA_RLC6_MIDCMD_CNTL_BASE_IDX                                                               0
1024 #define regSDMA_RLC7_RB_CNTL                                                                            0x0398
1025 #define regSDMA_RLC7_RB_CNTL_BASE_IDX                                                                   0
1026 #define regSDMA_RLC7_RB_BASE                                                                            0x0399
1027 #define regSDMA_RLC7_RB_BASE_BASE_IDX                                                                   0
1028 #define regSDMA_RLC7_RB_BASE_HI                                                                         0x039a
1029 #define regSDMA_RLC7_RB_BASE_HI_BASE_IDX                                                                0
1030 #define regSDMA_RLC7_RB_RPTR                                                                            0x039b
1031 #define regSDMA_RLC7_RB_RPTR_BASE_IDX                                                                   0
1032 #define regSDMA_RLC7_RB_RPTR_HI                                                                         0x039c
1033 #define regSDMA_RLC7_RB_RPTR_HI_BASE_IDX                                                                0
1034 #define regSDMA_RLC7_RB_WPTR                                                                            0x039d
1035 #define regSDMA_RLC7_RB_WPTR_BASE_IDX                                                                   0
1036 #define regSDMA_RLC7_RB_WPTR_HI                                                                         0x039e
1037 #define regSDMA_RLC7_RB_WPTR_HI_BASE_IDX                                                                0
1038 #define regSDMA_RLC7_RB_WPTR_POLL_CNTL                                                                  0x039f
1039 #define regSDMA_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX                                                         0
1040 #define regSDMA_RLC7_RB_RPTR_ADDR_HI                                                                    0x03a0
1041 #define regSDMA_RLC7_RB_RPTR_ADDR_HI_BASE_IDX                                                           0
1042 #define regSDMA_RLC7_RB_RPTR_ADDR_LO                                                                    0x03a1
1043 #define regSDMA_RLC7_RB_RPTR_ADDR_LO_BASE_IDX                                                           0
1044 #define regSDMA_RLC7_IB_CNTL                                                                            0x03a2
1045 #define regSDMA_RLC7_IB_CNTL_BASE_IDX                                                                   0
1046 #define regSDMA_RLC7_IB_RPTR                                                                            0x03a3
1047 #define regSDMA_RLC7_IB_RPTR_BASE_IDX                                                                   0
1048 #define regSDMA_RLC7_IB_OFFSET                                                                          0x03a4
1049 #define regSDMA_RLC7_IB_OFFSET_BASE_IDX                                                                 0
1050 #define regSDMA_RLC7_IB_BASE_LO                                                                         0x03a5
1051 #define regSDMA_RLC7_IB_BASE_LO_BASE_IDX                                                                0
1052 #define regSDMA_RLC7_IB_BASE_HI                                                                         0x03a6
1053 #define regSDMA_RLC7_IB_BASE_HI_BASE_IDX                                                                0
1054 #define regSDMA_RLC7_IB_SIZE                                                                            0x03a7
1055 #define regSDMA_RLC7_IB_SIZE_BASE_IDX                                                                   0
1056 #define regSDMA_RLC7_SKIP_CNTL                                                                          0x03a8
1057 #define regSDMA_RLC7_SKIP_CNTL_BASE_IDX                                                                 0
1058 #define regSDMA_RLC7_CONTEXT_STATUS                                                                     0x03a9
1059 #define regSDMA_RLC7_CONTEXT_STATUS_BASE_IDX                                                            0
1060 #define regSDMA_RLC7_DOORBELL                                                                           0x03aa
1061 #define regSDMA_RLC7_DOORBELL_BASE_IDX                                                                  0
1062 #define regSDMA_RLC7_STATUS                                                                             0x03c0
1063 #define regSDMA_RLC7_STATUS_BASE_IDX                                                                    0
1064 #define regSDMA_RLC7_DOORBELL_LOG                                                                       0x03c1
1065 #define regSDMA_RLC7_DOORBELL_LOG_BASE_IDX                                                              0
1066 #define regSDMA_RLC7_WATERMARK                                                                          0x03c2
1067 #define regSDMA_RLC7_WATERMARK_BASE_IDX                                                                 0
1068 #define regSDMA_RLC7_DOORBELL_OFFSET                                                                    0x03c3
1069 #define regSDMA_RLC7_DOORBELL_OFFSET_BASE_IDX                                                           0
1070 #define regSDMA_RLC7_CSA_ADDR_LO                                                                        0x03c4
1071 #define regSDMA_RLC7_CSA_ADDR_LO_BASE_IDX                                                               0
1072 #define regSDMA_RLC7_CSA_ADDR_HI                                                                        0x03c5
1073 #define regSDMA_RLC7_CSA_ADDR_HI_BASE_IDX                                                               0
1074 #define regSDMA_RLC7_IB_SUB_REMAIN                                                                      0x03c7
1075 #define regSDMA_RLC7_IB_SUB_REMAIN_BASE_IDX                                                             0
1076 #define regSDMA_RLC7_PREEMPT                                                                            0x03c8
1077 #define regSDMA_RLC7_PREEMPT_BASE_IDX                                                                   0
1078 #define regSDMA_RLC7_DUMMY_REG                                                                          0x03c9
1079 #define regSDMA_RLC7_DUMMY_REG_BASE_IDX                                                                 0
1080 #define regSDMA_RLC7_RB_WPTR_POLL_ADDR_HI                                                               0x03ca
1081 #define regSDMA_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                      0
1082 #define regSDMA_RLC7_RB_WPTR_POLL_ADDR_LO                                                               0x03cb
1083 #define regSDMA_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                      0
1084 #define regSDMA_RLC7_RB_AQL_CNTL                                                                        0x03cc
1085 #define regSDMA_RLC7_RB_AQL_CNTL_BASE_IDX                                                               0
1086 #define regSDMA_RLC7_MINOR_PTR_UPDATE                                                                   0x03cd
1087 #define regSDMA_RLC7_MINOR_PTR_UPDATE_BASE_IDX                                                          0
1088 #define regSDMA_RLC7_MIDCMD_DATA0                                                                       0x03d8
1089 #define regSDMA_RLC7_MIDCMD_DATA0_BASE_IDX                                                              0
1090 #define regSDMA_RLC7_MIDCMD_DATA1                                                                       0x03d9
1091 #define regSDMA_RLC7_MIDCMD_DATA1_BASE_IDX                                                              0
1092 #define regSDMA_RLC7_MIDCMD_DATA2                                                                       0x03da
1093 #define regSDMA_RLC7_MIDCMD_DATA2_BASE_IDX                                                              0
1094 #define regSDMA_RLC7_MIDCMD_DATA3                                                                       0x03db
1095 #define regSDMA_RLC7_MIDCMD_DATA3_BASE_IDX                                                              0
1096 #define regSDMA_RLC7_MIDCMD_DATA4                                                                       0x03dc
1097 #define regSDMA_RLC7_MIDCMD_DATA4_BASE_IDX                                                              0
1098 #define regSDMA_RLC7_MIDCMD_DATA5                                                                       0x03dd
1099 #define regSDMA_RLC7_MIDCMD_DATA5_BASE_IDX                                                              0
1100 #define regSDMA_RLC7_MIDCMD_DATA6                                                                       0x03de
1101 #define regSDMA_RLC7_MIDCMD_DATA6_BASE_IDX                                                              0
1102 #define regSDMA_RLC7_MIDCMD_DATA7                                                                       0x03df
1103 #define regSDMA_RLC7_MIDCMD_DATA7_BASE_IDX                                                              0
1104 #define regSDMA_RLC7_MIDCMD_DATA8                                                                       0x03e0
1105 #define regSDMA_RLC7_MIDCMD_DATA8_BASE_IDX                                                              0
1106 #define regSDMA_RLC7_MIDCMD_DATA9                                                                       0x03e1
1107 #define regSDMA_RLC7_MIDCMD_DATA9_BASE_IDX                                                              0
1108 #define regSDMA_RLC7_MIDCMD_DATA10                                                                      0x03e2
1109 #define regSDMA_RLC7_MIDCMD_DATA10_BASE_IDX                                                             0
1110 #define regSDMA_RLC7_MIDCMD_CNTL                                                                        0x03e3
1111 #define regSDMA_RLC7_MIDCMD_CNTL_BASE_IDX                                                               0
1112 
1113 #endif
1114