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Searched refs:regSDMA0_QUEUE0_RB_WPTR_HI (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v11.c388 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_WPTR_HI, in hqd_sdma_load_v11()
393 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_WPTR_HI, in hqd_sdma_load_v11()
428 reg <= regSDMA0_QUEUE0_RB_WPTR_HI; reg++) in hqd_sdma_dump_v11()
H A Dsdma_v6_0.c218 ring->me, regSDMA0_QUEUE0_RB_WPTR_HI), in sdma_v6_0_ring_set_wptr()
500 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0); in sdma_v6_0_gfx_resume()
529 …WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(r… in sdma_v6_0_gfx_resume()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_offset.h202 #define regSDMA0_QUEUE0_RB_WPTR_HI … macro
H A Dgc_11_0_3_offset.h208 #define regSDMA0_QUEUE0_RB_WPTR_HI … macro