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Searched refs:regSDMA0_EDC_COUNTER2 (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v4_4.c124 { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
128 { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
132 { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
136 { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
144 { "SDMA_UTCL1_WR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
148 { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
152 { "SDMA_SPLIT_DATA_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
160 { "SDMA_MC_RDRET_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
211 reg_offset = sdma_v4_4_get_reg_offset(adev, instance, regSDMA0_EDC_COUNTER2); in sdma_v4_4_query_ras_error_count_by_instance()
215 sdma_v4_4_get_ras_error_count(adev, regSDMA0_EDC_COUNTER2, reg_value, in sdma_v4_4_query_ras_error_count_by_instance()
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_0_offset.h95 #define regSDMA0_EDC_COUNTER2 … macro