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Searched refs:regOTG1_OTG_DRR_TIMING_INT_STATUS (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h9155 #define regOTG1_OTG_DRR_TIMING_INT_STATUS … macro
H A Ddcn_3_1_5_offset.h8914 #define regOTG1_OTG_DRR_TIMING_INT_STATUS … macro
H A Ddcn_3_1_4_offset.h8210 #define regOTG1_OTG_DRR_TIMING_INT_STATUS … macro
H A Ddcn_3_2_1_offset.h8284 #define regOTG1_OTG_DRR_TIMING_INT_STATUS … macro
H A Ddcn_3_2_0_offset.h8285 #define regOTG1_OTG_DRR_TIMING_INT_STATUS … macro
H A Ddcn_3_1_6_offset.h9379 #define regOTG1_OTG_DRR_TIMING_INT_STATUS … macro