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Searched refs:regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h8840 #define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h7899 #define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h7973 #define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h7974 #define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h9064 #define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX … macro