Home
last modified time | relevance | path

Searched refs:regOTG0_OTG_GSL_CONTROL_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h8920 #define regOTG0_OTG_GSL_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h8681 #define regOTG0_OTG_GSL_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h7977 #define regOTG0_OTG_GSL_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h8051 #define regOTG0_OTG_GSL_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h8052 #define regOTG0_OTG_GSL_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h9144 #define regOTG0_OTG_GSL_CONTROL_BASE_IDX … macro