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Searched refs:regMPCC1_MPCC_TOP_SEL (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h6485 #define regMPCC1_MPCC_TOP_SEL … macro
H A Ddcn_3_1_5_offset.h6244 #define regMPCC1_MPCC_TOP_SEL … macro
H A Ddcn_3_1_4_offset.h13250 #define regMPCC1_MPCC_TOP_SEL … macro
H A Ddcn_3_2_1_offset.h4788 #define regMPCC1_MPCC_TOP_SEL … macro
H A Ddcn_3_2_0_offset.h4789 #define regMPCC1_MPCC_TOP_SEL … macro
H A Ddcn_3_1_6_offset.h6705 #define regMPCC1_MPCC_TOP_SEL … macro