1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Tehuti Networks(R) Network Driver
4  * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved
5  */
6 
7 #ifndef _TEHUTI_H
8 #define _TEHUTI_H
9 
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/netdevice.h>
13 #include <linux/etherdevice.h>
14 #include <linux/pci.h>
15 #include <linux/delay.h>
16 #include <linux/ethtool.h>
17 #include <linux/mii.h>
18 #include <linux/crc32.h>
19 #include <linux/uaccess.h>
20 #include <linux/in.h>
21 #include <linux/ip.h>
22 #include <linux/tcp.h>
23 #include <linux/sched.h>
24 #include <linux/tty.h>
25 #include <linux/if_vlan.h>
26 #include <linux/interrupt.h>
27 #include <linux/vmalloc.h>
28 #include <linux/firmware.h>
29 #include <asm/byteorder.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/slab.h>
32 
33 /* Compile Time Switches */
34 /* start */
35 #define BDX_TSO
36 #define BDX_LLTX
37 #define BDX_DELAY_WPTR
38 /* #define BDX_MSI */
39 /* end */
40 
41 #if !defined CONFIG_PCI_MSI
42 #   undef BDX_MSI
43 #endif
44 
45 #define BDX_DEF_MSG_ENABLE	(NETIF_MSG_DRV          | \
46 				NETIF_MSG_PROBE        | \
47 				NETIF_MSG_LINK)
48 
49 /* ioctl ops */
50 #define BDX_OP_READ  1
51 #define BDX_OP_WRITE 2
52 
53 /* RX copy break size */
54 #define BDX_COPYBREAK    257
55 
56 #define DRIVER_AUTHOR     "Tehuti Networks(R)"
57 #define BDX_DRV_DESC      "Tehuti Networks(R) Network Driver"
58 #define BDX_DRV_NAME      "tehuti"
59 #define BDX_NIC_NAME      "Tehuti 10 Giga TOE SmartNIC"
60 #define BDX_NIC2PORT_NAME "Tehuti 2-Port 10 Giga TOE SmartNIC"
61 #define BDX_DRV_VERSION   "7.29.3"
62 
63 #ifdef BDX_MSI
64 #    define BDX_MSI_STRING "msi "
65 #else
66 #    define BDX_MSI_STRING ""
67 #endif
68 
69 /* netdev tx queue len for Luxor. default value is, btw, 1000
70  * ifcontig eth1 txqueuelen 3000 - to change it at runtime */
71 #define BDX_NDEV_TXQ_LEN 3000
72 
73 /* Max MTU for Jumbo Frame mode, per tehutinetworks.net Features FAQ is 16k */
74 #define BDX_MAX_MTU	(16 * 1024)
75 
76 #define FIFO_SIZE  4096
77 #define FIFO_EXTRA_SPACE            1024
78 
79 #if BITS_PER_LONG == 64
80 #    define H32_64(x)  (u32) ((u64)(x) >> 32)
81 #    define L32_64(x)  (u32) ((u64)(x) & 0xffffffff)
82 #elif BITS_PER_LONG == 32
83 #    define H32_64(x)  0
84 #    define L32_64(x)  ((u32) (x))
85 #else				/* BITS_PER_LONG == ?? */
86 #    error BITS_PER_LONG is undefined. Must be 64 or 32
87 #endif				/* BITS_PER_LONG */
88 
89 #ifdef __BIG_ENDIAN
90 #   define CPU_CHIP_SWAP32(x) swab32(x)
91 #   define CPU_CHIP_SWAP16(x) swab16(x)
92 #else
93 #   define CPU_CHIP_SWAP32(x) (x)
94 #   define CPU_CHIP_SWAP16(x) (x)
95 #endif
96 
97 #define READ_REG(pp, reg)         readl(pp->pBdxRegs + reg)
98 #define WRITE_REG(pp, reg, val)   writel(val, pp->pBdxRegs + reg)
99 
100 #ifndef NET_IP_ALIGN
101 #   define NET_IP_ALIGN 2
102 #endif
103 
104 #ifndef NETDEV_TX_OK
105 #   define NETDEV_TX_OK 0
106 #endif
107 
108 #define LUXOR_MAX_PORT     2
109 #define BDX_MAX_RX_DONE    150
110 #define BDX_TXF_DESC_SZ    16
111 #define BDX_MAX_TX_LEVEL   (priv->txd_fifo0.m.memsz - 16)
112 #define BDX_MIN_TX_LEVEL   256
113 #define BDX_NO_UPD_PACKETS 40
114 
115 struct pci_nic {
116 	int port_num;
117 	void __iomem *regs;
118 	int irq_type;
119 	struct bdx_priv *priv[LUXOR_MAX_PORT];
120 };
121 
122 enum { IRQ_INTX, IRQ_MSI, IRQ_MSIX };
123 
124 #define PCK_TH_MULT   128
125 #define INT_COAL_MULT 2
126 
127 #define BITS_MASK(nbits)			((1<<nbits)-1)
128 #define GET_BITS_SHIFT(x, nbits, nshift)	(((x)>>nshift)&BITS_MASK(nbits))
129 #define BITS_SHIFT_MASK(nbits, nshift)		(BITS_MASK(nbits)<<nshift)
130 #define BITS_SHIFT_VAL(x, nbits, nshift)	(((x)&BITS_MASK(nbits))<<nshift)
131 #define BITS_SHIFT_CLEAR(x, nbits, nshift)	\
132 	((x)&(~BITS_SHIFT_MASK(nbits, nshift)))
133 
134 #define GET_INT_COAL(x)				GET_BITS_SHIFT(x, 15, 0)
135 #define GET_INT_COAL_RC(x)			GET_BITS_SHIFT(x, 1, 15)
136 #define GET_RXF_TH(x)				GET_BITS_SHIFT(x, 4, 16)
137 #define GET_PCK_TH(x)				GET_BITS_SHIFT(x, 4, 20)
138 
139 #define INT_REG_VAL(coal, coal_rc, rxf_th, pck_th)	\
140 	((coal)|((coal_rc)<<15)|((rxf_th)<<16)|((pck_th)<<20))
141 
142 struct fifo {
143 	dma_addr_t da;		/* physical address of fifo (used by HW) */
144 	char *va;		/* virtual address of fifo (used by SW) */
145 	u32 rptr, wptr;		/* cached values of RPTR and WPTR registers,
146 				   they're 32 bits on both 32 and 64 archs */
147 	u16 reg_CFG0, reg_CFG1;
148 	u16 reg_RPTR, reg_WPTR;
149 	u16 memsz;		/* memory size allocated for fifo */
150 	u16 size_mask;
151 	u16 pktsz;		/* skb packet size to allocate */
152 	u16 rcvno;		/* number of buffers that come from this RXF */
153 };
154 
155 struct txf_fifo {
156 	struct fifo m;		/* minimal set of variables used by all fifos */
157 };
158 
159 struct txd_fifo {
160 	struct fifo m;		/* minimal set of variables used by all fifos */
161 };
162 
163 struct rxf_fifo {
164 	struct fifo m;		/* minimal set of variables used by all fifos */
165 };
166 
167 struct rxd_fifo {
168 	struct fifo m;		/* minimal set of variables used by all fifos */
169 };
170 
171 struct rx_map {
172 	u64 dma;
173 	struct sk_buff *skb;
174 };
175 
176 struct rxdb {
177 	int *stack;
178 	struct rx_map *elems;
179 	int nelem;
180 	int top;
181 };
182 
183 union bdx_dma_addr {
184 	dma_addr_t dma;
185 	struct sk_buff *skb;
186 };
187 
188 /* Entry in the db.
189  * if len == 0 addr is dma
190  * if len != 0 addr is skb */
191 struct tx_map {
192 	union bdx_dma_addr addr;
193 	int len;
194 };
195 
196 /* tx database - implemented as circular fifo buffer*/
197 struct txdb {
198 	struct tx_map *start;	/* points to the first element */
199 	struct tx_map *end;	/* points just AFTER the last element */
200 	struct tx_map *rptr;	/* points to the next element to read */
201 	struct tx_map *wptr;	/* points to the next element to write */
202 	int size;		/* number of elements in the db */
203 };
204 
205 /*Internal stats structure*/
206 struct bdx_stats {
207 	u64 InUCast;			/* 0x7200 */
208 	u64 InMCast;			/* 0x7210 */
209 	u64 InBCast;			/* 0x7220 */
210 	u64 InPkts;			/* 0x7230 */
211 	u64 InErrors;			/* 0x7240 */
212 	u64 InDropped;			/* 0x7250 */
213 	u64 FrameTooLong;		/* 0x7260 */
214 	u64 FrameSequenceErrors;	/* 0x7270 */
215 	u64 InVLAN;			/* 0x7280 */
216 	u64 InDroppedDFE;		/* 0x7290 */
217 	u64 InDroppedIntFull;		/* 0x72A0 */
218 	u64 InFrameAlignErrors;		/* 0x72B0 */
219 
220 	/* 0x72C0-0x72E0 RSRV */
221 
222 	u64 OutUCast;			/* 0x72F0 */
223 	u64 OutMCast;			/* 0x7300 */
224 	u64 OutBCast;			/* 0x7310 */
225 	u64 OutPkts;			/* 0x7320 */
226 
227 	/* 0x7330-0x7360 RSRV */
228 
229 	u64 OutVLAN;			/* 0x7370 */
230 	u64 InUCastOctects;		/* 0x7380 */
231 	u64 OutUCastOctects;		/* 0x7390 */
232 
233 	/* 0x73A0-0x73B0 RSRV */
234 
235 	u64 InBCastOctects;		/* 0x73C0 */
236 	u64 OutBCastOctects;		/* 0x73D0 */
237 	u64 InOctects;			/* 0x73E0 */
238 	u64 OutOctects;			/* 0x73F0 */
239 };
240 
241 struct bdx_priv {
242 	void __iomem *pBdxRegs;
243 	struct net_device *ndev;
244 
245 	struct napi_struct napi;
246 
247 	/* RX FIFOs: 1 for data (full) descs, and 2 for free descs */
248 	struct rxd_fifo rxd_fifo0;
249 	struct rxf_fifo rxf_fifo0;
250 	struct rxdb *rxdb;	/* rx dbs to store skb pointers */
251 	int napi_stop;
252 
253 	/* Tx FIFOs: 1 for data desc, 1 for empty (acks) desc */
254 	struct txd_fifo txd_fifo0;
255 	struct txf_fifo txf_fifo0;
256 
257 	struct txdb txdb;
258 	int tx_level;
259 #ifdef BDX_DELAY_WPTR
260 	int tx_update_mark;
261 	int tx_noupd;
262 #endif
263 	spinlock_t tx_lock;	/* NETIF_F_LLTX mode */
264 
265 	/* rarely used */
266 	u8 port;
267 	u32 msg_enable;
268 	int stats_flag;
269 	struct bdx_stats hw_stats;
270 	struct pci_dev *pdev;
271 
272 	struct pci_nic *nic;
273 
274 	u8 txd_size;
275 	u8 txf_size;
276 	u8 rxd_size;
277 	u8 rxf_size;
278 	u32 rdintcm;
279 	u32 tdintcm;
280 };
281 
282 /* RX FREE descriptor - 64bit*/
283 struct rxf_desc {
284 	u32 info;		/* Buffer Count + Info - described below */
285 	u32 va_lo;		/* VAdr[31:0] */
286 	u32 va_hi;		/* VAdr[63:32] */
287 	u32 pa_lo;		/* PAdr[31:0] */
288 	u32 pa_hi;		/* PAdr[63:32] */
289 	u32 len;		/* Buffer Length */
290 };
291 
292 #define GET_RXD_BC(x)			GET_BITS_SHIFT((x), 5, 0)
293 #define GET_RXD_RXFQ(x)			GET_BITS_SHIFT((x), 2, 8)
294 #define GET_RXD_TO(x)			GET_BITS_SHIFT((x), 1, 15)
295 #define GET_RXD_TYPE(x)			GET_BITS_SHIFT((x), 4, 16)
296 #define GET_RXD_ERR(x)			GET_BITS_SHIFT((x), 6, 21)
297 #define GET_RXD_RXP(x)			GET_BITS_SHIFT((x), 1, 27)
298 #define GET_RXD_PKT_ID(x)		GET_BITS_SHIFT((x), 3, 28)
299 #define GET_RXD_VTAG(x)			GET_BITS_SHIFT((x), 1, 31)
300 #define GET_RXD_VLAN_ID(x)		GET_BITS_SHIFT((x), 12, 0)
301 #define GET_RXD_VLAN_TCI(x)		GET_BITS_SHIFT((x), 16, 0)
302 #define GET_RXD_CFI(x)			GET_BITS_SHIFT((x), 1, 12)
303 #define GET_RXD_PRIO(x)			GET_BITS_SHIFT((x), 3, 13)
304 
305 struct rxd_desc {
306 	u32 rxd_val1;
307 	u16 len;
308 	u16 rxd_vlan;
309 	u32 va_lo;
310 	u32 va_hi;
311 };
312 
313 /* PBL describes each virtual buffer to be */
314 /* transmitted from the host.*/
315 struct pbl {
316 	u32 pa_lo;
317 	u32 pa_hi;
318 	u32 len;
319 };
320 
321 /* First word for TXD descriptor. It means: type = 3 for regular Tx packet,
322  * hw_csum = 7 for ip+udp+tcp hw checksums */
323 #define TXD_W1_VAL(bc, checksum, vtag, lgsnd, vlan_id)	\
324 	((bc) | ((checksum)<<5) | ((vtag)<<8) | \
325 	((lgsnd)<<9) | (0x30000) | ((vlan_id)<<20))
326 
327 struct txd_desc {
328 	u32 txd_val1;
329 	u16 mss;
330 	u16 length;
331 	u32 va_lo;
332 	u32 va_hi;
333 	struct pbl pbl[];	/* Fragments */
334 } __packed;
335 
336 /* Register region size */
337 #define BDX_REGS_SIZE	  0x1000
338 
339 /* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */
340 #define regTXD_CFG1_0   0x4000
341 #define regRXF_CFG1_0   0x4010
342 #define regRXD_CFG1_0   0x4020
343 #define regTXF_CFG1_0   0x4030
344 #define regTXD_CFG0_0   0x4040
345 #define regRXF_CFG0_0   0x4050
346 #define regRXD_CFG0_0   0x4060
347 #define regTXF_CFG0_0   0x4070
348 #define regTXD_WPTR_0   0x4080
349 #define regRXF_WPTR_0   0x4090
350 #define regRXD_WPTR_0   0x40A0
351 #define regTXF_WPTR_0   0x40B0
352 #define regTXD_RPTR_0   0x40C0
353 #define regRXF_RPTR_0   0x40D0
354 #define regRXD_RPTR_0   0x40E0
355 #define regTXF_RPTR_0   0x40F0
356 #define regTXF_RPTR_3   0x40FC
357 
358 /* hardware versioning */
359 #define  FW_VER         0x5010
360 #define  SROM_VER       0x5020
361 #define  FPGA_VER       0x5030
362 #define  FPGA_SEED      0x5040
363 
364 /* Registers from 0x0100-0x0150 were remapped to 0x5100-0x5150 */
365 #define regISR regISR0
366 #define regISR0          0x5100
367 
368 #define regIMR regIMR0
369 #define regIMR0          0x5110
370 
371 #define regRDINTCM0      0x5120
372 #define regRDINTCM2      0x5128
373 
374 #define regTDINTCM0      0x5130
375 
376 #define regISR_MSK0      0x5140
377 
378 #define regINIT_SEMAPHORE 0x5170
379 #define regINIT_STATUS    0x5180
380 
381 #define regMAC_LNK_STAT  0x0200
382 #define MAC_LINK_STAT    0x4	/* Link state */
383 
384 #define regGMAC_RXF_A   0x1240
385 
386 #define regUNC_MAC0_A   0x1250
387 #define regUNC_MAC1_A   0x1260
388 #define regUNC_MAC2_A   0x1270
389 
390 #define regVLAN_0       0x1800
391 
392 #define regMAX_FRAME_A  0x12C0
393 
394 #define regRX_MAC_MCST0    0x1A80
395 #define regRX_MAC_MCST1    0x1A84
396 #define MAC_MCST_NUM       15
397 #define regRX_MCST_HASH0   0x1A00
398 #define MAC_MCST_HASH_NUM  8
399 
400 #define regVPC                  0x2300
401 #define regVIC                  0x2320
402 #define regVGLB                 0x2340
403 
404 #define regCLKPLL               0x5000
405 
406 /*for 10G only*/
407 #define regREVISION        0x6000
408 #define regSCRATCH         0x6004
409 #define regCTRLST          0x6008
410 #define regMAC_ADDR_0      0x600C
411 #define regMAC_ADDR_1      0x6010
412 #define regFRM_LENGTH      0x6014
413 #define regPAUSE_QUANT     0x6018
414 #define regRX_FIFO_SECTION 0x601C
415 #define regTX_FIFO_SECTION 0x6020
416 #define regRX_FULLNESS     0x6024
417 #define regTX_FULLNESS     0x6028
418 #define regHASHTABLE       0x602C
419 #define regMDIO_ST         0x6030
420 #define regMDIO_CTL        0x6034
421 #define regMDIO_DATA       0x6038
422 #define regMDIO_ADDR       0x603C
423 
424 #define regRST_PORT        0x7000
425 #define regDIS_PORT        0x7010
426 #define regRST_QU          0x7020
427 #define regDIS_QU          0x7030
428 
429 #define regCTRLST_TX_ENA   0x0001
430 #define regCTRLST_RX_ENA   0x0002
431 #define regCTRLST_PRM_ENA  0x0010
432 #define regCTRLST_PAD_ENA  0x0020
433 
434 #define regCTRLST_BASE     (regCTRLST_PAD_ENA|regCTRLST_PRM_ENA)
435 
436 #define regRX_FLT   0x1400
437 
438 /* TXD TXF RXF RXD  CONFIG 0x0000 --- 0x007c*/
439 #define  TX_RX_CFG1_BASE          0xffffffff	/*0-31 */
440 #define  TX_RX_CFG0_BASE          0xfffff000	/*31:12 */
441 #define  TX_RX_CFG0_RSVD          0x0ffc	/*11:2 */
442 #define  TX_RX_CFG0_SIZE          0x0003	/*1:0 */
443 
444 /*  TXD TXF RXF RXD  WRITE 0x0080 --- 0x00BC */
445 #define  TXF_WPTR_WR_PTR        0x7ff8	/*14:3 */
446 
447 /*  TXD TXF RXF RXD  READ  0x00CO --- 0x00FC */
448 #define  TXF_RPTR_RD_PTR        0x7ff8	/*14:3 */
449 
450 #define TXF_WPTR_MASK 0x7ff0	/* last 4 bits are dropped
451 				 * size is rounded to 16 */
452 
453 /*  regISR 0x0100 */
454 /*  regIMR 0x0110 */
455 #define  IMR_INPROG   0x80000000	/*31 */
456 #define  IR_LNKCHG1   0x10000000	/*28 */
457 #define  IR_LNKCHG0   0x08000000	/*27 */
458 #define  IR_GPIO      0x04000000	/*26 */
459 #define  IR_RFRSH     0x02000000	/*25 */
460 #define  IR_RSVD      0x01000000	/*24 */
461 #define  IR_SWI       0x00800000	/*23 */
462 #define  IR_RX_FREE_3 0x00400000	/*22 */
463 #define  IR_RX_FREE_2 0x00200000	/*21 */
464 #define  IR_RX_FREE_1 0x00100000	/*20 */
465 #define  IR_RX_FREE_0 0x00080000	/*19 */
466 #define  IR_TX_FREE_3 0x00040000	/*18 */
467 #define  IR_TX_FREE_2 0x00020000	/*17 */
468 #define  IR_TX_FREE_1 0x00010000	/*16 */
469 #define  IR_TX_FREE_0 0x00008000	/*15 */
470 #define  IR_RX_DESC_3 0x00004000	/*14 */
471 #define  IR_RX_DESC_2 0x00002000	/*13 */
472 #define  IR_RX_DESC_1 0x00001000	/*12 */
473 #define  IR_RX_DESC_0 0x00000800	/*11 */
474 #define  IR_PSE       0x00000400	/*10 */
475 #define  IR_TMR3      0x00000200	/*9 */
476 #define  IR_TMR2      0x00000100	/*8 */
477 #define  IR_TMR1      0x00000080	/*7 */
478 #define  IR_TMR0      0x00000040	/*6 */
479 #define  IR_VNT       0x00000020	/*5 */
480 #define  IR_RxFL      0x00000010	/*4 */
481 #define  IR_SDPERR    0x00000008	/*3 */
482 #define  IR_TR        0x00000004	/*2 */
483 #define  IR_PCIE_LINK 0x00000002	/*1 */
484 #define  IR_PCIE_TOUT 0x00000001	/*0 */
485 
486 #define  IR_EXTRA (IR_RX_FREE_0 | IR_LNKCHG0 | IR_PSE | \
487     IR_TMR0 | IR_PCIE_LINK | IR_PCIE_TOUT)
488 #define  IR_RUN (IR_EXTRA | IR_RX_DESC_0 | IR_TX_FREE_0)
489 #define  IR_ALL 0xfdfffff7
490 
491 #define  IR_LNKCHG0_ofst        27
492 
493 #define  GMAC_RX_FILTER_OSEN  0x1000	/* shared OS enable */
494 #define  GMAC_RX_FILTER_TXFC  0x0400	/* Tx flow control */
495 #define  GMAC_RX_FILTER_RSV0  0x0200	/* reserved */
496 #define  GMAC_RX_FILTER_FDA   0x0100	/* filter out direct address */
497 #define  GMAC_RX_FILTER_AOF   0x0080	/* accept over run */
498 #define  GMAC_RX_FILTER_ACF   0x0040	/* accept control frames */
499 #define  GMAC_RX_FILTER_ARUNT 0x0020	/* accept under run */
500 #define  GMAC_RX_FILTER_ACRC  0x0010	/* accept crc error */
501 #define  GMAC_RX_FILTER_AM    0x0008	/* accept multicast */
502 #define  GMAC_RX_FILTER_AB    0x0004	/* accept broadcast */
503 #define  GMAC_RX_FILTER_PRM   0x0001	/* [0:1] promiscuous mode */
504 
505 #define  MAX_FRAME_AB_VAL       0x3fff	/* 13:0 */
506 
507 #define  CLKPLL_PLLLKD          0x0200	/*9 */
508 #define  CLKPLL_RSTEND          0x0100	/*8 */
509 #define  CLKPLL_SFTRST          0x0001	/*0 */
510 
511 #define  CLKPLL_LKD             (CLKPLL_PLLLKD|CLKPLL_RSTEND)
512 
513 /*
514  * PCI-E Device Control Register (Offset 0x88)
515  * Source: Luxor Data Sheet, 7.1.3.3.3
516  */
517 #define PCI_DEV_CTRL_REG 0x88
518 #define GET_DEV_CTRL_MAXPL(x)           GET_BITS_SHIFT(x, 3, 5)
519 #define GET_DEV_CTRL_MRRS(x)            GET_BITS_SHIFT(x, 3, 12)
520 
521 /*
522  * PCI-E Link Status Register (Offset 0x92)
523  * Source: Luxor Data Sheet, 7.1.3.3.7
524  */
525 #define PCI_LINK_STATUS_REG 0x92
526 #define GET_LINK_STATUS_LANES(x)		GET_BITS_SHIFT(x, 6, 4)
527 
528 /* Debugging Macros */
529 
530 #define DBG2(fmt, args...)					\
531 	pr_err("%s:%-5d: " fmt, __func__, __LINE__, ## args)
532 
533 #define BDX_ASSERT(x) BUG_ON(x)
534 
535 #ifdef DEBUG
536 
537 #define ENTER						\
538 do {							\
539 	pr_err("%s:%-5d: ENTER\n", __func__, __LINE__); \
540 } while (0)
541 
542 #define RET(args...)					 \
543 do {							 \
544 	pr_err("%s:%-5d: RETURN\n", __func__, __LINE__); \
545 	return args;					 \
546 } while (0)
547 
548 #define DBG(fmt, args...)					\
549 	pr_err("%s:%-5d: " fmt, __func__, __LINE__, ## args)
550 #else
551 #define ENTER do {  } while (0)
552 #define RET(args...)   return args
553 #define DBG(fmt, args...)			\
554 do {						\
555 	if (0)					\
556 		pr_err(fmt, ##args);		\
557 } while (0)
558 #endif
559 
560 #endif /* _BDX__H */
561