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Searched refs:regMC_VM_MX_L1_TLB_CNTL (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v1_2.c202 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL); in gfxhub_v1_2_xcc_init_tlb_regs()
216 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v1_2_xcc_init_tlb_regs()
446 tmp = RREG32_SOC15(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL); in gfxhub_v1_2_xcc_gart_disable()
452 WREG32_SOC15_RLC(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v1_2_xcc_gart_disable()
H A Dmmhub_v1_8.c198 tmp = RREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_8_init_tlb_regs()
212 WREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v1_8_init_tlb_regs()
445 tmp = RREG32_SOC15(MMHUB, j, regMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_8_gart_disable()
450 WREG32_SOC15(MMHUB, j, regMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v1_8_gart_disable()
H A Dmmhub_v1_7.c160 tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_7_init_tlb_regs()
172 WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v1_7_init_tlb_regs()
361 tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_7_gart_disable()
367 WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp); in mmhub_v1_7_gart_disable()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_1_8_0_offset.h3136 #define regMC_VM_MX_L1_TLB_CNTL … macro
H A Dmmhub_1_7_offset.h5122 #define regMC_VM_MX_L1_TLB_CNTL … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h7388 #define regMC_VM_MX_L1_TLB_CNTL … macro
H A Dgc_9_4_3_offset.h2070 #define regMC_VM_MX_L1_TLB_CNTL … macro