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Searched refs:regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h12838 #define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX macro
H A Ddcn_3_1_5_offset.h12703 #define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX macro
H A Ddcn_3_1_4_offset.h11849 #define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX macro
H A Ddcn_3_2_1_offset.h12021 #define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX macro
H A Ddcn_3_2_0_offset.h12012 #define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX macro
H A Ddcn_3_1_6_offset.h13434 #define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX macro