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Searched refs:regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h5902 #define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h5661 #define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h6815 #define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h4509 #define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h4510 #define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h6122 #define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX … macro