Home
last modified time | relevance | path

Searched refs:regDSCL1_DSCL_MEM_PWR_STATUS (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h4517 #define regDSCL1_DSCL_MEM_PWR_STATUS … macro
H A Ddcn_3_1_5_offset.h4276 #define regDSCL1_DSCL_MEM_PWR_STATUS … macro
H A Ddcn_3_1_4_offset.h5430 #define regDSCL1_DSCL_MEM_PWR_STATUS … macro
H A Ddcn_3_2_1_offset.h3736 #define regDSCL1_DSCL_MEM_PWR_STATUS … macro
H A Ddcn_3_2_0_offset.h3737 #define regDSCL1_DSCL_MEM_PWR_STATUS … macro
H A Ddcn_3_1_6_offset.h4737 #define regDSCL1_DSCL_MEM_PWR_STATUS … macro