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Searched refs:regDSCC0_DSCC_PPS_CONFIG18 (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h12515 #define regDSCC0_DSCC_PPS_CONFIG18 … macro
H A Ddcn_3_1_5_offset.h12380 #define regDSCC0_DSCC_PPS_CONFIG18 … macro
H A Ddcn_3_1_4_offset.h11644 #define regDSCC0_DSCC_PPS_CONFIG18 … macro
H A Ddcn_3_2_1_offset.h11748 #define regDSCC0_DSCC_PPS_CONFIG18 … macro
H A Ddcn_3_2_0_offset.h11739 #define regDSCC0_DSCC_PPS_CONFIG18 … macro
H A Ddcn_3_1_6_offset.h13111 #define regDSCC0_DSCC_PPS_CONFIG18 … macro