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Searched refs:regDSCC0_DSCC_PPS_CONFIG12 (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h12503 #define regDSCC0_DSCC_PPS_CONFIG12 … macro
H A Ddcn_3_1_5_offset.h12368 #define regDSCC0_DSCC_PPS_CONFIG12 … macro
H A Ddcn_3_1_4_offset.h11632 #define regDSCC0_DSCC_PPS_CONFIG12 … macro
H A Ddcn_3_2_1_offset.h11736 #define regDSCC0_DSCC_PPS_CONFIG12 … macro
H A Ddcn_3_2_0_offset.h11727 #define regDSCC0_DSCC_PPS_CONFIG12 … macro
H A Ddcn_3_1_6_offset.h13099 #define regDSCC0_DSCC_PPS_CONFIG12 … macro