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Searched refs:regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_offset.h12477 #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS … macro
H A Ddcn_3_1_5_offset.h12342 #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS … macro
H A Ddcn_3_1_4_offset.h11606 #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS … macro
H A Ddcn_3_2_1_offset.h11710 #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS … macro
H A Ddcn_3_2_0_offset.h11701 #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS … macro
H A Ddcn_3_1_6_offset.h13073 #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS … macro